CN107978636A - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN107978636A CN107978636A CN201610939043.5A CN201610939043A CN107978636A CN 107978636 A CN107978636 A CN 107978636A CN 201610939043 A CN201610939043 A CN 201610939043A CN 107978636 A CN107978636 A CN 107978636A
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- 229910052581 Si3N4 Inorganic materials 0.000 description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof and electronic device.The described method includes：Semiconductor substrate is provided, the gate structure formed with fin and around the fin, groove is also formed with the fin of the gate structure both sides on the semiconductor substrate；The groove is filled using the dopant material comprising dopant and covers the fin and the gate structure；Annealing steps are performed, to form low-doped drain region in the fin below the gate structure.The low-doped drain region profile formed by the method is more homogeneous, more effectively controls short-channel effect (short channel effects), the performance and yield for making device improve.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.At present, due to the demand of high device density, high-performance and low cost, half
Conductor industry has advanced to nanometer technology process node, and the preparation of semiconductor devices is limited be subject to various physics limits.
Continuous with cmos device size reduces, and has promoted three dimensional design such as fin from the challenge prepared with design aspect
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, its can effectively control device it is scaled caused by the short channel for being difficult to overcome effect
Answer, the density of the transistor array formed on substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) is set, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
Low doped drain region (Light Drain Doping, LDD) is usually in PMOS and NMOS in FinFET preparation
Ion implanting is carried out before stressor layers extension in region at an oblique angle to be formed, yet with shadowing effect (shadow
Effect), it can cause the profile of doping not homogeneous enough during the ion implanting, therefore be difficult to have by the LDD
The control short-channel effect (short channel effects) of effect, the performance and yield for making device reduce.
Therefore, be to solve above-mentioned technical problem of the prior art, it is necessary to propose a kind of new semiconductor devices and its
Preparation method and electronic device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problem of presently, there are, an embodiment of the present invention provides a kind of preparation method of semiconductor devices, institute
The method of stating includes：
Semiconductor substrate is provided, on the semiconductor substrate the gate structure formed with fin and around the fin,
Groove is also formed with the fin of the gate structure both sides；
The groove is filled using the dopant material comprising dopant and covers the fin and the gate structure；
Annealing steps are performed, to form low-doped drain region in the fin below the gate structure.
Alternatively, the method still further comprises following steps：
The dopant material is removed, to expose the groove；
The epitaxial growth semiconductor material layer in the groove, to form source and drain.
Alternatively, dopant material described in rotary coating, to fill the groove and cover the fin and the grid knot
Structure.
Alternatively, the Semiconductor substrate includes NMOS area and PMOS area, in the NMOS area and the PMOS
Region is each formed with the fin and the gate structure around the fin；
The first protective layer is formed in the NMOS area, to cover the fin and the grid in the NMOS area
Pole structure；
The fin of the gate structure both sides in the PMOS area is patterned, to form the first groove；
First groove is filled using the dopant material comprising P-type dopant and covers the PMOS area；
Annealing steps are performed, to form p-type in the fin below the gate structure in the PMOS area
Low-doped drain region；
The dopant material for including the P-type dopant is removed, to expose first groove；
The first semiconductor material layer of epitaxial growth in first groove, to form PMOS lifting source and drain；
First protective layer is removed, to expose the NMOS area.
Alternatively, the method further includes：
The second protective layer is formed in the PMOS area, to cover the fin and the grid in the PMOS area
Pole structure；
The fin of the gate structure both sides in the NMOS area is patterned, to form the second groove；
Second groove is filled using the dopant material comprising N type dopant and covers the NMOS area；
Annealing steps are performed, it is low to form N-type in the fin described in the NMOS area below gate structure
Impure drain region；
The dopant material for including the N type dopant is removed, to expose second groove；
The second semiconductor material layer of epitaxial growth in second groove, to form NMOS lifting source and drain；
Second protective layer is removed, to expose the NMOS area.
Alternatively, after NMOS liftings source and drain and PMOS lifting source and drain is formed, the method still further comprises difference
The step of N-type ion implanting is carried out to the NMOS area and p-type ion implanting is carried out to the PMOS area.
Alternatively, after the N-type ion implanting and the p-type ion implanting, the method, which still further comprises, to be held
The step of row spike annealing and/or laser annealing.
Alternatively, the annealing steps include spike annealing step.
Present invention also offers a kind of semiconductor devices being prepared by the above method, the semiconductor devices bag
Include：
Semiconductor substrate；
Fin, positioned at the semiconductor substrate；
Gate structure, is set on the fin and around the fin；
Wherein, formed with low-doped drain region in the fin below the gate structure.
Present invention also offers a kind of electronic device, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology, the present invention provides a kind of preparation method of semiconductor devices,
No longer it is to be initially formed LDD in the method, re-forms groove and the epitaxial growth source and drain in the groove, but forming groove
Filling includes the dopant material of dopant afterwards, to fill the groove and the dopant is diffused to institute by annealing steps
State in the fin below gate structure, to form low-doped drain region.The low-doped drain region formed by the method
Profile is more homogeneous, more effectively controls short-channel effect (short channel effects), makes the performance and yield of device
Improve.
The semiconductor devices of the present invention, as a result of above-mentioned preparation method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is a kind of indicative flowchart of the preparation method of semiconductor devices of an alternative embodiment of the invention；
Fig. 2A-Fig. 2 I are that a kind of correlation step of the preparation method of semiconductor devices in one embodiment of the invention is formed
Structure sectional view；
Fig. 3 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
The present invention is in order to solve the problems, such as that current technique exists, there is provided a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, on the semiconductor substrate the gate structure formed with fin and around the fin,
Groove is also formed with the fin of the gate structure both sides；
The groove is filled using the dopant material comprising dopant and covers the fin and the gate structure；
Annealing steps are performed, to form low-doped drain region in the fin below the gate structure.
No longer it is to be initially formed LDD in the method, is then forming groove and the epitaxial growth source and drain in the groove,
But filling includes the dopant material of dopant afterwards in groove is formed, to fill the groove and make institute by annealing steps
State dopant to diffuse in the fin below the gate structure, to form low-doped drain region.Pass through the method shape
Into low-doped drain region profile it is more homogeneous, more effectively control short-channel effect (short channel effects), make
The performance and yield of device improve.
Alternatively, dopant material described in rotary coating, to fill the groove and cover the fin and the grid knot
Structure.
Alternatively, the Semiconductor substrate includes NMOS area and PMOS area, in the NMOS area and the PMOS
Region is each formed with the fin and the gate structure around the fin；
The first protective layer is formed in the NMOS area, to cover the fin and the grid in the NMOS area
Pole structure；
The fin of the gate structure both sides in the PMOS area is patterned, to form the first groove；
First groove is filled using the dopant material comprising P-type dopant and covers the PMOS area；
Annealing steps are performed, it is low to form p-type in the fin described in the PMOS area below gate structure
Impure drain region；
The dopant material for including P-type dopant is removed, to expose first groove；
The first semiconductor material layer of epitaxial growth in first groove, to form PMOS lifting source and drain；
First protective layer is removed, to expose the NMOS area.
Alternatively, the second protective layer is formed in the PMOS area, to cover the fin in the PMOS area
With the gate structure；
The fin of the gate structure both sides in the NMOS area is patterned, to form the second groove；
First groove is filled using the dopant material comprising N type dopant and covers the NMOS area；
Annealing steps are performed, it is low to form N-type in the fin described in the NMOS area below gate structure
Impure drain region；
The dopant material for including N type dopant is removed, to expose second groove；
The second semiconductor material layer of epitaxial growth in second groove, to form NMOS lifting source and drain；
Second protective layer is removed, to expose the NMOS area.
Wherein, the order of the above-mentioned formation NMOS liftings source and drain and the PMOS liftings source and drain can exchange.
In order to solve the problems in the existing technology, the present invention provides a kind of preparation method of semiconductor devices,
No longer it is to be initially formed LDD in the method, re-forms groove and the epitaxial growth source and drain in the groove, but forming groove
Filling includes the dopant material of dopant afterwards, to fill the groove and the dopant is diffused to institute by annealing steps
State in the fin below gate structure, to form low-doped drain region.The low-doped drain region formed by the method
Profile is more homogeneous, more effectively controls short-channel effect (short channel effects), makes the performance and yield of device
Improve.
The semiconductor devices of the present invention, as a result of above-mentioned preparation method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Embodiment one
In the following, the preparation side of the semiconductor devices of proposition of the embodiment of the present invention is described with reference to Fig. 1 and Fig. 2A to Fig. 2 I
The detailed step of one illustrative methods of method.Wherein, Fig. 1 is a kind of system of semiconductor devices of an alternative embodiment of the invention
The indicative flowchart of Preparation Method, specifically includes：
Step S1：Semiconductor substrate is provided, on the semiconductor substrate the grid formed with fin and around the fin
Pole structure, groove is also formed with the fin of the gate structure both sides；
Step S2：The groove is filled using the dopant material comprising dopant and covers the fin and the grid knot
Structure；
Step S3：Annealing steps are performed, to form low-doped drain region in the fin below the gate structure.
The preparation method of the semiconductor devices of the present embodiment, specifically comprises the following steps：
Performing step 1, there is provided Semiconductor substrate 201, the Semiconductor substrate include NMOS area and PMOS area,
The NMOS area and the PMOS area are each formed with the fin and the NMOS gate structure 202 around the fin
With PMOS gate structures 203.
Specifically, as shown in Figure 2 A, the Semiconductor substrate can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI), be laminated silicon (SSOI) on insulator, SiGe (S-SiGeOI) be laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..
The Semiconductor substrate 201 includes NMOS area and PMOS area, to form nmos device in subsequent steps
And PMOS device.
Form fleet plough groove isolation structure in the Semiconductor substrate, the forming method of the fleet plough groove isolation structure can be with
Method commonly used in the prior art is selected, such as first, sequentially forms the first oxide skin(coating) and the first nitrogen on a semiconductor substrate
Compound layer.Then, dry etch process is performed, the first nitride layer, the first oxide skin(coating) and Semiconductor substrate are carried out successively
Etch to form groove.Specifically, the figuratum photoresist layer of tool can be formed on the first nitride layer, with the photoresist layer
Dry etching is carried out to the first nitride layer for mask, to transfer a pattern to the first nitride layer, and with photoresist layer and the
Mononitride layer performs etching the first oxide skin(coating) and Semiconductor substrate for mask, to form groove.Certainly can also use
Other methods form groove, due to the technique to be known in the art, to be no longer described further.
Then, shallow trench isolated material is filled in the trench, to form fleet plough groove isolation structure.Specifically, can be
Shallow trench isolated material is formed on mononitride layer and in groove, the shallow trench isolated material can be silica, nitrogen oxidation
Silicon and/or other existing advanced low-k materials；Perform chemical mechanical milling tech and stop on the first nitride layer, with
Form the fleet plough groove isolation structure.
The Semiconductor substrate can be divided into NMOS area and PMOS area by the shallow trench isolation in the present invention.
Fin is formed in the NMOS area and PMOS area, specific steps include but not limited to：Served as a contrast in semiconductor
On bottom formed hard mask layer (not shown), formed the hard mask layer can be familiar with using those skilled in the art it is each
Kind suitable technique, such as chemical vapor deposition method, the hard mask layer can be the oxide skin(coating) that is laminated from bottom to top and
Silicon nitride layer；The hard mask layer is patterned, is formed and is used to etch Semiconductor substrate to be formed on the multiple of cylindricality fin
The mask being isolated from each other, in one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；Erosion
Semiconductor substrate is carved to be formed on cylindricality fin.
Then NMOS gate structure 202 and PMOS gate structures 203 are formed on the fin.
Wherein, the NMOS gate structure 202 and PMOS gate structures 203 can be conventional gate structure or metal gates
Structure is not limited to a certain kind.
Illustrated below exemplified by forming metal gate structure, what the embodiment was merely exemplary, including it is following
Step：
Depositing isolation material layer, to be filled up completely the gap between fin structure.In one embodiment, using with can
The chemical vapor deposition method of mobility implements the deposition.The material of spacer material layer can be with selective oxidation thing, such as HARP.
Then spacer material layer described in etch-back, to the object height of the fin.Specifically, material is isolated described in etch-back
The bed of material, with fin described in exposed portion, and then forms the fin with certain height.
Dummy gate oxide skin(coating) and dummy gate are formed on the spacer material layer, to cover the fin.Specifically
Ground, deposits dummy gate oxide skin(coating) and dummy gate material layer in this step.
Wherein, the dummy gate oxide skin(coating) can select common oxide, such as SiO2, the dummy gate material
The bed of material can select semi-conducting material commonly used in the art, such as can select polysilicon etc., it is not limited to and it is a certain, herein
Will not enumerate,
The methods of deposition process of the dummy gate material layer can select chemical vapor deposition or atomic layer deposition.
Then the dummy gate oxide skin(coating) and dummy gate material layer are patterned, to form the dummy gate around the fin.
Specifically, photoresist layer is formed in the dummy gate material layer, then exposure imaging, to form opening, so
Afterwards using the photoresist layer as dummy gate material layer described in mask etch, to form dummy gate.
Offset side wall and clearance wall are formed on the side wall of the dummy gate structure.
Specifically, the method may further include the both sides formation offset side wall (offset of the dummy gate
spacer).The material of the offset side wall is, for example, silicon nitride, the insulating materials such as silica or silicon oxynitride.With device
Size further diminishes, and the channel length of device is less and less, and the particle injection depth of source-drain electrode is also less and less, deviates side
The effect of wall is, to improve the channel length of the transistor formed, to reduce short-channel effect and caused by short-channel effect
Hot carrier's effect.The technique that offset side wall is formed in gate structure both sides can be chemical vapor deposition, in the present embodiment, institute
The thickness for stating offset side wall may diminish to 80 angstroms.
Alternatively, clearance wall is formed on the offset side wall of the dummy gate.
Specifically, on the offset side wall formed formed clearance wall (Spacer), the clearance wall can be silica,
A kind of or their combinations are formed in silicon nitride, silicon oxynitride.As embodiment in the one of the present embodiment, the clearance wall is
Silica, silicon nitride collectively constitute, and concrete technology is：The first silicon oxide layer, the first silicon nitride layer are formed on a semiconductor substrate
And second silicon oxide layer, clearance wall is then formed using engraving method.
Deposit the interlayer dielectric layer and planarize, to fill the gap between the dummy gate.
Specifically, interlevel dielectric deposition and planarize, planarization is described to interlayer dielectric layer to the dummy gate
Top.
Wherein, the interlayer dielectric layer can select dielectric material commonly used in the art, such as various oxides etc.,
Interlayer dielectric layer can select SiO in the embodiment2, its thickness is not limited to a certain numerical value.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.
The dummy gate oxide skin(coating) and the dummy gate are removed, to form groove.Specifically, the side of the removal
Method can be photoetching and etching.Gas used includes HBr in etching process, it is as main etch gas；Further include work
To etch the O of make-up gas2Or Ar, it can improve the quality of etching.
Then the method for SiCoNi is selected to remove the dummy gate oxide skin(coating), to expose the fin.In the step
In in order to reduce the damage removed during the dummy gate oxide skin(coating) to other materials layer, no longer select HF to be lost
Carve, but select the SiCoNi processing procedures of selective higher, the dummy gate oxide skin(coating) is removed by the method, will not be right
Device causes to damage.
Boundary layer, high k dielectric layer are formed in the groove.
Wherein described high k dielectric layer can select dielectric material commonly used in the art, for example, introduce in Hf02 Si, Al,
N, the element such as La, Ta and the ratio of each element is optimized obtained hafnium etc..The method for forming the high k dielectric layer can be with
It is physical gas-phase deposition or atom layer deposition process.
Work-function layer is formed on the high k dielectric layer, the work-function layer selects TiAl, then forms glue line,
Conductive layer is deposited on the glue line, the groove is filled at the same time to cover the glue line.
The conductive layer selects metal, such as W.
Wherein, the NMOS gate structure is different with the work-function layer in PMOS gate structures, can be according to the method described above
Different work-function layers is formed respectively.
After the metal gates are formed further interlayer dielectric layer described in etch-back to the gate structure both sides
Under fin, to expose the fin.
Step 2 is performed, the first protective layer is formed in the NMOS area, described in covering in the NMOS area
Fin and the gate structure, and the fin of the gate structure both sides in the PMOS area is patterned, to be formed
First groove.
Specifically, as shown in Figure 2 A, the first groove is formed in the fin of the PMOS area, it is alternatively, described
First groove is " ∑ " connected in star, can select the fin of gate structure both sides described in dry etching in this step,
CF can be selected in the dry etching4、CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas stream
Measure as CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-
150mTorr, etching period 5-120s.
Wherein, the extending direction of the gate structure is vertical with the extending direction of the fin, and first groove is set
In on the unlapped fin of the gate structure.
Wherein, the shape of first groove can also be the other shapes such as square, it is not limited to a certain.
In this step in order to avoid being impacted to the NMOS area, first described before above-mentioned steps are performed
The first protective layer is formed in NMOS area, to cover the fin and the gate structure in the NMOS area, only to institute
PMOS area is stated to be etched.
Step 3 is performed, first groove is filled using the dopant material comprising P-type dopant and covers the PMOS
Region；Annealing steps are performed, it is low-doped to form p-type in the fin described in the PMOS area below gate structure
Drain region.
Specifically, as shown in Figure 2 B, rotary coating includes the dopant material of P-type dopant, to fill first groove.
Wherein, the dopant material is the dopant material comprising B.
Spike annealing step is performed, as shown in Figure 2 C, so that the P-type dopant uniformly diffuses to the PMOS grids
In the fin below structure, with the drain region that the p-type formed in the fin is low-doped.
The method filling afterwards in the first groove is formed includes the dopant material of P-type dopant, described recessed to fill
Groove simultaneously makes the dopant diffuse in the fin below the gate structure by annealing steps, low-doped to be formed
Drain region.The low-doped drain region profile formed by the method is more homogeneous, more effectively controls short-channel effect (short
Channel effects), the performance and yield for making device improve.
Step 4 is performed, the dopant material for including P-type dopant is removed, to expose first groove；Described
The first semiconductor material layer of epitaxial growth in first groove, to form PMOS lifting source and drain.
Specifically, as shown in Figure 2 D, described in the methods of removing the dopant material, such as can passing through high-temperature oxydation removes
Dopant material.
After the dopant material is removed in first groove the first semiconductor material layer of epitaxial growth, described the
Semiconductor material layer can be SiGe layer, but be not limited to the material.
Wherein, the extension can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, different in the present invention
One kind in matter extension, molecular beam epitaxy.
Finally, first protective layer is removed, to expose the NMOS area.
Step 5 is performed, the second protective layer is formed in the PMOS area, described in covering in the PMOS area
Fin and the gate structure, and the fin of the gate structure both sides in the NMOS area is patterned, to be formed
Second groove.
Specifically, as shown in Figure 2 E, the second groove is formed in the fin of the NMOS area, it is alternatively, described
Second groove is square groove, can select the fin of the gate structure both sides described in dry etching in this step,
CF4, CHF3 can be selected in the dry etching, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas
Body flow is CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-
150mTorr, etching period 5-120s.
Wherein, the extending direction of the gate structure is vertical with the extending direction of the fin, and second groove is set
In on the unlapped fin of the gate structure.
In this step in order to avoid being impacted to the PMOS area, first described before above-mentioned steps are performed
The first protective layer is formed in PMOS area, to cover the fin and the gate structure in the PMOS area, only to institute
NMOS area is stated to be etched.
Step 6 is performed, second groove is filled using the dopant material comprising N type dopant and covers the NMOS
Region；Annealing steps are performed, it is low-doped to form N-type in the fin described in the NMOS area below gate structure
Drain region.
Specifically, as shown in Figure 2 E, rotary coating includes the dopant material of N type dopant, to fill second groove.
Wherein, the dopant material is the dopant material comprising As.
Spike annealing step is performed, as shown in Figure 2 F, so that the N type dopant uniformly diffuses to the NMOS gate
In the fin below structure, with the drain region that the N-type formed in the fin is low-doped.
The method in the second groove is formed after filling bag containing N type dopant dopant material, to fill described the
Two grooves simultaneously make the dopant diffuse in the fin below the gate structure by annealing steps, to form low-mix
Miscellaneous drain region.The low-doped drain region profile formed by the method is more homogeneous, more effectively controls short-channel effect
(short channel effects), the performance and yield for making device improve.
Step 7 is performed, the dopant material for including N type dopant is removed, to expose second groove；Described
The second semiconductor material layer of epitaxial growth in second groove, to form NMOS lifting source and drain.
Specifically, as shown in Figure 2 G, described in the methods of removing the dopant material, such as can passing through high-temperature oxydation removes
Dopant material.
After the dopant material is removed in second groove the second semiconductor material layer of epitaxial growth, described the
Two semiconductor material layers can be SiP layers, but be not limited to the material.
Wherein, the extension can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, different in the present invention
One kind in matter extension, molecular beam epitaxy.
Step 8 is performed, using second protective layer as injection masking layer, N-type ion note is carried out to the NMOS area
Enter, as illustrated in figure 2h.
Then second protective layer is removed, the 3rd protective layer is formed in the NMOS area, to cover the NMOS
Region, and using the 3rd protective layer as injection masking layer, p-type ion implanting is carried out to the PMOS area, as shown in figure 2i.
After the N-type ion implanting and the p-type ion implanting, the method still further comprises execution spike and moves back
The step of fire and/or laser annealing.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, other correlation steps can also be included, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the problems in the existing technology, the present invention provides a kind of preparation method of semiconductor devices,
No longer it is to be initially formed LDD in the method, re-forms groove and the epitaxial growth source and drain in the groove, but forming groove
In after filling include the dopant material of dopant, to fill the groove and diffuse to the dopant by annealing steps
In the fin below the gate structure, to form low-doped drain region.The low-doped leakage formed by the method
Area's profile is more homogeneous, more effectively controls short-channel effect (short channel effects), makes the performance of device and good
Rate improves.
Embodiment two
The embodiment of the present invention provides a kind of semiconductor devices, it uses the preparation method in previous embodiment one to prepare and obtains
.
The semiconductor devices includes：
Semiconductor substrate；
Fin, positioned at the semiconductor substrate；
Gate structure, is set on the fin and around the fin；
Wherein, formed with low-doped drain region in the fin below the gate structure.
Wherein, the Semiconductor substrate includes NMOS area and PMOS area, formed with NMOS in the NMOS area
Gate structure, formed with PMOS gate structures in the PMOS area.
The Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..
The Semiconductor substrate 201 includes NMOS area and PMOS area, to form nmos device in subsequent steps
And PMOS device.
Formed with fleet plough groove isolation structure in the Semiconductor substrate, the forming method of the fleet plough groove isolation structure can
To select method commonly used in the prior art,
The Semiconductor substrate can be divided into NMOS area and PMOS area by the shallow trench isolation in the present invention,
Formed with fin in the NMOS area and PMOS area.
NMOS gate structure is formed in the NMOS area, PMOS gate structures are formed in the PMOS area.
The NMOS gate structure and the both sides of PMOS gate structures side wall formed with offset side wall (offset
spacer).The material of the offset side wall is, for example, silicon nitride, the insulating materials such as silica or silicon oxynitride.With device
Size further diminishes, and the channel length of device is less and less, and the particle injection depth of source-drain electrode is also less and less, deviates side
The effect of wall is, to improve the channel length of the transistor formed, to reduce short-channel effect and caused by short-channel effect
Hot carrier's effect.The technique that offset side wall is formed in gate structure both sides can be chemical vapor deposition, in the present embodiment, institute
The thickness for stating offset side wall may diminish to 80 angstroms.
It is described into the both sides of NMOS gate and the PMOS grids formed with low-doped drain region (LDD).
Wherein, low-doped drain region forming method fills the doping material for including dopant afterwards to be described in groove is formed
Material, to fill the groove and make the dopant diffuse to the fin below the gate structure by annealing steps
In, to form low-doped drain region.The low-doped drain region profile formed by the method is more homogeneous, more effectively control
Short-channel effect (short channel effects), the performance and yield for making device improve.
In order to solve the problems in the existing technology, the present invention provides a kind of semiconductor devices, in the semiconductor
The preparation process of device is no longer to be initially formed LDD, re-forms groove and in the groove epitaxial growth source and drain, but recessed being formed
Filling includes the dopant material of dopant after in groove, to fill the groove and spread the dopant by annealing steps
In the fin below to the gate structure, to form low-doped drain region.Formed by the method low-doped
Drain region profile is more homogeneous, more effectively control short-channel effect (short channel effects), make device performance and
Yield improves.
The semiconductor devices of the present invention, as a result of above-mentioned preparation method, thus equally has the advantages that above-mentioned.
Embodiment three
The embodiment of the present invention provides a kind of electronic device, it include electronic building brick and be electrically connected with the electronic building brick partly
Conductor device.Wherein, the semiconductor devices includes the preparation method manufacture of the semiconductor devices according to embodiment one
Semiconductor devices, or the semiconductor devices described in including embodiment two.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or the semiconductor device according to embodiment one
Semiconductor devices obtained by the preparation method of part, the semiconductor devices include：Semiconductor substrate；Fin, positioned at described half
Above conductor substrate；Gate structure, is set on the fin and around the fin；Wherein, below the gate structure
The fin in formed with low-doped drain region.No longer it is to be initially formed LDD, then shape in the preparation process of the semiconductor devices
The epitaxial growth source and drain into groove and in the groove, but filling includes the dopant material of dopant after the formation of the recess,
To fill the groove and the dopant is diffused in the fin below the gate structure by annealing steps, with
Form low-doped drain region.The low-doped drain region profile formed by the method is more homogeneous, more effectively controls short ditch
Channel effect (short channel effects), the performance and yield for making device improve.
The electronic device of the present invention, as a result of above-mentioned semiconductor device, thus equally has the advantages that above-mentioned.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. preparation method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided, on the semiconductor substrate the gate structure formed with fin and around the fin, in institute State and be also formed with groove on the fin of gate structure both sides；The groove is filled using the dopant material comprising dopant and covers the fin and the gate structure；Annealing steps are performed, to form low-doped drain region in the fin below the gate structure.
- 2. according to the method described in claim 1, it is characterized in that, the method still further comprises following steps：The dopant material is removed, to expose the groove；The epitaxial growth semiconductor material layer in the groove, to form source and drain.
- 3. according to the method described in claim 1, it is characterized in that, dopant material described in rotary coating, to fill the groove And cover the fin and the gate structure.
- 4. according to the method described in claim 1, it is characterized in that, the Semiconductor substrate includes NMOS area and PMOS areas Domain, the fin and the gate structure around the fin are each formed with the NMOS area and the PMOS area；The first protective layer is formed in the NMOS area, to cover the fin and the grid knot in the NMOS area Structure；The fin of the gate structure both sides in the PMOS area is patterned, to form the first groove；First groove is filled using the dopant material comprising P-type dopant and covers the PMOS area；Annealing steps are performed, to form p-type low-mix in the fin below the gate structure in the PMOS area Miscellaneous drain region；The dopant material for including the P-type dopant is removed, to expose first groove；The first semiconductor material layer of epitaxial growth in first groove, to form PMOS lifting source and drain；First protective layer is removed, to expose the NMOS area.
- 5. according to the method described in claim 4, it is characterized in that, the method further includes：Formed in the PMOS area Second protective layer, to cover the fin and the gate structure in the PMOS area；The fin of the gate structure both sides in the NMOS area is patterned, to form the second groove；Second groove is filled using the dopant material comprising N type dopant and covers the NMOS area；Annealing steps are performed, it is low-doped to form N-type in the fin described in the NMOS area below gate structure Drain region；The dopant material for including the N type dopant is removed, to expose second groove；The second semiconductor material layer of epitaxial growth in second groove, to form NMOS lifting source and drain；Second protective layer is removed, to expose the NMOS area.
- 6. according to the method described in claim 5, it is characterized in that, formed NMOS liftings source and drain and PMOS liftings source and drain it Afterwards, the method still further comprise respectively to the NMOS area carry out N-type ion implanting and to the PMOS area into The step of row p-type ion implanting.
- 7. according to the method described in claim 6, it is characterized in that, the N-type ion implanting and the p-type ion implanting it Afterwards, the method still further comprises the step of performing spike annealing and/or laser annealing.
- 8. method according to claim 4 or 5, it is characterised in that the annealing steps include spike annealing step.
- 9. a kind of semiconductor devices being prepared by one of claim 1 to 8 the method, it is characterised in that described half Conductor device includes：Semiconductor substrate；Fin, positioned at the semiconductor substrate；Gate structure, is set on the fin and around the fin；Wherein, formed with low-doped drain region in the fin below the gate structure.
- 10. a kind of electronic device, including the semiconductor devices described in claim 9.
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| JPH11111979A (en) * | 1997-09-30 | 1999-04-23 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| KR100694391B1 (en) * | 2005-12-30 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US20070267703A1 (en) * | 2006-05-17 | 2007-11-22 | Chartered Semiconductor Manufacturing Ltd. | Strained channel transistor and method of fabrication thereof |
| CN105097546A (en) * | 2014-05-05 | 2015-11-25 | 台湾积体电路制造股份有限公司 | Method for FinFET Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11111979A (en) * | 1997-09-30 | 1999-04-23 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| KR100694391B1 (en) * | 2005-12-30 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US20070267703A1 (en) * | 2006-05-17 | 2007-11-22 | Chartered Semiconductor Manufacturing Ltd. | Strained channel transistor and method of fabrication thereof |
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