CN107978563A - A kind of semiconductor devices and preparation method, electronic device - Google Patents
A kind of semiconductor devices and preparation method, electronic device Download PDFInfo
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- CN107978563A CN107978563A CN201610919383.1A CN201610919383A CN107978563A CN 107978563 A CN107978563 A CN 107978563A CN 201610919383 A CN201610919383 A CN 201610919383A CN 107978563 A CN107978563 A CN 107978563A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 238000002360 preparation method Methods 0.000 title claims abstract description 56
- 239000000463 material Substances 0.000 claims abstract description 138
- 125000006850 spacer group Chemical group 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 175
- 238000005530 etching Methods 0.000 description 25
- 238000009792 diffusion process Methods 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000012212 insulator Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method, electronic device.The described method includes：Semiconductor substrate is provided, on the semiconductor substrate the first spacer material layer formed with several columns strip fin and the covering fin；First spacer material layer is etched to the strip fin, to form the first groove above the strip fin；On the side wall of first groove and bottom sequentially forms the first laying and clearance wall；The fin is etched, to form the second groove in the strip fin, the strip fin is divided into spaced fin structure by second groove；Remove the clearance wall；The second laying is formed on the surface of first groove and second groove, to be used as lateral etch stop layer；Form the second spacer material layer；The mask layer is removed, to expose first spacer material layer；Below first spacer material layer described in etch-back to the fin structure；Form gate structure.
Description
Technical field
The present invention relates to technical field of semiconductors, is filled in particular to a kind of semiconductor devices and preparation method, electronics
Put.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.At present, due to the demand of high device density, high-performance and low cost, half
Conductor industry has advanced to nanometer technology process node, and the preparation of semiconductor devices is limited be subject to various physics limits.
Continuous with cmos device size reduces, and the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, its can effectively control device it is scaled caused by the short channel for being difficult to overcome effect
Answer, the density of the transistor array formed on substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) is set, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
In order to further improve the density of device in FinFET techniques, many single diffusion region cut-out (single can be designed
Diffusion break, SDB) isolate to form more narrower shallow trench, to save the region of grid array.
In addition, the design generally includes control of multiple dummy gates for critical size, the usual virtual grid
Pole is arranged on the shallow plough groove isolation area that the SDB is formed, in order to improve the performance of the FinFET, usually in grid
The source and drain of the both sides of structure forms epitaxial stress layer, due to the dummy gate on the fleet plough groove isolation structure and is located at fin
The height of the grid of on piece is not consistent, therefore not accurate enough in the event of alignment offset, alignment when extension, it is easy to
Cause the profile of the epitaxial stress layer inconsistent, device performance is reduced or even is failed.
Therefore, it is necessary to a kind of new semiconductor devices and preparation method are proposed, to solve existing technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problem of presently, there are, the present invention provides a kind of preparation method of semiconductor devices, the method
Including：
Semiconductor substrate is provided, on the semiconductor substrate formed with several columns strip fin and the covering fin
The first spacer material layer；
Patterned mask layer is formed on first spacer material layer, and using the mask layer as described in mask etch
First spacer material layer is to the strip fin, to form the first groove above the strip fin；
On the side wall of first groove and bottom sequentially forms the first laying and clearance wall；
Using the clearance wall on the side wall of first groove as fin described in mask etch, with the strip fin
The strip fin is divided into spaced fin structure by the second groove of middle formation, second groove；
Remove the clearance wall；
The second laying is formed on the surface of first groove and second groove, to be used as lateral etch stop
Layer；
The second spacer material layer is formed, to fill first groove and second groove；
The mask layer is removed, to expose first spacer material layer；
Below first spacer material layer described in etch-back to the fin structure, to form the fin structure of object height；
Gate structure is formed on the fin structure and on second spacer material layer.
Alternatively, forming the method for the strip fin includes：
Hard mask stack is formed on the semiconductor substrate, and using the hard mask stack as mask patterning described half
Conductor substrate, to form strip fin described in several columns；
First spacer material layer is deposited, to fill the groove between strip fin described in several columns；
First spacer material layer is planarized to the top of the hard mask stack.
Alternatively, forming the method for first groove includes：
Oxide liner layer, the mask layer are sequentially formed on first spacer material layer and with openings patterned
Photoresist layer；
Using the photoresist layer as oxide liner layer, the mask layer and the hard mask stack described in mask etch
To the top of the strip fin, to form the first groove above the strip fin.
Alternatively, the step of forming first laying and the clearance wall includes：
On the mask layer, the side wall of first groove and bottom sequentially form the first cushioning material layer and clearance wall
Material layer；
The spacer material layer is patterned, to form the clearance wall on the side wall of the first groove.
Alternatively, forming the method for second spacer material layer includes：
Second laying is formed on the surface of the first gasket material layer surface and second groove, to be used as horizontal stroke
To etching stopping layer；
The second spacer material layer is deposited, to fill first groove and second groove and cover second pad
Layer；
Second spacer material layer is planarized to the mask layer.
Alternatively, forming the method for the fin structure of object height includes：
Below first spacer material layer described in etch-back to the hard mask stack；
The hard mask stack is removed, to expose first spacer material layer；
Again the first spacer material layer described in etch-back to object height the fin structure, while etch remove part
More than at the top of second spacer material layer to the fin structure.
Alternatively, forming the method for the gate structure includes：
Gate dielectric is formed on the surface of the fin structure；
Gate structure is formed on the gate dielectric of the fin structure, on second spacer material layer
Dummy gate structure is formed on the gate dielectric.
Alternatively, the gate dielectric, simultaneous oxidation are formed on the surface of the fin structure by the method for oxidation
Second laying, to form the gate dielectric on the surface of second spacer material layer.
Alternatively, second laying includes one kind in silicon and polysilicon.
Present invention also offers the semiconductor devices that a kind of above method is prepared, it is characterised in that the semiconductor
Device includes：
Semiconductor substrate；
Some fin structures, pass through groove in the Semiconductor substrate and on the extending direction of the fin structure
It is spaced；
Spacer material layer, is filled in the groove；
Lateral etch stop layer, positioned at the surface of the spacer material layer and wraps up the spacer material layer；
Gate structure, above the fin structure；
Dummy gate structure, positioned at the top of the spacer material layer.
Alternatively, the height of the spacer material layer below the dummy gate structure is greater than or equal to the fin knot
The height of structure.
Present invention also offers a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation side of semiconductor devices
Method, forms laying in the method in the groove between the fin structure, and formed in the groove second every
From material layer, more narrower shallow ridges are formed to form single diffusion region cut-out (single diffusion break, SDB)
Groove is isolated, and the laying and the first spacer material layer have larger etching selectivity, to be used as etching first isolation
Lateral etch stop layer during material layer, to prevent to single diffusion region cut-out (single diffusion break, SDB)
Cause to damage.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 3 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 4 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 5 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 6 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 7 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 8 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 9 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 10 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 11 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 12 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 13 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 14 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 15 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 16 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 17 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Figure 18 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, component, area,
Floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to further include using and
The different orientation of device in operation.For example, if the device upset in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation side of semiconductor devices
Method, the described method includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with several columns strip fin and the covering fin
The first spacer material layer；
Patterned mask layer is formed on first spacer material layer, and using the mask layer as described in mask etch
First spacer material layer is to the strip fin, to form the first groove above the strip fin；
On the side wall of first groove and bottom sequentially forms the first laying and clearance wall；
Using the clearance wall as fin described in mask etch, to form the second groove in the strip fin, described
The strip fin is divided into spaced fin structure by two grooves；
Remove the clearance wall；
The second laying is formed on the surface of first groove and second groove, to form lateral etch stop
Layer；
The second spacer material layer is formed, to fill first groove and second groove；
The mask layer is removed, to expose first spacer material layer；
Below first spacer material layer described in etch-back to the fin structure, to form the fin structure of object height；
Gate structure is formed on the fin structure and on second spacer material layer.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation side of semiconductor devices
Method, forms laying in the method in the groove between the fin structure, and formed in the groove second every
From material layer, more narrower shallow ridges are formed to form single diffusion region cut-out (single diffusion break, SDB)
Groove is isolated, and the laying and the first spacer material layer have larger etching selectivity, to be used as etching first isolation
Lateral etch stop layer during material layer, to prevent to single diffusion region cut-out (single diffusion break, SDB)
Cause to damage.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2 shows that the preparation method of semiconductor devices of the present invention implements institute
Obtain the diagrammatic cross-section of structure；Fig. 3 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain structure
Diagrammatic cross-section；Fig. 4 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；
Fig. 5 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；Fig. 6 shows this
The preparation method for inventing the semiconductor devices is implemented to obtain the diagrammatic cross-section of structure；Fig. 7 shows of the present invention half
The preparation method of conductor device is implemented to obtain the diagrammatic cross-section of structure；Fig. 8 shows semiconductor devices of the present invention
Preparation method is implemented to obtain the diagrammatic cross-section of structure；Fig. 9 shows that the preparation method of semiconductor devices of the present invention is real
Apply the diagrammatic cross-section of obtained structure；Figure 10 shows that the preparation method of semiconductor devices of the present invention is implemented to be tied
The diagrammatic cross-section of structure；Figure 11 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the section of structure and shows
It is intended to；Figure 12 shows that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；Figure 13
Show that the preparation method of semiconductor devices of the present invention is implemented to obtain the diagrammatic cross-section of structure；Figure 14 shows this hair
The preparation method of the bright semiconductor devices is implemented to obtain the diagrammatic cross-section of structure；Figure 15, which is shown, of the present invention partly to be led
The preparation method of body device is implemented to obtain the diagrammatic cross-section of structure；Figure 16 shows the system of semiconductor devices of the present invention
Preparation Method is implemented to obtain the diagrammatic cross-section of structure；Figure 17 shows that the preparation method of semiconductor devices of the present invention is implemented
The diagrammatic cross-section of obtained structure.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step bag of the preparation method
Include：
Step S1：Semiconductor substrate is provided, on the semiconductor substrate formed with several columns strip fin and covering
First spacer material layer of the fin；
Step S2：Patterned mask layer is formed on first spacer material layer, and using the mask layer as mask
First spacer material layer is etched to the strip fin, to form the first groove above the strip fin；
Step S3：On the side wall of first groove and bottom sequentially forms the first laying and clearance wall；
Step S4：Using the clearance wall on the side wall of first groove as fin described in mask etch, with described
The second groove is formed in strip fin, the strip fin is divided into spaced fin structure by second groove；
Step S5：Remove the clearance wall；
Step S6：The second laying is formed on the surface of first groove and second groove, to be used as horizontal erosion
Carve stop-layer；
Step S7：The second spacer material layer is formed, to fill first groove and second groove；
Step S8：The mask layer is removed, to expose first spacer material layer；
Step S9：Below first spacer material layer described in etch-back to the fin structure, to form the fin of object height
Chip architecture；
Step S10：Gate structure is formed on the fin structure and on second spacer material layer.
In the following, the embodiment of the preparation method of the semiconductor devices of the present invention is described in detail.
First, step 1 is performed, there is provided Semiconductor substrate 201, on the semiconductor substrate formed with several columns strip
First spacer material layer of fin and the covering fin.
Specifically, as shown in Fig. 2, in this step the Semiconductor substrate can be in the following material being previously mentioned extremely
Few one kind：Silicon, silicon-on-insulator (SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Semiconductor substrate 201 selects silicon in this embodiment.
Then pad oxide skin(coating) (Pad oxide) 202 is formed on the semiconductor substrate, wherein the pad oxide skin(coating)
The forming method of (Pad oxide) can be formed by the method for deposition, such as the side such as chemical vapor deposition, atomic layer deposition
Method, can also be formed, details are not described herein by the surface of Semiconductor substrate described in thermal oxide.
Further, the step of performing ion implanting can also be further included in this step, to be served as a contrast in the semiconductor
Trap is formed in bottom, wherein the ionic species and method for implanting that inject can be method commonly used in the art, herein not one by one
Repeat.
Then, some strip fins being parallel to each other are formed on a semiconductor substrate, if such as the strip fin include
Dry row, to form fin array.
Wherein, the width of fin is all identical, or fin is divided into multiple fins groups with different in width.
Hard mask layer 203 is formed on the pad oxide skin(coating) 202.
Specifically, as shown in Fig. 2, wherein, cushion of the pad oxide skin(coating) 202 as the hard mask layer 203, institute
Stating pad oxide skin(coating) 202 can solve the problems, such as that hard mask layer SiN comes off in spacer material layer etch-back process.
Wherein, the hard mask layer selects SiN.
Patterning pads oxide skin(coating) 202, hard mask layer and the Semiconductor substrate, to form some strip fins.
Specific forming method includes：Photoresist layer (not shown) is formed on a semiconductor substrate, forms the light
Photoresist layer can use the various suitable techniques that those skilled in the art are familiar with, and pattern the photoresist layer, formed and used
In etching Semiconductor substrate to be formed on multiple masks being isolated from each other of fin, then using the photoresist layer as mask
Pad oxide skin(coating) 202, hard mask layer 203 and the Semiconductor substrate 201 are etched, to form multiple fins.
Pad oxide layer is subsequently formed, to cover the surface of Semiconductor substrate, the side wall of fin structure and described hard
The side wall of mask layer and top.
In one embodiment, pad oxide layer is formed using on-site steam generation technique (ISSG).
Alternatively, the protective layer of covering pad oxide layer can also be formed in this step, with the technique of subsequent implementation
Cause damages to the height and characteristic size of fin structure.In one embodiment, using the chemical gaseous phase with flowable
Depositing operation (FCVD) forms protective layer, and the material of protective layer can be silicon nitride.
The first spacer material layer is deposited, to fill the groove between the strip fin and cover the strip fin.
In one embodiment, the deposition is implemented using the chemical vapor deposition method with flowable.First every
Material from material layer can be with selective oxidation thing, such as HARP.
Still further comprise planarization after depositing first spacer material layer the step of, for example, planarization it is described every
The step of from material layer to the hard mask layer.
Perform step 2, form patterned mask layer on first spacer material layer, and using the mask layer as
First spacer material layer described in mask etch is to the strip fin, to form the first groove above the strip fin.
Specifically, forming the method for first groove includes：
Oxide liner layer 204, the mask layer 205 are sequentially formed on first spacer material layer and there is opening
Patterned photoresist layer, as shown in Figure 3 and Figure 4；
Using the photoresist layer as oxide liner layer, the mask layer and the hard mask stack described in mask etch
The extremely top of the strip fin, to form the first groove above the strip fin, as shown in Figure 5.
The first groove described in dry etching can be selected in this step, can be with the dry etching
Select CF4、CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF4 10-
200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, during etching
Between be 5-120s.
First groove is etched to the following smaller depth in the top of the strip fin or top.
The photoresist layer is removed after first groove is formed, as shown in Figure 6.
Step 3 is performed, on the side wall of first groove and bottom sequentially forms the first laying and clearance wall.
Specifically, the step of forming first laying and the clearance wall includes：
Step 1：On the mask layer, the side wall of first groove and bottom sequentially form the first cushioning material layer and
Spacer material layer, as shown in Figure 7；
Step 2：The spacer material layer is patterned, to form the clearance wall, such as Fig. 8 on the side wall of the first groove
It is shown.
In the step 1, first laying selects oxide skin(coating).
Wherein, the spacer material layer can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
Into.As embodiment in the one of the present embodiment, the clearance wall is silica.
Method commonly used in the art can be selected in the etch process of clearance wall described in the step 2, it is not limited to certain
It is a kind of.
Step 4 is performed, using the clearance wall as fin described in mask etch, to form second in the strip fin
The strip fin is divided into spaced fin structure by groove, second groove.
Specifically, as shown in figure 8, using the clearance wall as fin described in mask etch to be formed on the strip fin
Some grooves, to form some spaced fin structures on the extending direction of the strip fin.
The second groove described in dry etching can be selected in this step, can be with the dry etching
Select CF4、CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF4 10-
200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, during etching
Between be 5-120s.
Then the clearance wall is removed, as shown in Figure 9.
Step 5 is performed, the second laying 207 is formed on the surface of first groove and second groove, to be formed
Lateral etch stop layer.
Specifically, as shown in figure 9, on first laying and the surface of second groove forms described second
Laying 207, to be used as lateral etch stop layer.
Wherein, second laying 207 selects silicon or polysilicon, it has larger with first spacer material layer
Etching selectivity, using ensure during the first spacer material layer described in follow-up etch-back its can as protection second every
Absciss layer is not by lateral etches, therefore second laying 207 protects the second separation layer as lateral etch stop layer.
Step 6 is performed, the second spacer material layer is formed, to fill first groove and second groove.
Specifically, as shown in Figure 10, the second spacer material layer is deposited in this step, to fill first groove and institute
State the second groove and cover second laying；
Second spacer material layer is planarized to the mask layer, as shown in figure 11.
The deposition is implemented using the chemical vapor deposition method with flowable.The material of second spacer material layer can
With selective oxidation thing, such as HARP.
Step 7 is performed, the mask layer is removed, to expose first spacer material layer.
Specifically, as shown in figure 12, the mask layer is removed, to expose the oxide liner layer 204 below.
Step 8 is performed, described in etch-back below the first spacer material layer to the fin structure, to form object height
Fin structure.
Specifically, forming the method for the fin structure of object height includes：
First, below the first spacer material layer described in etch-back to the hard mask stack, as shown in figure 13.
Then the hard mask stack is removed, to expose first spacer material layer, as shown in figure 14.
Finally, again the first spacer material layer described in etch-back to object height the fin structure, while etching go
More than at the top of part second spacer material layer to the fin structure, as shown in figure 15.
Second laying 207 surrounds second spacer material layer in this step, it isolates material with described first
The bed of material has larger etching selectivity, can protect the second separation layer not by lateral etches in the etching step, therefore
Second laying 207 protects the second separation layer as lateral etch stop layer.
Step 9 is performed, gate structure is formed on the fin structure and on second spacer material layer.
Specifically, as shown in figs. 16-17, forming the method for the gate structure includes：
Gate dielectric is formed on the surface of the fin structure；
Gate structure is formed on the gate dielectric of the fin structure, on second spacer material layer
Dummy gate structure is formed on the gate dielectric.
Wherein, the gate dielectric, simultaneous oxidation are formed on the surface of the fin structure by the method for oxide
Second laying, to form the gate dielectric on the surface of second spacer material layer.
Alternatively, groove is formed in the Semiconductor substrate of the gate structure both sides, alternatively, the groove is
" ∑ " connected in star, can select the first source-drain area described in dry etching in this step, can be selected in the dry etching
CF4、CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas flow is CF410-200sccm,
CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, etching period 5-
120s。
Then, the epitaxial growth stressor layers in the groove, to form source and drain, as shown in figure 13.
Further, the stressor layers select SiGe or SiC in the present invention, and the extension can be selected and subtracted in the present invention
Press one kind in extension, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, molecular beam epitaxy.
In addition, the method still further comprises the step of forming contact etch stop layer, the forming method can be with
Various methods commonly used in the art are selected, details are not described herein.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, other correlation steps can also be included, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation side of semiconductor devices
Method, forms laying in the method in the groove between the fin structure, and formed in the groove second every
From material layer, more narrower shallow ridges are formed to form single diffusion region cut-out (single diffusion break, SDB)
Groove is isolated, and the laying and the first spacer material layer have larger etching selectivity, to be used as etching first isolation
Lateral etch stop layer during material layer, to prevent to single diffusion region cut-out (single diffusion break, SDB)
Cause to damage.
Embodiment two
Present invention also offers a kind of semiconductor devices, the semiconductor devices includes：
Semiconductor substrate；
Some fin structures, pass through groove in the Semiconductor substrate and on the extending direction of the fin structure
It is spaced；
Spacer material layer, is filled in the groove；
Lateral etch stop layer, positioned at the surface of the spacer material layer and wraps up the spacer material layer；
Gate structure, above the fin structure；
Dummy gate structure, positioned at the top of the spacer material layer.
Wherein, the height of the spacer material layer below the dummy gate structure is greater than or equal to the fin structure
Height.
Wherein, the semiconductor devices includes Semiconductor substrate, and the Semiconductor substrate can be the following material being previously mentioned
At least one of material：Silicon, silicon-on-insulator (SOI), be laminated silicon (SSOI) on insulator, be laminated SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Semiconductor substrate is selected in this embodiment
Use silicon.
Specifically, on a semiconductor substrate formed with multiple fins, the width of fin is all identical, or fin is divided into tool
There are multiple fins groups of different in width.
The semiconductor devices still further comprises the gate structure set around the fin, the side wall of the grid structure
Upper formation offsets side wall and clearance wall.
The material of the offset side wall is, for example, silicon nitride, the insulating materials such as silica or silicon oxynitride.With device
Size further diminishes, and the channel length of device is less and less, and the particle injection depth of source-drain electrode is also less and less, deviates side
The effect of wall is, to improve the channel length of the transistor formed, to reduce short-channel effect and caused by short-channel effect
Hot carrier's effect.
Formed with clearance wall (Spacer) on the offset side wall formed, the clearance wall can be silica, nitridation
A kind of or their combinations are formed in silicon, silicon oxynitride.
In the both sides of the gate structure formed with lifting source and drain.The gate structure includes boundary layer, in the present invention
Select ozone to carry out chemical oxidation to the Semiconductor substrate, form boundary layer.
It is described partly to lead the present invention provides a kind of semiconductor devices in order to solve the above problem present in current technique
Body device forms laying in the groove in preparation process between the fin structure, and forms second in the groove
Spacer material layer is more narrower shallow to be formed to form single diffusion region cut-out (single diffusion break, SDB)
Trench isolations, the laying and the first spacer material layer have larger etching selectivity, using as etching described first every
Lateral etch stop layer during from material layer, with prevent to the single diffusion region cut-out (single diffusion break,
SDB) cause to damage.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has the advantages that above-mentioned.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic device, it includes semiconductor devices, which is
Semiconductor devices in previous embodiment two, or half obtained by the preparation method of semiconductor devices according to embodiment one
Conductor device.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
Due to including semiconductor devices part have higher performance, which equally has the advantages that above-mentioned.
Wherein, Figure 14 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, is included in shell 301
In display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or the semiconductor device according to embodiment one
Semiconductor devices obtained by the preparation method of part, the semiconductor devices include Semiconductor substrate；Some fin structures, are located at
It is in the Semiconductor substrate and spaced by groove on the extending direction of the fin structure；Spacer material layer, filling
In the groove；Lateral etch stop layer, positioned at the surface of the spacer material layer and wraps up the spacer material layer；Grid
Structure, above the fin structure；Dummy gate structure, positioned at the top of the spacer material layer.The semiconductor device
Part forms laying in the groove in preparation process between the fin structure, and the second isolation is formed in the groove
Material layer, more narrower shallow trench are formed to form single diffusion region cut-out (single diffusion break, SDB)
Isolation, the laying and the first spacer material layer have larger etching selectivity, to be used as etching the first isolation material
Lateral etch stop layer during the bed of material, to prevent from making single diffusion region cut-out (single diffusion break, SDB)
Into damage.
The electronic device of the present invention, as a result of above-mentioned semiconductor device, thus equally has the advantages that above-mentioned.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
- A kind of 1. preparation method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided, on the semiconductor substrate the formed with several columns strip fin and the covering fin One spacer material layer；Patterned mask layer is formed on first spacer material layer, and using the mask layer as described in mask etch first Spacer material layer is to the strip fin, to form the first groove above the strip fin；On the side wall of first groove and bottom sequentially forms the first laying and clearance wall；Using the clearance wall on the side wall of first groove as fin described in mask etch, with the shape in the strip fin Into the second groove, the strip fin is divided into spaced fin structure by second groove；Remove the clearance wall；The second laying is formed on the surface of first groove and second groove, to be used as lateral etch stop layer；The second spacer material layer is formed, to fill first groove and second groove；The mask layer is removed, to expose first spacer material layer；Below first spacer material layer described in etch-back to the fin structure, to form the fin structure of object height；Gate structure is formed on the fin structure and on second spacer material layer.
- 2. according to the method described in claim 1, it is characterized in that, forming the method for the strip fin includes：Hard mask stack is formed on the semiconductor substrate, and using the hard mask stack as the mask patterning semiconductor Substrate, to form strip fin described in several columns；First spacer material layer is deposited, to fill the groove between strip fin described in several columns；First spacer material layer is planarized to the top of the hard mask stack.
- 3. according to the method described in claim 2, it is characterized in that, forming the method for first groove includes：Oxide liner layer, the mask layer are sequentially formed on first spacer material layer and there is openings patterned light Photoresist layer；Using the photoresist layer as oxide liner layer, the mask layer and the hard mask stack described in mask etch to institute The top of strip fin is stated, to form the first groove above the strip fin.
- 4. according to the method described in claim 1, it is characterized in that, the step of forming first laying and the clearance wall Including：On the mask layer, the side wall of first groove and bottom sequentially form the first cushioning material layer and spacer material Layer；The spacer material layer is patterned, to form the clearance wall on the side wall of the first groove.
- 5. the method according to claim 1 or 4, it is characterised in that forming the method for second spacer material layer includes：Second laying is formed on the surface of the first gasket material layer surface and second groove, to be used as horizontal erosion Carve stop-layer；The second spacer material layer is deposited, to fill first groove and second groove and cover second laying；Second spacer material layer is planarized to the mask layer.
- 6. according to the method described in claim 2, it is characterized in that, forming the method for the fin structure of object height includes：Below first spacer material layer described in etch-back to the hard mask stack；The hard mask stack is removed, to expose first spacer material layer；Again the first spacer material layer described in etch-back to object height the fin structure, while etch remove part described in More than at the top of second spacer material layer to the fin structure.
- 7. according to the method described in claim 1, it is characterized in that, forming the method for the gate structure includes：Gate dielectric is formed on the surface of the fin structure；Gate structure is formed on the gate dielectric of the fin structure, described on second spacer material layer Dummy gate structure is formed on gate dielectric.
- 8. the method according to the description of claim 7 is characterized in that by the method for oxidation the fin structure surface shape Into the gate dielectric, the second laying described in simultaneous oxidation is described to be formed on the surface of second spacer material layer Gate dielectric.
- 9. according to the method described in claim 1, it is characterized in that, second laying includes one in silicon and polysilicon Kind.
- 10. a kind of semiconductor devices being prepared based on one of claim 1 to 9 the method, it is characterised in that described half Conductor device includes：Semiconductor substrate；Some fin structures, it is mutual by groove in the Semiconductor substrate and on the extending direction of the fin structure Interval；Spacer material layer, is filled in the groove；Lateral etch stop layer, positioned at the surface of the spacer material layer and wraps up the spacer material layer；Gate structure, above the fin structure；Dummy gate structure, positioned at the top of the spacer material layer.
- 11. semiconductor devices according to claim 10, it is characterised in that below the dummy gate structure it is described every Height from material layer is greater than or equal to the height of the fin structure.
- 12. a kind of electronic device, it is characterised in that the electronic device includes the semiconductor described in one of claim 10 to 11 Device.
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| CN110875191A (en) * | 2019-11-28 | 2020-03-10 | 上海华力集成电路制造有限公司 | Method for manufacturing fin type transistor |
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