CN110867413A - Method for forming single diffusion region cut - Google Patents
Method for forming single diffusion region cut Download PDFInfo
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- CN110867413A CN110867413A CN201911132956.6A CN201911132956A CN110867413A CN 110867413 A CN110867413 A CN 110867413A CN 201911132956 A CN201911132956 A CN 201911132956A CN 110867413 A CN110867413 A CN 110867413A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a forming method for cutting off a single diffusion region, and relates to the field of semiconductor manufacturing. The method comprises the following steps: forming a plurality of strip fins and a virtual grid on a silicon substrate, wherein side walls are formed on two sides of the virtual grid; forming a source electrode and a drain electrode on the strip-shaped fin; depositing an interlayer dielectric layer, and performing CMP on the interlayer dielectric layer to expose the top of the virtual grid; replacing the dummy gate with a metal gate; etching the top of the metal gate to obtain a contact window; carrying out a photoetching process to expose part of the metal grid, wherein the exposed metal grid is used for manufacturing a single diffusion region for cutting off; etching the exposed metal grid and the silicon below the exposed metal grid to form a single diffusion region groove; and depositing a filling material and carrying out CMP to form the single diffusion region cutting, wherein the filling material is used for filling the contact window and the single diffusion region groove. The problem that the performance of a device is easily poor due to the existing single diffusion region cutting method is solved; the effect of improving the performance and the yield of the device is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for forming single diffusion region cutting.
Background
With the continuous development of semiconductor technology, the size of CMOS devices is also continuously reduced. Since the line width of the gate is also reduced when the CMOS device is scaled down, the source and the drain are easily leaked, and the saturation current of the CMOS device is difficult to increase, the CMOS device is developed from a two-dimensional planar type to a three-dimensional type, and a fin field effect transistor (FinFET) is developed accordingly. The FinFET technology can be used for 22nm and below technology nodes, and in order to increase the device density in the FinFET process, a plurality of Single Diffusion Breaks (SDB) are used to form more narrower shallow trench isolations, so as to save the area of the gate array.
In general, the single diffusion region is cut off before the fin is manufactured, but the method easily causes the source and drain epitaxial surface to have a unfilled corner and the formed source and drain to be asymmetric, and the etching difficulty is increased due to the high aspect ratio, and the source and drain are easy to leak electricity; in addition, a larger virtual grid needs to be covered above the cut part of the existing single diffusion region to avoid high leakage current generated by the subsequent process, but the window between the metal grid and the metal layer contact hole is reduced; the above problems all result in the performance of the device being affected.
Disclosure of Invention
The application provides a method for forming single diffusion region cut-off, which can solve the problem that the performance of a device formed with the single diffusion region cut-off in the related art is poor.
In one aspect, an embodiment of the present application provides a method for forming a single diffusion region cut, where the method includes:
forming a plurality of strip fins and a virtual grid on a silicon substrate, wherein side walls are formed on two sides of the virtual grid;
forming a source electrode and a drain electrode on the strip-shaped fin;
depositing an interlayer dielectric layer, and carrying out Chemical Mechanical Planarization (CMP) on the interlayer dielectric layer to expose the top of the virtual grid;
replacing the dummy gate with a metal gate;
etching the top of the metal gate to obtain a contact window;
carrying out a photoetching process to expose part of the metal grid, wherein the exposed metal grid is used for manufacturing a single diffusion region for cutting off;
etching the exposed metal grid and the silicon below the exposed metal grid to form a single diffusion region groove;
and depositing a filling material and carrying out CMP to form the single diffusion region cutting, wherein the filling material is used for filling the contact window and the single diffusion region groove.
Optionally, replacing the dummy gate with a metal gate includes:
removing the virtual grid electrode through photoetching and etching processes to form a groove;
and depositing an interface oxide layer, a high-k dielectric layer and a metal layer, and forming a metal gate in the trench.
Optionally, etching the exposed metal gate and the silicon under the exposed metal gate to form a single diffusion region trench, including:
etching to remove the exposed metal gate;
and etching the exposed silicon below the metal gate to a preset depth to form a single diffusion region groove.
Optionally, the etching to remove the exposed metal gate includes:
and removing the exposed metal gate by a dry etching or wet etching process.
Alternatively, the single diffusion cutoff is 300 to 2000 angstroms deep.
Optionally, the filling material is any one of silicon nitride, silicon oxycarbonitride, silicon dioxide, silicon carbonitride and polysilicon.
Optionally, depositing a filling material and performing CMP to form a single diffusion region cut, where the filling material is used to fill the contact window and the single diffusion region trench, and includes:
removing the photoresist or the hard mask in the photoetching process;
and depositing a filling material and carrying out CMP to form the single diffusion region cutting, wherein the filling material is used for filling the contact window and the single diffusion region groove.
Optionally, the interlayer dielectric layer is made of silicon oxynitride or silicon dioxide. The technical scheme at least comprises the following advantages:
forming a strip-shaped fin and a virtual grid on a silicon substrate, forming a source electrode and a drain electrode on the strip-shaped fin, depositing an interlayer dielectric layer, performing CMP (chemical mechanical polishing), exposing the top of the virtual grid, replacing the virtual grid with a metal grid, etching the top of the metal grid to obtain a contact window, performing a photoetching process, exposing the metal grid for manufacturing single diffusion region cutting, etching the exposed metal grid and silicon below the metal grid to form a single diffusion region groove, depositing a filling material to fill the contact window on the top of the metal grid and the single diffusion region groove, performing CMP until the interlayer dielectric layer is exposed, and forming single diffusion region cutting on the silicon substrate; the method changes the process stage of the cutting formation of the single diffusion region, and solves the problem that the performance of a device is easily poor due to the existing method for cutting the single diffusion region; the effect of improving the performance and the yield of the device is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for forming a single diffusion cutoff provided in an embodiment of the present application;
FIG. 2 is a top view of a silicon substrate with a stripe fin and a gate in a positional relationship;
fig. 3 is a schematic diagram illustrating an implementation of a method for forming a single diffusion region cut according to an embodiment of the present application;
fig. 4 is a schematic implementation diagram of a method for forming a single diffusion region cut according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating an implementation of a method for forming a single diffusion region cut according to an embodiment of the present application;
fig. 6 is a schematic implementation diagram of a method for forming a single diffusion region cut according to an embodiment of the present application;
FIG. 7 is a flow chart of another method for forming a single diffusion cutoff provided by an embodiment of the present application;
wherein 21 denotes a strip fin; 22 denotes a gate electrode; 23 denotes a source/drain; 24 denotes a sidewall; 25 denotes an interlayer dielectric layer; 26 denotes an interface oxide layer; 27 denotes a high-k dielectric layer; 28 denotes a metal layer; 29 denotes a contact window; 30 denotes photoresist/hard mask; 31 denotes a single diffusion region trench; and 32 a filler material.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for forming a single diffusion region cut according to an embodiment of the present application is shown, as shown in fig. 1, the method includes the following steps:
Forming a plurality of strip fins on a silicon substrate, then forming a plurality of virtual grids, and forming side walls on two sides of each virtual grid.
Generally, a plurality of strip-shaped fins are parallel to each other, a plurality of virtual grids are parallel to each other, and the virtual grids are perpendicular to the strip-shaped fins; the dummy gate covers a portion of the strip fin.
The dummy gate is used for manufacturing the metal gate. The dummy gate includes a polysilicon gate and a temporary gate oxide layer.
As shown in fig. 2, the silicon wafer includes a plurality of strip fins 21 and a plurality of gates 22.
And 102, forming a source electrode and a drain electrode on the strip-shaped fins.
And forming a source electrode and a drain electrode on the plurality of strip-shaped fins through photoetching and ion implantation processes.
And 103, depositing an interlayer dielectric layer, and performing CMP on the interlayer dielectric layer to expose the top of the virtual grid.
Depositing an interlayer dielectric layer on the surface of the silicon wafer, then performing Chemical Mechanical Planarization (CMP) on the interlayer dielectric layer, and stopping the CMP when the top of the dummy gate is exposed.
And step 104, replacing the virtual grid with a metal grid.
And 105, etching the top of the metal grid to obtain a contact window.
As shown in fig. 3, a portion of the top of the metal gate is etched away, resulting in a contact window 29.
And 106, carrying out a photoetching process to expose part of the metal grid, wherein the exposed metal grid is used for manufacturing a single diffusion region and cutting off.
As shown in fig. 4, the portion where the single diffusion region cut is not required to be made is covered, and the metal gate for making the single diffusion region cut is not covered.
The position and the number of the exposed metal gates are determined according to the position and the number of the single diffusion region cutting.
As shown in fig. 5, the exposed metal gate is etched away and the silicon under the metal gate is etched to form a single diffusion region trench 31.
As shown in fig. 6, after the filling material 32 is deposited, CMP is performed on the filling material, and when the interlayer dielectric layer 25 is exposed, the CMP is stopped, thereby completing the fabrication of the single diffusion region cut.
In summary, the embodiment of the present application provides a method for manufacturing a single diffusion region on a silicon substrate, including forming a strip fin and a dummy gate on the silicon substrate, forming a source and a drain on the strip fin, depositing an interlayer dielectric layer and performing CMP, exposing the top of the dummy gate, replacing the dummy gate with a metal gate, etching the top of the metal gate to obtain a contact window, performing a photolithography process to expose the metal gate for manufacturing a single diffusion region cut, etching the exposed metal gate and silicon below the metal gate to form a single diffusion region trench, depositing a filling material to fill the contact window at the top of the metal gate and the single diffusion region trench, performing CMP until the interlayer dielectric layer is exposed, and forming a single diffusion region cut on the silicon substrate; the method changes the process stage of the cutting formation of the single diffusion region, and solves the problem that the performance of a device is easily poor due to the existing method for cutting the single diffusion region; the effect of improving the performance and the yield of the device is achieved.
Referring to fig. 7, a flow chart of another method for forming a single diffusion region cut according to an embodiment of the present application is shown, and as shown in fig. 7, the method may include the following steps:
in step 701, a plurality of strip fins and a virtual gate are formed on a silicon substrate, and side walls are formed on two sides of the virtual gate.
This step is explained in step 101 above and will not be described here.
At step 702, source and drain are formed on the striped fin.
This step is explained in step 102 above and will not be described here.
Optionally, the interlayer dielectric layer is made of silicon oxynitride (SiON) or silicon dioxide (SiO)2)。
And 704, removing the virtual grid electrode through photoetching and etching processes to form a groove.
And removing the polysilicon gate and the temporary gate oxide layer which form the virtual gate by photoetching and etching processes to form a groove. And reserving side walls at two sides of the virtual grid.
And depositing an interface oxide layer 26, a high-k dielectric layer 27 and a metal layer 28 in sequence to form a metal gate in the trench.
Optionally, the top of the metal gate is etched by a dry etching or wet etching process to obtain a contact window 29, as shown in fig. 3.
And 707, performing a photolithography process to expose a part of the metal gate, wherein the exposed metal gate is used for manufacturing a single diffusion region for cutting off.
As shown in fig. 4, the area of the single diffusion region cut that is not required to be made is covered with photoresist or hard mask 30 in the photolithography process, exposing the metal gate for making the single diffusion region cut.
In step 708, the exposed metal gate is etched away.
Optionally, the exposed metal gate is etched and removed by a dry etching or wet etching process.
Optionally, the side walls on the two sides of the gate are reserved.
And 709, etching the exposed silicon below the metal gate to a preset depth to form a single diffusion region groove.
The silicon under the removed metal gate is etched to a predetermined depth to form a single diffusion region trench 31, as shown in fig. 5.
Optionally, the silicon under the removed metal gate is etched by a dry etching process.
The predetermined depth is related to the depth of the single diffusion cutoff, and the predetermined depth is determined according to the depth of the single diffusion cutoff.
Alternatively, the single diffusion cutoff is 300 to 2000 angstroms deep.
At step 710, the photoresist or hard mask in the photolithography process is removed.
The photoresist or hard mask covering the surface of the silicon wafer is removed prior to depositing the fill material.
And 711, depositing a filling material and performing CMP to form a single diffusion region cut, wherein the filling material is used for filling the contact window and the single diffusion region groove.
Optionally, the filling material is silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon dioxide (SiO)2) Silicon carbonitride (SiCN), polysilicon (poly).
And after depositing the filling material, performing CMP on the filling material, and stopping CMP when the interlayer dielectric layer is exposed. As shown in fig. 6, the single diffusion region trench 31 and the contact window 29 are filled with a filler 32, and the single diffusion region cutting is completed.
In summary, the embodiment of the present application provides a method for manufacturing a single diffusion region on a silicon substrate, including forming a strip fin and a dummy gate on the silicon substrate, forming a source and a drain on the strip fin, depositing an interlayer dielectric layer and performing CMP, exposing the top of the dummy gate, replacing the dummy gate with a metal gate, etching the top of the metal gate to obtain a contact window, performing a photolithography process to expose the metal gate for manufacturing a single diffusion region cut, etching the exposed metal gate and silicon below the metal gate to form a single diffusion region trench, depositing a filling material to fill the contact window at the top of the metal gate and the single diffusion region trench, performing CMP until the interlayer dielectric layer is exposed, and forming a single diffusion region cut on the silicon substrate; the method changes the process stage of cutting off and forming the single diffusion region, avoids the situations that the source and drain epitaxial surface has a unfilled corner and the source and drain are asymmetric, does not need to increase the characteristic size of the virtual grid, does not reduce the window between the replaced metal grid and the metal layer contact hole, and solves the problem that the performance of a device is easily deteriorated by the existing method for cutting off the single diffusion region; the effect of improving the performance and the yield of the device is achieved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method of forming a single diffusion cutoff, the method comprising:
forming a plurality of strip fins and a virtual grid on a silicon substrate, wherein side walls are formed on two sides of the virtual grid;
forming a source electrode and a drain electrode on the strip-shaped fin;
depositing an interlayer dielectric layer, and carrying out Chemical Mechanical Planarization (CMP) on the interlayer dielectric layer to expose the top of the virtual grid;
replacing the dummy gate with a metal gate;
etching the top of the metal grid to obtain a contact window;
carrying out a photoetching process to expose part of the metal grid, wherein the exposed metal grid is used for manufacturing a single diffusion region for cutting off;
etching the exposed metal grid and the silicon below the exposed metal grid to form a single diffusion region groove;
and depositing a filling material and carrying out CMP to form the single diffusion region cutting, wherein the filling material is used for filling the contact window and the single diffusion region groove.
2. The method of claim 1, wherein replacing the dummy gate with a metal gate comprises:
removing the virtual grid electrode through photoetching and etching processes to form a groove;
and depositing an interface oxide layer, a high-k dielectric layer and a metal layer, and forming the metal gate in the groove.
3. The method of claim 1, wherein the etching the exposed metal gate and the silicon under the exposed metal gate to form the single diffusion region trench comprises:
etching to remove the exposed metal gate;
and etching the silicon below the exposed metal gate to the preset depth to form the single diffusion region groove.
4. The method of claim 3, wherein the etching to remove the exposed metal gate comprises:
and removing the exposed metal gate by a dry etching or wet etching process.
5. The method of any of claims 1 to 4, wherein the single diffusion cutoff is 300 to 2000 angstroms deep.
6. The method of claim 1, wherein the filling material is any one of silicon nitride, silicon oxycarbonitride, silicon dioxide, silicon carbonitride, polysilicon.
7. The method of claim 1, wherein depositing a fill material and performing CMP to form the single diffusion cutoff, the fill material filling the contact window and the single diffusion trench, comprises:
removing the photoresist or the hard mask in the photoetching process;
and depositing the filling material and performing CMP to form the single diffusion region cutting, wherein the filling material is used for filling the contact window and the single diffusion region groove.
8. The method of claim 1, wherein the interlayer dielectric layer is made of silicon oxynitride or silicon dioxide.
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| CN113078056A (en) * | 2021-03-30 | 2021-07-06 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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