CN109037214A - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN109037214A CN109037214A CN201710439763.XA CN201710439763A CN109037214A CN 109037214 A CN109037214 A CN 109037214A CN 201710439763 A CN201710439763 A CN 201710439763A CN 109037214 A CN109037214 A CN 109037214A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims description 136
- 125000006850 spacer group Chemical group 0.000 claims description 81
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 18
- 238000010438 heat treatment Methods 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 93
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
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- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof and electronic devices.The described method includes: providing semiconductor substrate；Fin is formed on the semiconductor substrate, wherein the top of top critical size of the bottom critical dimension of the fin greater than the fin, the bottom of the fin and the fin is in terraced structure.Wherein had different sizes at the top and bottom of the fin in the semiconductor devices, wherein the bottom critical dimension of the fin is greater than the critical size at the top of the fin, it can be very good solve self-heating effect in current technique (self-heating effect) by the setting, further improve the performance and yield of the semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to nanotechnology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is for 20nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
In order to improve the performance of FinFET, it is usually formed SiGe channel in FinFET, but with FinFET
Fin width is smaller and smaller in device, and self-heating effect (self-heating effect) becomes increasingly severe, especially
For the FinFET of SiGe channel.The self-heating effect (self-heating effect) not only reduces the property of device
Can, or even will affect the reliability of device.
Therefore, it in order to improve the performance and yield of semiconductor devices, needs further to change the preparation method work of device
Into to eliminate the above problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of preparation method of semiconductor devices, which comprises
Semiconductor substrate is provided；
Fin is formed on the semiconductor substrate, wherein the bottom critical dimension of the fin is greater than the top of the fin
The top of portion's critical size, the bottom of the fin and the fin is in terraced structure.
Optionally, the material of the semiconductor substrate includes the first semiconductor material, and the material of the fin includes and institute
State the second different semiconductor material of the first semiconductor material.
Optionally, the material of the fin includes SiGe.
Optionally, the method for forming the fin includes:
There is provided semiconductor substrate, be formed on the semiconductor substrate virtual fin and be located at the virtual fin it
Between spacer material layer；
Virtual fin described in etch-back, to form opening；
The bottom for the spacer material layer that the open bottom is exposed is etched, bottom critical dimension is widened to be opened to be formed
Mouthful；
The opening is filled using fin material, to form the fin that bottom critical dimension is greater than top critical size
Piece.
Optionally, the spacer material layer includes the first spacer material layer and the second spacer material layer stacked gradually, with
And the clearance wall between second spacer material layer top and the virtual fin.
Optionally, the method for the formation virtual fin includes:
Semiconductor substrate is provided, forms mask layer on the semiconductor substrate；
The mask layer and the semiconductor substrate are etched, to form the virtual fin；
The first spacer material layer is deposited, to cover the virtual fin；
First spacer material layer described in etch-back, to expose the virtual fin of object height；
Clearance wall is formed on the side wall of the virtual fin of the exposing；
First spacer material layer described in etch-back, to reduce the thickness of first spacer material layer；
Gap between the virtual fin on first spacer material layer forms the second spacer material layer.
Optionally, the step of virtual fin described in etch-back includes:
Virtual fin described in etch-back is to the clearance wall hereinafter, to form the opening and expose the clearance wall or less
Second spacer material layer.
Optionally, formed after the fin the method also includes:
Spacer material layer described in etch-back, to form the fin of object height.
Optionally, the side wall of the bottom and top of the fin is vertical.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Semiconductor substrate；
Fin is located in the semiconductor substrate, wherein the bottom critical dimension of the fin is greater than the top of the fin
The top of portion's critical size, the bottom of the fin and the fin is in terraced structure.
Optionally, the material of the semiconductor substrate includes the first semiconductor material, and the material of the fin includes and institute
State the second different semiconductor material of the first semiconductor material.
Optionally, the material of the fin includes SiGe.
Optionally, it is also formed with virtual fin on the semiconductor substrate, the fin is located at the dummy fins on piece,
The critical size of the virtual fin is less than the bottom critical dimension of the fin.
Optionally, spacer material layer is also formed in the semiconductor substrate, described in the spacer material layer at least covers
The big part of the bottom critical dimension of fin.
Optionally, the side wall of the bottom and top of the fin is vertical.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
The present invention provides a kind of semiconductor devices and preparation method thereof, wherein at the top of the fin in the semiconductor devices
It is had different sizes with bottom, wherein the bottom critical dimension of the fin is greater than the critical size at the top of the fin,
It can be very good solve self-heating effect in current technique (self-heating effect) by the setting, further
Improve the performance and yield of the semiconductor devices.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the process flow chart of the preparation method of the semiconductor devices of one embodiment of the present invention；
Fig. 2A to Fig. 2 K shows the correlation step institute of the preparation method of the semiconductor devices of one embodiment of the present invention
The diagrammatic cross-section of the device of acquisition；
Fig. 3 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiments.
Embodiment one
In order to solve aforementioned technical problem, the present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1,
It mainly comprises the steps that
Step S1: semiconductor substrate is provided；
Step S2: forming fin on the semiconductor substrate, wherein the bottom critical dimension of the fin is greater than described
The top of the top critical size of fin, the bottom of the fin and the fin is in terraced structure.
The present invention provides a kind of semiconductor devices and preparation method thereof, can make the semiconductor device by the method
It is had different sizes at the top and bottom of fin in part, wherein the bottom critical dimension of the fin is greater than the top of the fin
The critical size in portion can be very good solve self-heating effect (self-heating in current technique by the setting
Effect), the performance and yield of the semiconductor devices are further improved.
In the following, being described in detail with reference to preparation method of the Fig. 2A to Fig. 2 K to semiconductor devices of the invention, wherein Fig. 2A
The correlation step device obtained of the preparation method of the semiconductor devices of one embodiment of the present invention is shown to Fig. 2 K
Diagrammatic cross-section.
As an example, the preparation method of semiconductor devices of the invention the following steps are included:
Firstly, executing step 1, semiconductor substrate 201 is provided, is formed with virtual fin 202 on the semiconductor substrate
And part covers the first spacer material layer 204 of the virtual fin.
Specifically, as shown in Figure 2 A, semiconductor substrate 201 its can be following at least one of the material being previously mentioned:
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, further include these
The multilayered structure etc. that semiconductor is constituted, or for silicon (SSOI), insulator upper layer is laminated on silicon-on-insulator (SOI), insulator
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Illustratively, NMOS area and PMOS area be could be formed in semiconductor substrate 201.
In one example, multiple fins are formed on a semiconductor substrate, wherein the multiple fin is disposed adjacent, institute
The width for stating fin is all identical or fin is divided into multiple fins groups with different in width, and the length of fin can not also phase
Together.
Specifically, the forming method of the fin is not limited to a certain kind, and a kind of illustrative formation side is given below
Method: hard mask layer 203 is formed on a semiconductor substrate, those skilled in the art institute can be used by forming the hard mask layer 203
The various suitable techniques being familiar with, such as chemical vapor deposition process, the hard mask layer can be the oxygen being laminated from bottom to top
Compound layer and silicon nitride layer, in the present embodiment, the hard mask layer selects SiN.
Pattern the hard mask layer, formed for etching semiconductor substrate be formed on fin it is multiple each other every
From exposure mask, in one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；Etching is partly led
Body substrate is to be formed on fin.
Then, the first spacer material layer 204, first spacer material layer are formed on the surface of the semiconductor substrate
204 top surface is lower than the top surface of the virtual fin.
Specifically, form the method for first spacer material layer 204 the following steps are included:
Firstly, forming laying on the surface of the semiconductor substrate 201 and on the surface of the virtual fin.
Further, the laying also covers the hard mask layer.
The forming method of laying can be formed by the method for deposition, such as chemical vapor deposition, atomic layer deposition etc.
Method can also be formed by the surface of semiconductor substrate described in thermal oxide, and details are not described herein.
In one embodiment, pad oxide layer is formed using steam oxidation in situ (ISSG) technique.
Then, the first spacer material layer is deposited, to cover the virtual fin above-mentioned.
Specifically, as shown in Figure 2 B, deposit the first spacer material layer, to be filled up completely the gap between fin, and to every
From the flatening process that material layer carries out such as chemical mechanical grinding.In one embodiment, using the change with flowability
It learns gas-phase deposition (FCVD) and implements the deposition.Use the isolated material to deposition of FCVD technique then being also an option that property
Layer is made annealing treatment.The material of spacer material layer also can choose oxide, such as high-aspect-ratio technique (HARP) oxide,
It is specifically as follows silica.
Then, as shown in Figure 2 C, the first spacer material layer described in etch-back, until the object height of the virtual fin, with
Isolation structure is formed, the top surface of first spacer material layer is lower than the top surface of virtual fin.Specifically, first described in etch-back
Spacer material layer with virtual fin described in exposed portion, and then forms the virtual fin with certain height.
Retain the hard mask layer in this process.
Then, step 2 is executed, forms clearance wall on the side wall of the virtual fin of exposing.
Specifically, as shown in Figure 2 D, firstly, in 204 surface of the first spacer material layer and the virtual fin
Surface forms spacer material layer 205, to cover first spacer material layer 204 and the virtual fin.
Wherein, the spacer material layer 205 can be a kind of or their groups in silica, silicon nitride, silicon oxynitride
It closes and constitutes.
Then the spacer material layer is etched, the first isolated material layer surface and virtual fin are located at removal
The spacer material layer at top, and then clearance wall 2051 is formed on the side wall of the virtual fin, as shown in Figure 2 E.
Execute step 3, the first spacer material layer described in further etch-back, to reduce first spacer material layer
Thickness.
Specifically, as shown in Figure 2 F, the first spacer material layer described in further etch-back in this step is located at exposing
The virtual fin below the clearance wall.
Wherein, the etch-back method selection and the clearance wall and the virtual fin have larger etching selectivity
Method, it is not limited to it is a certain.
The thickness of first spacer material layer is only reduced in this step, but still retains part first isolated material
Layer.
As a kind of alternative embodiment, first spacer material layer can also be completely removed, is not done herein into one
The restriction of step.
Step 4 is executed, forms the second spacer material layer for covering the virtual fin on first spacer material layer
206。
Specifically, as shown in Figure 2 G, the second spacer material layer 206 is deposited, with the gap being filled up completely between virtual fin,
And the flatening process of such as chemical mechanical grinding is carried out to the second spacer material layer.In one embodiment, using have can
The chemical vapor deposition process (FCVD) of mobility implements the deposition.Using FCVD technique then being also an option that property to deposition
The second spacer material layer made annealing treatment.The material of second spacer material layer also can choose oxide, such as advanced wide
Than technique (HARP) oxide, it is specifically as follows silica.
Wherein, first spacer material layer and the second spacer material layer can select identical material, can also select
Different materials.
Step 5 is executed, virtual fin described in etch-back is to the clearance wall hereinafter, to form the opening and expose institute
State clearance wall second spacer material layer below.
Specifically, as illustrated in figure 2h, etch-back removes the part virtual fin in this step, and by the dummy fins
Piece is etched to the clearance wall hereinafter, with the second spacer material layer described in exposed portion.
The virtual fin to first spacer material layer or more is etched, in this step to avoid exposing described first
Spacer material layer.
Wherein, it if first spacer material layer and second spacer material layer select identical material, can also lose
The virtual fin is carved to first spacer material layer hereinafter, not further herein limited.
Wherein, remote plasma precursor reactant (Siconi processing procedure, Remote plasma are selected in this step
Reaction) or gas etch method (such as Certas processing procedure) etches first fin and second fin.
Wherein, the various operating methods and parameter of the Siconi processing procedure and the Certas processing procedure are referred to ability
Conventional Siconi processing procedure and the Certas processing procedure in domain, details are not described herein.
Execute step 6, second spacer material layer that etch-back is exposed, to expand the crucial ruler of the open bottom
It is very little.
Specifically, as shown in figure 2i, second spacer material layer below of clearance wall described in etch-back, to form key
The opening of dimension enlargement, in this step, the clearance wall have biggish as protective layer with second spacer material layer
Etching selectivity only expands the clearance wall bottom to protect second spacer material layer of the open top not to be etched
The opening in portion, and then form the small special opening of the big top opening of bottom opening.
Wherein, described to select wet etching to remove the second spacer material layer of part in the present invention, to form undercutting
(undercut), specifically, etching solution is dropped in the opening and is etched, selected in the wet etching hot HCl or
TMAH is etched, and specifically, when first semiconductor material layer selects Si, TMAH aqueous solution is selected to be etched, this
The heat generated when can work device after the virtual fin is formed in invention and plays conduction, and there is the device more
Good heat dissipation performance, avoids self-heating phenomenon.
Step 7 is executed, the opening is filled, to form the fin that bottom critical dimension is greater than top critical size.
Specifically, as shown in fig. 2j, epitaxial growth fin material in said opening forms bottom to fill the opening
Portion's critical size is greater than the fin 207 of top critical size.
Wherein, the fin can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, divide
One of beamlet extension.
Wherein, the fin selects sige material, and then forms the channel of SiGe, can further decrease self-heating effect
It answers.
Wherein, the side wall of the bottom and top of the fin is vertical, can further decrease self-heating effect.
Specifically, unstrpped gas is passed through when the SiGe layer described in extension, such as the gas GeH containing Ge4, and select H2As
Carrier gas, wherein reaction gas and the flow-rate ratio of carrier gas are 0.0001~0.01, select SiH2Cl2As reaction gas, H is selected2Make
For carrier gas, wherein reaction gas and the flow-rate ratio of carrier gas are 0.0001~0.01, and the temperature of deposition is 500-950 DEG C, preferably
550-750 DEG C, gas pressure 5-700Torr, preferably 5-40Torr.
Execute step 8, the second spacer material layer and the clearance wall described in etch-back, to be formed described in object height
Fin.
Specifically, as shown in figure 2k, the second spacer material layer described in further etch-back, to reduce the second isolation material
The thickness of the bed of material, while the removal part clearance wall is etched, to expose the fin of object height.
Wherein, the engraving method can select dry etching or wet etching etc. to select with the fin etch than high
Method, do not repeat further herein.
So far the introduction for completing the committed step of the preparation method to semiconductor devices of the invention, for complete device
The step of preparation of part also needs other, does not do repeat one by one herein.
In conclusion institute can be made by the method the present invention provides a kind of semiconductor devices and preparation method thereof
It states and is had different sizes at the top and bottom of the fin in semiconductor devices, wherein the bottom critical dimension of the fin is greater than institute
The critical size for stating the top of fin can be very good solve self-heating effect (self- in current technique by the setting
Heating effect), further improve the performance and yield of the semiconductor devices.
Embodiment two
This application provides a kind of semiconductor devices, and as shown in figure 2k, the semiconductor devices includes:
Semiconductor substrate 201；
Fin 207 is located in the semiconductor substrate, wherein the bottom critical dimension of the fin is greater than the fin
Top critical size.
Wherein, semiconductor substrate 201 its can be following at least one of the material being previously mentioned: Si, Ge, SiGe,
SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors further include that these semiconductors are constituted
Multilayered structure etc., or for silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S- is laminated on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Illustratively, NMOS area and PMOS area be could be formed in semiconductor substrate 201.
In one example, multiple fins are formed on a semiconductor substrate, wherein the multiple fin is disposed adjacent, institute
The width for stating fin is all identical or fin is divided into multiple fins groups with different in width, and the length of fin can not also phase
Together.
The first spacer material layer 204, first spacer material layer 204 are formed on the surface of the semiconductor substrate
Top surface be lower than the virtual fin top surface.
Using FCVD technique, then being also an option that property makes annealing treatment the first spacer material layer of deposition.Material is isolated
The material of the bed of material also can choose oxide, such as high-aspect-ratio technique (HARP) oxide, be specifically as follows silica.
Clearance wall is also formed in the bottom of the fin.
Wherein, the gap wall layer can be for a kind of in silica, silicon nitride, silicon oxynitride or they combine and constitute.
It is formed with the second spacer material layer 206 of fin described in covering part, on first spacer material layer with shape
At the fin of object height.
Wherein, first spacer material layer and the second spacer material layer can select identical material, can also select
Different materials.
Wherein, the side wall of the bottom and top of the fin is vertical, can further decrease self-heating effect.
Optionally, the material of the semiconductor substrate includes the first semiconductor material, and the material of the fin includes and institute
State the second different semiconductor material of the first semiconductor material.
Optionally, the material of the fin includes SiGe.
In conclusion the fin the present invention provides a kind of semiconductor devices and preparation method thereof, in the semiconductor devices
It is had different sizes at the top and bottom of piece, wherein the bottom critical dimension of the fin is greater than the key at the top of the fin
Size can be very good solve self-heating effect in current technique (self-heating effect) by the setting, into
One step improves the performance and yield of the semiconductor devices.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two, the semiconductor device
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, it can also be any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein the mobile phone handsets include semiconductor devices described in embodiment two, and the semiconductor devices includes:
Semiconductor substrate has been disposed adjacent the first fin and the second fin on the semiconductor substrate；
Semiconductor substrate；
Fin is located in the semiconductor substrate, wherein the bottom critical dimension of the fin is greater than the top of the fin
Portion's critical size.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of preparation method of semiconductor devices, which is characterized in that the described method includes:
Semiconductor substrate is provided；
Fin is formed on the semiconductor substrate, wherein the top that the bottom critical dimension of the fin is greater than the fin is closed
The top of key size, the bottom of the fin and the fin is in terraced structure.
2. the method according to claim 1, wherein the material of the semiconductor substrate includes the first semiconductor material
Material, the material of the fin includes second semiconductor material different from first semiconductor material.
3. the method according to claim 1, wherein the material of the fin includes SiGe.
4. the method according to claim 1, wherein the method for forming the fin includes:
Semiconductor substrate is provided, is formed with virtual fin on the semiconductor substrate and between the virtual fin
Spacer material layer；
Virtual fin described in etch-back, to form opening；
The bottom for the spacer material layer that the open bottom is exposed is etched, to form the widened opening of bottom critical dimension；
The opening is filled using fin material, to form the fin that bottom critical dimension is greater than top critical size.
5. according to the method described in claim 4, it is characterized in that, the spacer material layer includes the first isolation stacked gradually
Material layer and the second spacer material layer, and the gap between second spacer material layer top and the virtual fin
Wall.
6. according to the method described in claim 4, it is characterized in that, the method for forming the virtual fin includes:
Semiconductor substrate is provided, forms mask layer on the semiconductor substrate；
The mask layer and the semiconductor substrate are etched, to form the virtual fin；
The first spacer material layer is deposited, to cover the virtual fin；
First spacer material layer described in etch-back, to expose the virtual fin of object height；
Clearance wall is formed on the side wall of the virtual fin of the exposing；
First spacer material layer described in etch-back, to reduce the thickness of first spacer material layer；
Gap between the virtual fin on first spacer material layer forms the second spacer material layer.
7. according to the method described in claim 6, it is characterized in that, including: the step of virtual fin described in etch-back
Virtual fin described in etch-back is to the clearance wall hereinafter, to form the opening and expose clearance wall institute below
State the second spacer material layer.
8. according to the method described in claim 5, it is characterized in that, formed after the fin the method also includes:
Spacer material layer described in etch-back, to form the fin of object height.
9. the method according to claim 1, wherein the side wall of the bottom and top of the fin is vertical.
10. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Semiconductor substrate；
Fin is located in the semiconductor substrate, wherein the top that the bottom critical dimension of the fin is greater than the fin is closed
The top of key size, the bottom of the fin and the fin is in terraced structure.
11. semiconductor devices according to claim 10, which is characterized in that the material of the semiconductor substrate includes first
Semiconductor material, the material of the fin include second semiconductor material different from first semiconductor material.
12. semiconductor devices according to claim 10, which is characterized in that the material of the fin includes SiGe.
13. semiconductor devices according to claim 10, which is characterized in that be also formed with void on the semiconductor substrate
Quasi- fin, the fin are located at the dummy fins on piece, and the bottom that the critical size of the virtual fin is less than the fin is closed
Key size.
14. semiconductor devices described in 0 or 13 according to claim 1, which is characterized in that be also formed in the semiconductor substrate
Spacer material layer, the spacer material layer at least cover the big part of bottom critical dimension of the fin.
15. semiconductor devices according to claim 10, which is characterized in that the side wall of the bottom and top of the fin is
Vertical.
16. a kind of electronic device, which is characterized in that the electronic device includes semiconductor described in one of claim 10 to 15
Device.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130302975A1 (en) * | 2012-02-29 | 2013-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin Profile Structure and Method of Making Same |
| CN103996625A (en) * | 2014-06-12 | 2014-08-20 | 上海华力微电子有限公司 | Formation method of fin structure |
| US20150311342A1 (en) * | 2014-04-23 | 2015-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Finfet with esd protection |
| CN106601683A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electric device |
| CN106601687A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, the preparation method thereof and electronic device |
| CN106601675A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic device |
-
2017
- 2017-06-12 CN CN201710439763.XA patent/CN109037214B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130302975A1 (en) * | 2012-02-29 | 2013-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin Profile Structure and Method of Making Same |
| US20150311342A1 (en) * | 2014-04-23 | 2015-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Finfet with esd protection |
| CN103996625A (en) * | 2014-06-12 | 2014-08-20 | 上海华力微电子有限公司 | Formation method of fin structure |
| CN106601683A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electric device |
| CN106601687A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, the preparation method thereof and electronic device |
| CN106601675A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
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| CN109037214B (en) | 2021-02-26 |
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