CN106024713B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 230000026267 regulation of growth Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
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- 238000011065 in-situ storage Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000011574 phosphorus Substances 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
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- 239000007792 gaseous phase Substances 0.000 description 1
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- 239000013067 intermediate product Substances 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, it is formed with several fins on the semiconductor substrate, wherein, the semiconductor substrate includes NMOS area and PMOS area, it is formed with the NMOS gate around the fin in the NMOS area, the PMOS grid around the fin is formed in the PMOS area；Step S2: offset side wall is formed on the side wall of the NMOS gate and the PMOS grid；Step S3: the first semiconductor material layer of epitaxial growth on the fin of PMOS grid two sides, to form PMOS lifting source and drain；Step S4: removing the offset side wall on the NMOS gate side wall, and two semiconductor material layer of growth regulation on the fin of the NMOS gate two sides, to form NMOS lifting source and drain.The present invention drains to the offset side wall of channel by reducing from lifting source, can reduce the LDD injection damage, improve the performance of the semiconductor devices.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to nanotechnology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is for 20nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
In LDD ion implanting, the damage of the Si caused by the ion implanting on narrow fin can be caused huge
LDD resistance, this becomes the critical issue for enhancing the FinFET performance, especially for the As ion implanting in NMOS,
The ion implanting of large dosage becomes a very big hidden danger for narrow fin, being primarily due to fin can be by nothing
It is formed and is difficult crystallization due to lacking crystal seed.
The method that the method for reducing LDD resistance on narrow fin at present is mostly injected by large dosage of thermion, to control
Ion implanting damages problem, but thermion injection technology needs hard mask layer, this can further increase process challenge, simultaneously meeting
Increase process costs.
Therefore, it in order to improve the performance and yield of semiconductor devices, needs further to change the preparation method work of device
Into to eliminate the above problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, is formed with several fins on the semiconductor substrate, wherein described partly to lead
Body substrate includes NMOS area and PMOS area, and the NMOS gate around the fin is formed in the NMOS area,
The PMOS grid around the fin is formed in the PMOS area；
Step S2: offset side wall is formed on the side wall of the NMOS gate and the PMOS grid；
Step S3: the first semiconductor material layer of epitaxial growth on the fin of PMOS grid two sides, to form PMOS
It is lifted source and drain；
Step S4: the offset side wall on the NMOS gate side wall, and the institute in the NMOS gate two sides are removed
Two semiconductor material layer of growth regulation on fin is stated, to form NMOS lifting source and drain.
Optionally, in the step S3, shielding layer first is formed in the NMOS area, re-forms the PMOS lifting source
Leakage.
Optionally, first semiconductor material layer selects SiGe, and second semiconductor material layer selects SiC.
Optionally, the step S1 includes:
Step S11: semiconductor substrate is provided and executes ion implanting, to form trap；
Step S12: patterning the semiconductor substrate, to form the fin in the NMOS area and the PMOS area
Piece；
Step S13: depositing isolation material layer, to cover the fin, then spacer material layer described in etch-back, to expose
The fin is to object height.
Optionally, the step S1 may further comprise:
Step S14: channel stop injection is executed, to form channel punchthrough stop-layer；
Step S15: deposition gate oxide and gate material layers simultaneously pattern, to be respectively formed the NMOS gate and institute
State PMOS grid；
Step S16: source and drain LDD injection is executed.
Optionally, the method may further comprise:
Step S5: source and drain is lifted to the PMOS respectively and NMOS lifting source and drain executes ion implanting step；
Step S6: annealing steps are executed.
Optionally, in the step S4, after removing the offset side wall on the NMOS gate described in formation
NMOS is lifted before source and drain, and the method may further include the step of clearance wall is formed on the side wall of the NMOS gate.
Optionally, in the step S3, before forming the PMOS lifting source and drain, the method also includes described
The step of clearance wall is formed on the offset side wall of PMOS grid.
The present invention also provides a kind of semiconductor devices being prepared such as above-mentioned method.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
In the method after forming PMOS lifting source and drain, the offset side wall on the NMOS gate side wall is removed, then in extension
It grows SiC and forms NMOS lifting source and drain, can reduce the length of LDD by the method, LDD resistance can be reduced, also simultaneously
Enhancing stress of the channel from SIC can also provide more crystal seeds from channel and lifting source and drain simultaneously, be formed with improving
A possibility that crystal, drains to the offset side wall of channel by reducing from lifting source, can reduce the LDD injection damage,
Improve the performance of the semiconductor devices.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
The preparation process schematic diagram of the heretofore described semiconductor devices of Fig. 1 a-1e；
Fig. 2 is the process flow chart for preparing semiconductor devices of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
The preparation method of semiconductor devices described in the prior art includes: to provide substrate first, and the substrate includes NMOS
Region and PMOS area, are formed on the substrate hard mask layer；Then, the hard mask layer is patterned, is formed for etching substrate
To be formed on multiple exposure masks being isolated from each other of fin；Then, substrate is etched to be formed on multiple fins；Then, it sinks
Product forms the isolation structure between multiple fins；Finally, etching removes the hard mask layer.
Then channel punchthrough stop-layer ion implanting is executed, and forms grid on the fin, in the side of the grid
Clearance wall is formed on wall, the epitaxial growth SiGe on the fin of PMOS grid two sides, to form lifting source and drain, then in institute
Epitaxial growth SiC on the fin of NMOS gate two sides is stated, to form lifting source and drain, and source and drain injection is executed, anneals.
Wherein, due to the width very little of fin, when As ion implanting in NMOS, become for narrow fin
One very big hidden danger will cause very big ion implanting damage, need the ion implanting of big implantation dosage to reduce LDD electricity
Resistance, but fin can be difficult crystallization by unformed problem and due to lacking crystal seed since then.
Embodiment 1
Semiconductor devices of the present invention and preparation method are described further below with reference to Fig. 1 a-1e, Fig. 2.
Step 201 is executed, semiconductor substrate 101 is provided and executes ion implanting, to form trap.
The semiconductor substrate 101 can be following at least one of the material being previously mentioned: silicon, insulation in this step
Silicon (SOI) on body is laminated silicon (SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx is laminated on insulator on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein the semiconductor substrate includes NMOS area and PMOS area, to form NMOS device in subsequent steps
And PMOS device.
Then pad oxide skin(coating) (Pad oxide) is formed in the semiconductor substrate 101, wherein the pad oxide skin(coating)
The forming method of (Pad oxide) can be formed by the method for deposition, such as the side such as chemical vapor deposition, atomic layer deposition
Method can also be formed by the surface of semiconductor substrate described in thermal oxide, and details are not described herein.
Then step 202 is executed, forms multiple fins 102 in semiconductor substrate 101, the width of fin is all identical,
Or fin is divided into multiple fins groups with different in width.
As shown in Figure 1a, specific forming method includes: and forms hard mask layer in semiconductor substrate 201 (not show in figure
Out), the various suitable techniques that the hard mask layer can be familiar with using those skilled in the art, such as chemical gaseous phase are formed
Depositing operation, the hard mask layer can be the oxide skin(coating) and silicon nitride layer being laminated from bottom to top；Pattern the hard exposure mask
Layer forms multiple exposure masks being isolated from each other that fin is formed on for etching semiconductor substrate 101, in one embodiment
In, using patterning process described in self-aligned double patterning case (SADP) process implementing；Semiconductor substrate 101 is etched to be formed on
Fin structure.
Further, it can also further include in this step and execute channel stop injection, to form break-through stop-layer, institute
The injection ion for stating channel stop injection is carbon ion, Nitrogen ion or combination, and injection ion is relative to perpendicular to half
The incident angle in the direction of conductor substrate 101 is 10 ° -20 °.
Execute step 203, depositing isolation material layer 103, to cover the fin structure.
Specifically, as shown in Figure 1 b, depositing isolation material layer 103, to be filled up completely the gap between fin structure.One
In a embodiment, the deposition is implemented using the chemical vapor deposition process with flowability.The material of spacer material layer 103
It can choose oxide, such as HARP.
Then spacer material layer 103 described in etch-back, until the object height of the fin.
Specifically, as shown in Figure 1a, spacer material layer 103 described in etch-back with fin described in exposed portion, and then is formed
Fin with certain height.As an example, implement high annealing, so that spacer material layer 103 densifies, the high annealing
Temperature can be 700 DEG C -1000 DEG C；Chemical mechanical grinding is executed, until exposing the top of the hard mask layer；Described in removal
Silicon nitride layer in hard mask layer removes silicon nitride layer, the corruption of the wet etching using wet etching in one embodiment
Erosion liquid is diluted hydrofluoric acid；The oxide skin(coating) and part spacer material layer 103 in the hard mask layer are removed, to expose fin
The part of structure, and then form the fin structure with certain height.
Step 204 is executed, forms gate structure on the spacer material layer, the gate structure includes NMOS gate knot
Structure and PMOS gate structure, to cover the fin.
Specifically, as shown in Figure 1 b, gate structure material layer 104, the gate structure material layer are deposited in this step
Semiconductor material commonly used in the art can be selected, such as polysilicon can be selected etc., it is not limited to it is a certain, herein no longer
Enumerate,
The deposition method of the gate material layers can select the methods of chemical vapor deposition or atomic layer deposition.
Then the gate material layers are patterned, to form the gate structure around the fin.
The gate structure material layer is patterned in this step, to form surrounding gate structure, specifically, in the grid
Exposure mask layer laminate 105 is formed on the structural material of pole, wherein the mask stack includes the oxide skin(coating) being sequentially depositing, metallic hard
Mask layer (such as NiT), oxide hard-mask layer, then then exposure development is to cover with the mask stack to form opening
Film etches the gate structure material layer, to form surrounding gate structure.
Optionally, gate structure dielectric layer can also be further formed between the fin and the gate structure.
Step 205 is executed, forms offset side wall 106 on the side wall of the gate structure.
Specifically, as illustrated in figure 1 c, the deposition offset side-wall material layer in step, to cover the gate structure, and holds
Row overall etch step, to remove the offset side-wall material layer other than the gate structure sidewall, to form the offset
Side wall 106.
Wherein, the offset side wall 106 can select material commonly used in the art, in this application the offset side wall
106 select SiN.
Step 206 is executed, executes ion implanting, and form source and drain extension (SDE) in the two sides of the gate structure.
Specifically, the biggish ion implanting of dosage can be used in this step, details are not described herein.
Execute step 207, the first semiconductor material layer of epitaxial growth on the fin of PMOS grid two sides, to be formed
PMOS is lifted source and drain 108.
Specifically, as shown in Figure 1 d, shielding layer 107 is formed in the NMOS area in this step, described in masking
NMOS area, then on the fin of PMOS gate structure two sides described in selective epitaxial growth (SEG) formation
SiGe layer, specifically, select silicon-containing gas be used as unstrpped gas, select gas containing Ge conduct adulterate, under the conveying of carrier gas into
Enter reaction chamber, and then extension obtains the SiGe layer.Optionally, in situ mix can be carried out while SiGe layer described in epitaxial growth
Miscellaneous (in-situ doped).
Step 208 is executed, removes the offset side wall on the NMOS gate side wall, and in the NMOS gate two sides
The fin on two semiconductor substrate materials layer of growth regulation, with formed NMOS lifting source and drain 109.
Specifically, as shown in fig. le, the offset side wall on the NMOS gate side wall is removed, is reduced from lifting source and drain
To the offset side wall of channel, to reduce the length of LDD.
Then in the two sides epitaxial growth SiC layer of the gate structure in NMOS area, SiC source and drain is lifted to be formed
Pole.The SiC layer is formed using selective epitaxial growth (SEG) in the present invention, specifically, selects silicon-containing gas as raw material
Gas selects gas containing C as doping, reaction chamber is entered under the conveying of carrier gas, and then extension obtains the SiC layer.It is optional
Ground, SiC layer described in epitaxial growth while, can carry out doping (in-situ doped) in situ, can adulterate phosphorus or arsenic etc.,
Such as the gas containing phosphorus or arsenic is passed through while extension.
After removing the offset side wall on the NMOS gate side wall, it can be provided more from channel and lifting source and drain
More crystal seeds, by that can reduce the LDD injection damage, improves the semiconductor device to improve a possibility that forming crystal
The performance of part.
Step 209 is executed, execute ion implanting step again and carries out rapid thermal annealing.
It can inhibit the depth and horizontal proliferation of impurity in the present invention in order to demonstrate,prove activator impurity again, execute the ion note
Rapid thermal annealing is carried out after entering, optionally, the rapid thermal annealing temperature is 1000-1050 DEG C.
So far, the introduction of the preparation process of the semiconductor devices of the embodiment of the present invention is completed.After the above step, also
It may include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation method of the present embodiment is also
It can include other steps among above-mentioned each step or between different steps, these steps can pass through the prior art
In various techniques realize that details are not described herein again.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
In the method after forming PMOS lifting source and drain, the offset side wall on the NMOS gate side wall is removed, then in extension
It grows SiC and forms NMOS lifting source and drain, can reduce the length of LDD by the method, while can also be from channel and lift
It rises in source and drain and more crystal seeds is provided, to improve a possibility that forming crystal, drained to described in channel by reducing from lifting source
Side wall is deviated, the LDD injection damage can be reduced, improve the performance of the semiconductor devices.
Fig. 2 is the specifically semiconductor devices preparation flow figure described in embodiment of the present invention one, specifically includes:
Step S1: semiconductor substrate is provided, is formed with several fins on the semiconductor substrate, wherein described partly to lead
Body substrate includes NMOS area and PMOS area, and the NMOS gate around the fin is formed in the NMOS area,
The PMOS grid around the fin is formed in the PMOS area；
Step S2: offset side wall is formed on the side wall of the NMOS gate and the PMOS grid；
Step S3: the first semiconductor material layer of epitaxial growth on the fin of PMOS grid two sides, to form PMOS
It is lifted source and drain；
Step S4: the offset side wall on the NMOS gate side wall, and the institute in the NMOS gate two sides are removed
Two semiconductor material layer of growth regulation on fin is stated, to form NMOS lifting source and drain.
Embodiment 2
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects method preparation described in embodiment 1.
Reduce from lifting source without forming offset side wall on the side wall of NMOS gate in the semiconductor devices and drain to the described inclined of channel
Side wall is moved, can reduce the length of LDD, while more crystal seeds can also be provided from channel and lifting source and drain, to improve
A possibility that forming crystal, improves the performance of the semiconductor devices.
Embodiment 3
The present invention also provides a kind of electronic devices, including semiconductor devices as described in example 2.Wherein, semiconductor device
Part is semiconductor devices as described in example 2, or the semiconductor devices obtained according to preparation method described in embodiment 1.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, is formed with several fins on the semiconductor substrate, wherein the semiconductor lining
Bottom includes NMOS area and PMOS area, the NMOS gate around the fin is formed in the NMOS area, described
The PMOS grid around the fin is formed in PMOS area；
Step S2: offset side wall is formed on the side wall of the NMOS gate and on the side wall of the PMOS grid；
Step S3: the first semiconductor material layer of epitaxial growth on the fin of PMOS grid two sides, to form PMOS lifting
Source and drain；
Step S4: the offset side wall on the NMOS gate side wall, and the fin in the NMOS gate two sides are removed
Two semiconductor material layer of on piece growth regulation, to form NMOS lifting source and drain.
2. the method according to claim 1, wherein in the step S3, first being formed in the NMOS area
Shielding layer re-forms the PMOS lifting source and drain.
3. the method according to claim 1, wherein first semiconductor material layer selects SiGe, described the
Two semiconductor material layers select SiC.
4. the method according to claim 1, wherein the step S1 includes:
Step S11: semiconductor substrate is provided and executes ion implanting, to form trap；
Step S12: patterning the semiconductor substrate, to form the fin in the NMOS area and the PMOS area；
Step S13: depositing isolation material layer, to cover the fin, then spacer material layer described in etch-back, described in exposing
Fin is to object height.
5. according to the method described in claim 4, it is characterized in that, the step S1 may further comprise:
Step S14: channel stop injection is executed, to form channel punchthrough stop-layer；
Step S15: deposition gate oxide and gate material layers simultaneously pattern, to be respectively formed the NMOS gate and described
PMOS grid；
Step S16: source and drain LDD injection is executed.
6. the method according to claim 1, wherein the method may further comprise:
Step S5: source and drain is lifted to the PMOS respectively and NMOS lifting source and drain executes ion implanting step；
Step S6: annealing steps are executed.
7. the method according to claim 1, wherein in the step S4, on removing the NMOS gate
The offset side wall after formed before NMOS lifting source and drain, the method may further include the NMOS gate
Side wall on formed clearance wall the step of.
8. the method according to claim 1, wherein in the step S3, forming the PMOS lifting source
Before leakage, the method also includes forming clearance wall on the offset side wall of the PMOS grid.
9. a kind of semiconductor devices that the method as described in one of claim 1 to 8 is prepared.
10. a kind of electronic device, including semiconductor devices as claimed in claim 9.
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| CN104124174A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104241369A (en) * | 2013-06-24 | 2014-12-24 | 三星电子株式会社 | Semiconductor device and method for fabricating the same |
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| CN104124174A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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