CN106024713A - Semiconductor device, preparation method therefor, and electronic device - Google Patents
Semiconductor device, preparation method therefor, and electronic device Download PDFInfo
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- CN106024713A CN106024713A CN201510158085.0A CN201510158085A CN106024713A CN 106024713 A CN106024713 A CN 106024713A CN 201510158085 A CN201510158085 A CN 201510158085A CN 106024713 A CN106024713 A CN 106024713A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 8
- 238000009434 installation Methods 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The invention relates to a semiconductor device, a preparation method therefor, and an electronic device The method comprises the steps: S1, providing a semiconductor substrate, and forming a plurality of fins on the semiconductor substrate, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, the NMOS region is provided with an NMOS grid surrounding the fins, and the PMOS region is provided with a PMOS grid surrounding the fins; S2, forming offset side walls on side walls of the NMOS grid and the PMOS grid; S3, carrying out the epitaxial growth of a first semiconductor material layer on the fins at two sides of the PMOS grid, so as to form a PMOS lifting source-drain part; S4, removing the offset side wall on the side wall of the NMOS grid, and growing second semiconductor material layers on the fins at two sides of the NMOS grid, so as to form an NMOS lifting source-drain part. The method can reduce the LDD injection damage through reducing the offset side wall from the lifting source-drain part to a trench, and improves the performance of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor device and preparation thereof
Method, electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing
The size of IC-components realizes with the speed improving it.At present, due to close at the high device of pursuit
In degree, high-performance and low cost, semi-conductor industry has advanced to nanotechnology process node, semiconductor device
The preparation of part is limited by various physics limits.
Along with constantly reducing of cmos device size, promote three from the challenge manufactured with design aspect
Dimension design is such as the development of FinFET (FinFET).Relative to existing planar transistor,
FinFET is for 20nm and the advanced semiconductor device of following process node, and it can effective controller
Scaled the caused short-channel effect being difficult to overcome of part, it is also possible to be effectively improved shape on substrate
The density of the transistor array become, meanwhile, the grid in FinFET is arranged around fin (fin-shaped channel),
Therefore can control electrostatic from three faces, the performance in terms of Electrostatic Control is the most prominent.
In LDD ion implanting, the Si that the ion implanting on narrow fin causes damages, and can draw
The huge LDD resistance risen, this becomes the key issue strengthening described FinFET performance, especially
Being for the As ion implanting in NMOS, heavy dose of ion implanting becomes for narrow fin
It is a hidden danger the biggest, it is primarily due to fin and can suffer unformed and be difficult to crystalline substance owing to lacking crystal seed
Body.
Reduce the side that on narrow fin, the method for LDD resistance is mostly injected by heavy dose of thermion at present
Method, controls ion implanting and damages problem, but thermion injection technology needs hard mask layer, and this can enter
One step increases process challenge, can increase process costs simultaneously.
Therefore, in order to improve performance and the yield of semiconductor device, need the preparation method of device is made into
The improvement of one step, in order to eliminate the problems referred to above.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in detailed description of the invention
Part further describes.The Summary of the present invention is not meant to attempt to limit institute
The key feature of claimed technical scheme and essential features, more do not mean that and attempt to determine and wanted
Seek the protection domain of the technical scheme of protection.
The present invention is in order to overcome the problem of presently, there are, it is provided that the preparation method of a kind of semiconductor device, bag
Include:
Step S1: Semiconductor substrate is provided, is formed with some fins on the semiconductor substrate, wherein,
Described Semiconductor substrate includes NMOS area and PMOS area, is formed in described NMOS area
There is the NMOS gate around described fin, described PMOS area is formed around described fin
PMOS grid；
Step S2: form skew sidewall on the sidewall of described NMOS gate and described PMOS grid；
Step S3: at fin Epitaxial growth first semiconductor material layer of described PMOS grid both sides,
To form PMOS lifting source and drain；
Step S4: remove the described skew sidewall on described NMOS gate sidewall, and at described NMOS
The second semiconductor material layer is grown, to form NMOS lifting source and drain on the described fin of grid both sides.
Alternatively, in described step S3, first form shielding layer in described NMOS area, then formed
Described PMOS lifting source and drain.
Alternatively, described first semiconductor material layer selects SiGe, described second semiconductor material layer to select
SiC。
Alternatively, described step S1 includes:
Step S11: Semiconductor substrate is provided and performs ion implanting, to form trap；
Step S12: pattern described Semiconductor substrate, with at described NMOS area and described PMOS
Region forms described fin；
Step S13: depositing isolation material layer, to cover described fin, then isolates material described in etch-back
The bed of material, to expose described fin to object height.
Alternatively, described step S1 may further comprise:
Step S14: perform channel stop and inject, to form channel punchthrough stop-layer；
Step S15: deposition gate oxide and gate material layers also pattern, described to be formed respectively
NMOS gate and described PMOS grid；
Step S16: perform source and drain LDD and inject.
Alternatively, described method may further comprise:
Step S5: respectively described PMOS lifting source and drain and described NMOS lifting source and drain are performed ion
Implantation step；
Step S6: perform annealing steps.
Alternatively, in described step S4, at the described skew sidewall removed on described NMOS gate
Before forming described NMOS lifting source and drain afterwards, described method may further include described NMOS
The step of clearance wall is formed on the sidewall of grid.
Alternatively, in described step S3, before forming described PMOS lifting source and drain, described side
Method is additionally included in the step forming clearance wall on the skew sidewall of described PMOS grid.
Present invention also offers the semiconductor device that a kind of method described above prepares.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor device.
The present invention is to solve problems of the prior art, it is provided that the preparation of a kind of semiconductor device
Method, in the process after forming PMOS lifting source and drain, removes described NMOS gate sidewall
On skew sidewall, then epitaxial growth SiC formed NMOS lifting source and drain, can by described method
To reduce the length of LDD, LDD resistance can be reduced, strengthen the raceway groove stress from SIC the most simultaneously
More crystal seed can also be provided from raceway groove and lifting source and drain, to improve the possibility forming crystal simultaneously
Property, by reducing the described skew sidewall draining to raceway groove from lifting source, described LDD can be reduced and inject damage
Bad, improve the performance of described semiconductor device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Accompanying drawing shows
Go out embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,
The preparation process schematic diagram of the heretofore described semiconductor device of Fig. 1 a-1e；
Fig. 2 is the process chart preparing semiconductor device of the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention the most thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention,
Technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district
Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling
Conjunction is arrived " other element or during layer, its can directly on other element or layer, adjacent thereto, connect
Or be coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, claimed when element
For " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan
When part or layer, the most there is not element between two parties or layer.Although it should be understood that can use term first,
Two, the various element of third description, parts, district, floor and/or part, these elements, parts, district,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, parts,
District, floor or part and another element, parts, district, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ",
" ... on ", " above " etc., here can describe for convenience and be used thus in description figure
A shown element or feature and other element or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term is intended to also include the different orientation of device in using and operating.Example
As, if the device upset in accompanying drawing, then, it is described as " below other element " or " its it
Under " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, example
Property term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally take
Correspondingly explained to (90-degree rotation or other orientation) and spatial description language as used herein.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ",
When using in this specification, determine described feature, integer, step, operation, element and/or parts
Existence, but be not excluded for one or more other feature, integer, step, operation, element, parts
And/or group existence or interpolation.When using at this, term "and/or" includes any of relevant Listed Items
And all combinations.
The preparation method of semiconductor device described in prior art includes: first provide substrate, described substrate
Including NMOS area and PMOS area, substrate forms hard mask layer；Then, patterning is described
Hard mask layer, is formed for etching substrate to be formed on multiple masks being isolated from each other of fin；Connect
, etching substrate is to be formed on multiple fin；Then, the isolation junction between the multiple fin of formation of deposits
Structure；Finally, described hard mask layer is removed in etching.
Then perform channel punchthrough stop-layer ion implanting, and on described fin, form grid, described
Clearance wall is formed on the sidewall of grid, at the described fin Epitaxial growth SiGe of PMOS grid both sides,
To form lifting source and drain, then at the described fin Epitaxial growth SiC of described NMOS gate both sides,
To form lifting source and drain, and perform source and drain injection, anneal.
Wherein, owing to the width of fin is the least, during As ion implanting in NMOS, for narrow
Fin for become a hidden danger the biggest, the biggest ion implanting can be caused to damage, need big injection
The ion implanting of dosage reduces LDD resistance, but so since fin can suffer unformed problem and
It is difficult to crystallization owing to lacking crystal seed.
Embodiment 1
Below in conjunction with Fig. 1 a-1e, Fig. 2, semiconductor device of the present invention and preparation method are done further
Explanation.
Perform step 201, it is provided that Semiconductor substrate 101 also performs ion implanting, to form trap.
The most described Semiconductor substrate 101 can be at least in the following material being previously mentioned
Kind: stacking germanium on stacking silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator
SiClx (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.
Wherein said Semiconductor substrate includes NMOS area and PMOS area, with in follow-up step
Nmos device and PMOS device is formed in rapid.
Then in described Semiconductor substrate 101, form pad oxide skin(coating) (Pad oxide), wherein said pad
The forming method of oxide skin(coating) (Pad oxide) can be formed by the method for deposition, such as chemical gaseous phase
The methods such as deposition, ald, it is also possible to formed by the surface of Semiconductor substrate described in thermal oxide,
Do not repeat them here.
Then perform step 202, Semiconductor substrate 101 is formed multiple fin 102, the width of fin
The most identical, or fin is divided into multiple fins group with different in width.
As shown in Figure 1a, concrete forming method includes: form hard mask layer in Semiconductor substrate 201
(not shown), form that described hard mask layer can use that those skilled in the art are familiar with is various suitable
Suitable technique, such as chemical vapor deposition method, described hard mask layer can be the oxygen of stacking from bottom to top
Compound layer and silicon nitride layer；Pattern described hard mask layer, formed be used for etching Semiconductor substrate 101 with
It is formed on multiple masks being isolated from each other of fin, in one embodiment, uses self-aligned double patterning
Patterning process described in case (SADP) process implementing；Etching Semiconductor substrate 101 is to be formed on fin
Chip architecture.
Further, execution channel stop can also be comprised in this step further inject, to form break-through
Stop-layer, the injection ion that described channel stop injects is carbon ion, Nitrogen ion or combination,
Injecting ion is 10 °-20 ° relative to the incident angle in the direction being perpendicular to Semiconductor substrate 101.
Performing step 203, depositing isolation material layer 103, to cover described fin structure.
Specifically, as shown in Figure 1 b, depositing isolation material layer 103, to be filled up completely with between fin structure
Gap.In one embodiment, the chemical vapor deposition method with flowable is used to implement described
Deposition.The material of spacer material layer 103 can be with selective oxidation thing, such as HARP.
Then spacer material layer 103 described in etch-back, to the object height of described fin.
Specifically, as shown in Figure 1a, spacer material layer 103 described in etch-back, with fin described in exposed portion
Sheet, and then form the fin with certain height.As example, implement high annealing, so that isolation material
The bed of material 103 densification, the temperature of described high annealing can be 700 DEG C-1000 DEG C；Perform chemical machinery
Grind, until exposing the top of described hard mask layer；Remove the silicon nitride layer in described hard mask layer,
In one embodiment, using wet etching to remove silicon nitride layer, the corrosive liquid of described wet etching is dilution
Fluohydric acid.；Remove the oxide skin(coating) in described hard mask layer and part spacer material layer 103, to expose
The part of fin structure, and then form the fin structure with certain height.
Performing step 204, form grid structure on described spacer material layer, described grid structure includes
NMOS gate structure and PMOS grid structure, to cover described fin.
Specifically, as shown in Figure 1 b, gate structure material layer 104, described grid are deposited in this step
Structural material can select semi-conducting material commonly used in the art, such as, can select polysilicon etc., and
It is not limited to a certain kind, will not enumerate at this,
The deposition process of described gate material layers can select the sides such as chemical gaseous phase deposition or ald
Method.
Then described gate material layers is patterned, to form the grid structure around described fin.
Pattern described gate structure material layer in this step, to form all around gate structure, specifically,
Forming mask layer lamination 105 in described gate structure material layer, wherein said mask stack includes successively
The oxide skin(coating) of deposition, metal hard mask layer (such as NiT), oxide hard-mask layer, then exposure is aobvious
Shadow, to form opening, gate structure material layer described in then with described mask stack as mask etch, with
Form all around gate structure.
Alternatively, grid structure can also be formed between described fin and described grid structure further be situated between
Electric layer.
Perform step 205, the sidewall of described grid structure is formed skew sidewall 106.
Specifically, as illustrated in figure 1 c, deposition skew side-wall material layer in step, to cover described grid
Structure, and perform overall etch step, to remove the described skew sidewall beyond described gate structure sidewall
Material layer, to form described skew sidewall 106.
Wherein, described skew sidewall 106 can select material commonly used in the art, described in this application
Skew sidewall 106 selects SiN.
Perform step 206, perform ion implanting, and form source and drain extension in the both sides of described grid structure
District (SDE).
Specifically, can not repeat them here with the bigger ion implanting of using dosage in this step.
Perform step 207, at fin Epitaxial growth the first quasiconductor material of described PMOS grid both sides
The bed of material, to form PMOS lifting source and drain 108.
Specifically, as shown in Figure 1 d, shielding layer 107 is formed in described NMOS area in this step,
To cover described NMOS area, then select on the described fin of described PMOS grid structure both sides
Property epitaxial growth (SEG) form described SiGe layer, specifically, select silicon-containing gas as unstrpped gas,
Select containing Ge gas as doping, under the conveying of carrier gas, enter reative cell, and then extension obtains described
SiGe layer.Alternatively, (the in-situ that adulterates in situ can be carried out while SiGe layer described in epitaxial growth
doped)。
Perform step 208, remove the described skew sidewall on described NMOS gate sidewall, and described
Grow the second semiconductor substrate materials layer on the described fin of NMOS gate both sides, lift forming NMOS
Rise source and drain 109.
Specifically, as shown in fig. le, the described skew sidewall on described NMOS gate sidewall is removed,
Reduce the described skew sidewall draining to raceway groove from lifting source, to reduce the length of LDD.
Then in the both sides epitaxial growth SiC layer of described grid structure in NMOS area, lift to be formed
Rise SiC source-drain electrode.Selective epitaxial growth (SEG) is used to form described SiC layer, specifically in the present invention
Ground, selects silicon-containing gas as unstrpped gas, selects containing C gas as doping, under the conveying of carrier gas
Enter reative cell, and then extension obtains described SiC layer.Alternatively, SiC layer described in epitaxial growth is same
Time can carry out adulterating (in-situ doped) in situ, can be with Doping Phosphorus or arsenic etc., such as extension same
Time be passed through the phosphorous or gas of arsenic.
After the skew sidewall removed on described NMOS gate sidewall, can be from raceway groove and lifting source
Leakage provides more crystal seed, to improve the probability forming crystal, notes by described LDD can be reduced
Enter to damage, improve the performance of described semiconductor device.
Perform step 209, again perform ion implanting step and carry out rapid thermal annealing.
The degree of depth and the horizontal proliferation of impurity can be suppressed again in the present invention in order to demonstrate,prove activator impurity, performed institute
Carrying out rapid thermal annealing after stating ion implanting, alternatively, described rapid thermal annealing temperature is 1000-1050
℃。
So far, the introduction of the preparation process of the semiconductor device of the embodiment of the present invention is completed.In above-mentioned step
After Zhou, it is also possible to including other correlation step, here is omitted.Further, except above-mentioned steps it
Outward, the preparation method of the present embodiment can also include among each step above-mentioned or between different step
Other steps, these steps all can be realized by various techniques of the prior art, the most superfluous
State.
The present invention is to solve problems of the prior art, it is provided that the preparation of a kind of semiconductor device
Method, in the process after forming PMOS lifting source and drain, removes described NMOS gate sidewall
On skew sidewall, then epitaxial growth SiC formed NMOS lifting source and drain, can by described method
To reduce the length of LDD, more crystal seed can also be provided from raceway groove and lifting source and drain simultaneously, with
Improve the probability forming crystal, by reducing the described skew sidewall draining to raceway groove from lifting source, permissible
Reduce described LDD and inject damage, improve the performance of described semiconductor device.
Fig. 2 is the present invention one specifically figure of semiconductor device preparation flow described in embodiment, specifically
Including:
Step S1: Semiconductor substrate is provided, is formed with some fins on the semiconductor substrate, wherein,
Described Semiconductor substrate includes NMOS area and PMOS area, is formed in described NMOS area
There is the NMOS gate around described fin, described PMOS area is formed around described fin
PMOS grid；
Step S2: form skew sidewall on the sidewall of described NMOS gate and described PMOS grid；
Step S3: at fin Epitaxial growth first semiconductor material layer of described PMOS grid both sides,
To form PMOS lifting source and drain；
Step S4: remove the described skew sidewall on described NMOS gate sidewall, and at described NMOS
The second semiconductor material layer is grown, to form NMOS lifting source and drain on the described fin of grid both sides.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device is selected described in embodiment 1
Prepared by method.Described semiconductor device is formed without on the sidewall of NMOS gate offset sidewall, reduces
Drain to the described skew sidewall of raceway groove from lifting source, the length of LDD can be reduced, simultaneously can also be from ditch
Road and lifting source and drain provide more crystal seed, to improve the probability forming crystal, improves described half
The performance of conductor device.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment 2.Wherein,
Semiconductor device is the semiconductor device described in embodiment 2, or according to the preparation method described in embodiment 1
The semiconductor device obtained.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, it is possible to for any centre including described semiconductor device
Product.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and is not intended to limit the invention to described scope of embodiments
In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root
Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc.
Effect scope is defined.
Claims (10)
1. a preparation method for semiconductor device, including:
Step S1: Semiconductor substrate is provided, is formed with some fins on the semiconductor substrate, wherein,
Described Semiconductor substrate includes NMOS area and PMOS area, is formed in described NMOS area
There is the NMOS gate around described fin, described PMOS area is formed around described fin
PMOS grid；
Step S2: form skew sidewall on the sidewall of described NMOS gate and described PMOS grid；
Step S3: at fin Epitaxial growth first semiconductor material layer of described PMOS grid both sides,
To form PMOS lifting source and drain；
Step S4: remove the described skew sidewall on described NMOS gate sidewall, and at described NMOS
The second semiconductor material layer is grown, to form NMOS lifting source and drain on the described fin of grid both sides.
Method the most according to claim 1, it is characterised in that in described step S3, first exists
Described NMOS area forms shielding layer, then forms described PMOS lifting source and drain.
Method the most according to claim 1, it is characterised in that described first semiconductor material layer choosing
With SiGe, described second semiconductor material layer selects SiC.
Method the most according to claim 1, it is characterised in that described step S1 includes:
Step S11: Semiconductor substrate is provided and performs ion implanting, to form trap；
Step S12: pattern described Semiconductor substrate, with at described NMOS area and described PMOS
Region forms described fin；
Step S13: depositing isolation material layer, to cover described fin, then isolates material described in etch-back
The bed of material, to expose described fin to object height.
Method the most according to claim 4, it is characterised in that described step S1 is wrapped the most further
Include:
Step S14: perform channel stop and inject, to form channel punchthrough stop-layer；
Step S15: deposition gate oxide and gate material layers also pattern, described to be formed respectively
NMOS gate and described PMOS grid；
Step S16: perform source and drain LDD and inject.
Method the most according to claim 1, it is characterised in that described method may further comprise:
Step S5: respectively described PMOS lifting source and drain and described NMOS lifting source and drain are performed ion
Implantation step；
Step S6: perform annealing steps.
Method the most according to claim 1, it is characterised in that in described step S4, is going
Before forming described NMOS lifting source and drain after the described skew sidewall on described NMOS gate,
Described method may further include the step forming clearance wall on the sidewall of described NMOS gate.
Method the most according to claim 1, it is characterised in that in described step S3, in shape
Before becoming described PMOS lifting source and drain, described method is additionally included in the skew sidewall of described PMOS grid
The step of upper formation clearance wall.
9. the semiconductor device that the method as described in one of claim 1 to 8 prepares.
10. an electronic installation, including the semiconductor device described in claim 9.
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