CN106601680B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents

A kind of semiconductor devices and preparation method thereof, electronic device Download PDF

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Publication number
CN106601680B
CN106601680B CN201510675632.2A CN201510675632A CN106601680B CN 106601680 B CN106601680 B CN 106601680B CN 201510675632 A CN201510675632 A CN 201510675632A CN 106601680 B CN106601680 B CN 106601680B
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etching stopping
layer
stopping layer
laying
fin
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CN106601680A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, forms the spacer material layer of several fins being spaced apart from each other and the covering fin bottom on the semiconductor substrate, wherein the surface of the fin is formed with laying；Step S2: the first etching stopping layer and the second etching stopping layer are sequentially formed on the spacer material layer and the laying of exposing；Step S3: to second etching stopping layer and first etching stopping layer progress ion implanting in the horizontal direction on the spacer material layer, to change the etch-rate of first etching stopping layer and second etching stopping layer on the spacer material layer；Step S4: second etching stopping layer on the laying is removed；Step S5: first etching stopping layer and the laying of exposing are removed, while removing remaining second etching stopping layer.

Description

A kind of semiconductor devices and preparation method thereof, electronic device
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of semiconductor devices and preparation method thereof, electronics Device.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit The size of device is realized with improving its speed.Currently, due to the demand of high device density, high-performance and low cost, half Conductor industry has advanced to nanotechnology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, short-channel effect becomes a key factor for influencing device performance, Relative to existing planar transistor, FinFET is the advanced semiconductor device for 20nm and following process node, can be with The short-channel effect for being difficult to overcome caused by effective control device is scaled, can also effectively improve and be formed on the substrate Transistor array density, meanwhile, grid in FinFET is arranged around fin (fin-shaped channel), therefore can come from three faces Electrostatic is controlled, the performance in terms of Electrostatic Control is also more prominent.
Usually first etching forms fin and is formed on fin (usually up-narrow and down-wide) in FinFET preparation process Dummy gate dielectric layer, then simultaneously etch-back was prepared with forming the fin of object height subsequent depositing isolation material layer By the way that the removal part spacer material layer can be etched during removing dummy gate dielectric layer in journey, to make the fin Piece bottom scale reduces, so that channel stop ion implanting be made more to diffuse in channel, reduces the performance of device.
In addition, the short-channel effect of the bigger device of the width of fin bottom is more in the FinFET preparation process Small, fin bottom scale reduces, and short-channel effect is more serious, therefore how to prevent isolated material in device fabrication process The loss of layer plays an important role the yield and performance that enhance FinFET.
Therefore the method needs to improve the method there are above-mentioned many drawbacks at present, described to eliminate Problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, several fins being spaced apart from each other is formed on the semiconductor substrate and covers Cover the spacer material layer of the fin bottom, wherein the surface of the fin is formed with laying；
Step S2: sequentially formed on the spacer material layer and the laying of exposing the first etching stopping layer and Second etching stopping layer, to cover the spacer material layer and the laying；
Step S3: second etching stopping layer and described first in the horizontal direction on the spacer material layer is lost It carves stop-layer and carries out ion implanting, so that first etching stopping layer and second etching on the spacer material layer stop The only etching speed of the etch-rate of layer and first etching stopping layer and second etching stopping layer on the laying Rate is different；
Step S4: removing second etching stopping layer on the laying, to expose first etching stopping layer；
Step S5: first etching stopping layer and the laying for removing exposing are gone simultaneously with exposing the fin Except remaining second etching stopping layer, to expose first etching stopping layer on the spacer material layer.
Optionally, in the step S3, silicon is carried out to second etching stopping layer and first etching stopping layer Ion implanting, to change the etch-rate of first etching stopping layer and second etching stopping layer in horizontal direction.
Optionally, ion note is carried out to second etching stopping layer and first etching stopping layer with vertical direction Enter, the tilt angle in the ion implanting direction is 0.
Optionally, first etching stopping layer selects nitride.
Optionally, second etching stopping layer selects oxide.
Optionally, the step S1 includes:
Step S11: providing the semiconductor substrate, forms pad oxide skin(coating) on the semiconductor substrate, wherein described Semiconductor substrate includes NMOS area and PMOS area；
Step S12: first kind ion implanting is executed in the NMOS area, to form p-well, in the PMOS area Middle execution Second Type ion implanting, to form N trap；
Step S13: patterned mask layer is formed on the semiconductor substrate and using the mask layer as mask etch The semiconductor substrate, to form the fin in the NMOS area and the PMOS area respectively.
Optionally, the step S1 further include:
Step S14: the laying is formed on the surface of the fin, to cover the fin；
Step S15: depositing isolation material layer, to cover the laying；
Step S16: spacer material layer described in etch-back, with the laying in fin sidewall described in exposed portion.
Optionally, the step S1 further include:
Step S17: channel stop ion implanting is carried out to the fin of spacer material layer covering；
Step S18: it removes the mask layer on the fin and anneals.
The present invention also provides a kind of semiconductor devices being prepared such as above-mentioned method.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices, In the method after etching the spacer material layer and forming the fin of object height, in the fin and the isolation material Form the first etching stopping layer and the second etching stopping layer on the bed of material, and to the first etching stopping layer and the second etching stopping layer into The vertical ion implanting of row, to change the etching speed of first etching stopping layer and the second etching stopping layer in horizontal direction Rate keeps it different from the etch-rate of first etching stopping layer and the second etching stopping layer on vertical direction, finally goes Except first etching stopping layer and the second etching stopping layer in fin sidewall described on vertical direction, on retention level direction First etching stopping layer and the second etching stopping layer finally removed on the fin with protecting the spacer material layer The laying or dummy gate dielectric layer, the first etching stopping layer and the second etching stopping layer protect institute in this process It is not damaged to state spacer material layer.
The present invention avoids the etching removal part spacer material layer during the preparation process by the method, to make Fin bottom scale reduces, the problem of reducing the performance of device, further improves the performance of semiconductor devices and good Rate.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1l is the preparation process schematic diagram of heretofore described semiconductor devices；
Fig. 2 is the process flow chart for preparing semiconductor devices of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation, The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute There is combination.
Embodiment one
Semiconductor devices of the present invention and preparation method are described further with reference to the accompanying drawing, wherein figure 1a-1l is the preparation process schematic diagram of heretofore described semiconductor devices；Fig. 2 is to prepare semiconductor devices of the present invention Process flow chart.
Semiconductor substrate 101 is provided and executes ion implanting, to form trap.
The semiconductor substrate 101 can be following at least one of the material being previously mentioned: silicon, insulation in this step Silicon (SOI) on body is laminated silicon (SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx is laminated on insulator on insulator (SiGeOI) and germanium on insulator (GeOI) etc..
As shown in Figure 1a, wherein the semiconductor substrate 101 includes NMOS area and PMOS area, in subsequent step Middle formation NMOS device and PMOS device.
Optionally, the method can also include that pad oxide skin(coating) (Pad is formed in the semiconductor substrate 101 Oxide), wherein the forming method of pad oxide skin(coating) (Pad oxide) can be formed by the method for deposition, such as chemistry The methods of vapor deposition, atomic layer deposition, can also be formed by the surface of semiconductor substrate described in thermal oxide, no longer superfluous herein It states.
Further, the step of executing ion implanting can also be further included, in this step to serve as a contrast in the semiconductor Trap is formed in bottom, optionally, first kind ion implanting, such as B is executed in NMOS area, to form p-well, in PMOS area Middle execution Second Type ion implanting, such as P, to form N trap.
The ionic species and method for implanting wherein injected can be method commonly used in the art, not go to live in the household of one's in-laws on getting married one by one herein It states.
Then, hard mask layer 103 is formed in semiconductor substrate 101, the semiconductor substrate is then patterned, in institute State the fin that NMOS and PMOS is formed in semiconductor substrate.
Specifically, as shown in Figure 1 b, wherein optionally, may be used also between the semiconductor substrate and the hard mask layer To form amorphous silicon, buffer layer of the amorphous silicon as the hard mask layer, the amorphous silicon can solve every The problem of falling off from hard mask layer SiN in material layer etch-back process.
In addition, unformed silicon can be used as the buffer layer of the hard mask layer, the substrate Si lattice and SiN can solve Mismatch and missing problem；The amorphous silicon buffer layer exists in subsequent steps and subsequent technique is compatible.
Wherein, the hard mask layer selects SiN.
Then, the amorphous si-layer, hard mask layer and the semiconductor substrate 101 are etched, to form multiple fins 102, the semiconductor substrate is partially etched in this step.
Specifically, as shown in Figure 1 b, wherein the width of the fin is all identical or fin is divided into different in width Multiple fins groups.
Specific forming method includes: to form photoresist layer (not shown) on a semiconductor substrate, forms the light The various suitable techniques that photoresist layer can be familiar with using those skilled in the art, pattern the photoresist layer, are formed and are used Multiple exposure masks being isolated from each other of fin are formed in etching semiconductor substrate, then using the photoresist layer as exposure mask The amorphous si-layer, hard mask layer and the semiconductor substrate 101 are etched, it is multiple with fin 102 to be formed.
Optionally, pad oxide layer can also be formed on the fin, to cover surface, the fin of semiconductor substrate The side wall and top of the side wall of structure and the hard mask layer.
Specifically, in one embodiment, technique (ISSG) is generated using on-site steam and forms pad oxide layer.
Then, depositing isolation material layer 104, to cover the fin.
Specifically, as illustrated in figure 1 c, depositing isolation material layer, to be filled up completely the gap between fin structure.At one In embodiment, the material of spacer material layer can choose oxide, such as HARP.
In one embodiment, spacer material layer is formed using the chemical vapor deposition process (FCVD) with flowability 104。
Wherein the chemical vapor deposition process with flowability selects higher temperature, same during deposition When complete annealing steps, wherein the annealing temperature be 1000-1050 DEG C, annealing time 10-20s so that the phosphate material Phosphorus in layer is adequately spread, and to realize the purpose of threshold voltage ion implanting, and then adjusts the threshold voltage of fin.
Planarisation step is still further comprised after depositing the spacer material layer 104, planarizes the isolated material Layer 104 is to the top of the fin, as shown in Figure 1 d.
Then, spacer material layer described in etch-back, until the object height of the fin, as shown in fig. le.
Specifically, spacer material layer described in etch-back with fin described in exposed portion, and then is formed with certain height Fin.
Optionally, such as in this step spacer material layer described in SiCoNi processing procedure etch-back is selected, wherein described The various parameters of SiCoNi processing procedure can select conventional parameter.
Then, channel stop ion implanting is carried out to the spacer material layer.
Specifically, as shown in fig. le, implement channel stop injection in this step, to form the break-through stop-layer, control System is located at the source/drain break-through of fin structure bottom.
The injection ion of the channel stop injection can select ion commonly used in the art, it is not limited to a certain Kind.
Optionally, after executing the channel stop ion implanting, the step of execution is annealed is still further comprised.
Optionally, after executing the channel stop ion implanting, the institute removed on the fin is still further comprised Hard mask layer is stated, as shown in Figure 1 f.
Then, the first etching stopping layer 105 is sequentially formed on the spacer material layer and the laying of exposing The laying of the spacer material layer and exposing is covered with the second etching stopping layer 106.
Specifically, as shown in Figure 1 g, first is formed on the spacer material layer and the laying of exposing first Etching stopping layer 105, wherein first etching stopping layer selects nitride, such as can select SiN.
Then, the second etching stopping layer 106 is formed on first etching stopping layer, it is as shown in figure 1h wherein, described Second etching stopping layer 106 selects oxide, such as can select SiO2, but it is not limited to the material, as shown in figure 1h.
Then, to first etching stopping layer 105 and described second on the spacer material layer in horizontal direction Etching stopping layer 106 carries out ion implanting, so that first etching stopping layer 105 on the spacer material layer and described the The etch-rate of two etching stopping layers 106 and first etching stopping layer 105 on the laying and second etching The etch-rate of stop-layer 106 is different.
Specifically, as shown in figure 1i, in this step with vertical direction to the spacer material layer in horizontal direction On first etching stopping layer 105 and second etching stopping layer 106 carry out ion implanting so that the isolated material On the etch-rate and the laying of first etching stopping layer 105 and second etching stopping layer 106 on layer First etching stopping layer 105 is different with the etch-rate of second etching stopping layer 106.
Optionally, the tilt angle of the ion implanting is 0.
Optionally, Si ion implantation is carried out to first etching stopping layer 105 and second etching stopping layer 106, To change the etch-rate of first etching stopping layer 105 and second etching stopping layer 106 in horizontal direction, losing When carving first etching stopping layer 105 and the second etching stopping layer 106 removed in the fin sidewall, retain First etching stopping layer 105 and second etching stopping layer 106 in horizontal direction on the spacer material layer.
Then, second etching stopping layer on the laying is removed, to expose first etching stopping layer.
Specifically, as shown in fig. ij, second etching stopping layer on the laying is removed in this step, is retained Second etching stopping layer on the spacer material layer in the horizontal direction, to expose described in fin sidewall One etching stopping layer.
In this step due to being infused in second etching stopping layer on the spacer material layer in the horizontal direction Silicon is entered, etch-rate is different from the etch-rate of second etching stopping layer in the fin sidewall, therefore can be with Selectively remove second etching stopping layer in the fin sidewall.
Then, first etching stopping layer and the laying for removing exposing are removed simultaneously with exposing the fin Remaining second etching stopping layer, to expose first etching stopping layer 105 on the spacer material layer.
Specifically, as shown in Fig. 1 k-1l, first etching stopping layer on the laying is removed in this step, Retain first etching stopping layer on the spacer material layer in the horizontal direction, to expose the laying.
In this step due to being infused in first etching stopping layer on the spacer material layer in the horizontal direction Silicon is entered, etch-rate is different from the etch-rate of first etching stopping layer in the fin sidewall, therefore can be with Selectively remove first etching stopping layer on described side wall.
When removing the laying exposing fin in this step, due to being formed with the first etching on spacer material layer Stop-layer is protected to being formed on the spacer material layer, using first etching stopping layer as stop-layer, is prevented to isolated material Layer damages, therefore avoids the etching removal part spacer material layer during the preparation process, to make the fin bottom The problem of portion's scale reduces, and reduces the performance of device, further improves the performance and yield of semiconductor devices.
So far, the introduction of the preparation process of the semiconductor devices of the embodiment of the present invention is completed.After the above step, also It may include other correlation steps, such as form gate structure on the fin structure, details are not described herein again.Also, in addition to Except above-mentioned steps, the preparation method of the present embodiment can also include it among above-mentioned each step or between different steps His step, these steps can realize that details are not described herein again by various techniques in the prior art.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices, In the method after etching the spacer material layer and forming the fin of object height, in the fin and the isolation material Form the first etching stopping layer and the second etching stopping layer on the bed of material, and to the first etching stopping layer and the second etching stopping layer into The vertical ion implanting of row, to change the etching speed of first etching stopping layer and the second etching stopping layer in horizontal direction Rate keeps it different from the etch-rate of first etching stopping layer and the second etching stopping layer on vertical direction, finally goes Except first etching stopping layer and the second etching stopping layer in fin sidewall described on vertical direction, on retention level direction First etching stopping layer and the second etching stopping layer finally removed on the fin with protecting the spacer material layer The laying or dummy gate dielectric layer, the first etching stopping layer and the second etching stopping layer protect institute in this process It is not damaged to state spacer material layer.
The present invention avoids the etching removal part spacer material layer during the preparation process by the method, to make Fin bottom scale reduces, the problem of reducing the performance of device, further improves the performance of semiconductor devices and good Rate.
Fig. 2 is the specifically semiconductor devices preparation flow figure described in embodiment of the present invention one, specifically includes:
Step S1: semiconductor substrate is provided, several fins being spaced apart from each other is formed on the semiconductor substrate and covers Cover the spacer material layer of the fin bottom, wherein the surface of the fin is formed with laying；
Step S2: sequentially formed on the spacer material layer and the laying of exposing the first etching stopping layer and Second etching stopping layer, to cover the spacer material layer and the laying；
Step S3: second etching stopping layer and described first in the horizontal direction on the spacer material layer is lost It carves stop-layer and carries out ion implanting, so that first etching stopping layer and second etching on the spacer material layer stop The only etching speed of the etch-rate of layer and first etching stopping layer and second etching stopping layer on the laying Rate is different；
Step S4: removing second etching stopping layer on the laying, to expose first etching stopping layer；
Step S5: first etching stopping layer and the laying for removing exposing are gone simultaneously with exposing the fin Except remaining second etching stopping layer, to expose first etching stopping layer on the spacer material layer.
Embodiment two
The present invention also provides a kind of semiconductor devices, the present invention also provides a kind of semiconductor devices, the semiconductor Device selects method preparation described in embodiment 1.
The semiconductor devices includes:
Semiconductor substrate 101, the semiconductor substrate include NMOS and PMOS；
Fin 102 is located in the semiconductor substrate, and the fin is in terraced structure, wherein the terraced structure；
Spacer material layer 104, be located at the semiconductor substrate on and covering part described in fin；
Etching stopping layer 106, positioned at the top of the spacer material layer.
Wherein, the semiconductor substrate 101 can be following at least one of the material being previously mentioned: on silicon, insulator Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator (SiGeOI) and germanium on insulator (GeOI) etc..
Wherein the semiconductor substrate 101 includes logic area and active area, wherein can be formed in the active area SRAM device, the active area further comprises NMOS area and PMOS area, to form NMOS device in subsequent steps And PMOS device.
Wherein, the material of spacer material layer can choose oxide, such as HARP.In one embodiment, using having The chemical vapor deposition process of flowability implements the deposition.
The etching stopping layer is located above the spacer material layer, can select nitride and/or oxide.
Etching stopping layer is formed on spacer material layer in semiconductor devices of the present invention, to the spacer material layer Upper formation protection, using the etching stopping layer as stop-layer, prevents from damaging spacer material layer, therefore avoid and preparing The etching removal part spacer material layer reduces the performance of device so that fin bottom scale be made to reduce in the process The problem of, further improve the performance and yield of semiconductor devices.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two.Wherein, semiconductor device Part is semiconductor devices described in embodiment two, or the semiconductor devices that the preparation method according to embodiment one obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (10)

1. a kind of preparation method of semiconductor devices, comprising:
Step S1: providing semiconductor substrate, form several fins being spaced apart from each other on the semiconductor substrate, the fin Surface is formed with laying, forms the spacer material layer for covering the fin bottom and the laying bottom, exposed portion institute State fin and the part laying；
Step S2: the first etching stopping layer and second are sequentially formed on the spacer material layer and the laying of exposing Etching stopping layer, to cover the laying of the spacer material layer and exposing；
Step S3: in the horizontal direction on the spacer material layer second etching stopping layer and it is described first etching stop Only layer carries out ion implanting, so that first etching stopping layer and second etching stopping layer on the spacer material layer Etch-rate and the laying on first etching stopping layer and second etching stopping layer etch-rate not Together；
Step S4: removing second etching stopping layer on the laying, to expose described first on the laying Etching stopping layer；
Step S5: first etching stopping layer and the laying on the laying are removed, to expose the fin, together When remove second etching stopping layer on the spacer material layer, to expose first erosion on the spacer material layer Carve stop-layer.
2. the method according to claim 1, wherein in the step S3, to second etching stopping layer Si ion implantation is carried out with first etching stopping layer, to change first etching stopping layer in horizontal direction and described The etch-rate of second etching stopping layer.
3. the method according to claim 1, wherein with vertical direction to described on the spacer material layer Two etching stopping layers and first etching stopping layer carry out ion implanting, and the tilt angle in the ion implanting direction is 0.
4. the method according to claim 1, wherein first etching stopping layer selects nitride.
5. the method according to claim 1, wherein second etching stopping layer selects oxide.
6. the method according to claim 1, wherein the step S1 includes:
Step S11: providing the semiconductor substrate, forms pad oxide skin(coating) on the semiconductor substrate, wherein described partly to lead Body substrate includes NMOS area and PMOS area；
Step S12: first kind ion implanting is executed in the NMOS area and is held in the PMOS area with forming p-well Row Second Type ion implanting, to form N trap；
Step S13: patterned mask layer is formed on the semiconductor substrate and using the mask layer as described in mask etch Semiconductor substrate, to form the fin in the NMOS area and the PMOS area respectively.
7. according to the method described in claim 6, it is characterized in that, the step S1 further include:
Step S14: the laying is formed on the surface of the fin, to cover the fin；
Step S15: depositing isolation material layer, to cover the laying；
Step S16: spacer material layer described in etch-back, with the laying in fin sidewall described in exposed portion.
8. the method according to the description of claim 7 is characterized in that the step S1 further include:
Step S17: channel stop ion implanting is carried out to the fin of spacer material layer covering；
Step S18: it removes the mask layer on the fin and anneals.
9. a kind of semiconductor devices that the method as described in one of claim 1 to 8 is prepared.
10. a kind of electronic device, including semiconductor devices as claimed in claim 9.
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