CN103165428A - Method for manufacturing semiconductor device - Google Patents
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- CN103165428A CN103165428A CN2011104165137A CN201110416513A CN103165428A CN 103165428 A CN103165428 A CN 103165428A CN 2011104165137 A CN2011104165137 A CN 2011104165137A CN 201110416513 A CN201110416513 A CN 201110416513A CN 103165428 A CN103165428 A CN 103165428A
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Abstract
The invention discloses a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device comprises that a semiconductor substrate is provided, wherein a fin and a grid electrode vertically striding the fin are formed on the semiconductor substrate, and a sacrificial layer is further formed on the grid electrode. Side wall material layers are formed on two sides of the grid electrode and the sacrificial layer which are on the semiconductor substrate, backing-etching technology is carried out side wall material layers to enable the upper surface of the sacrificial layer to be higher than the upper surfaces of the side wall material layers, a first masking film layer is formed and covers the side wall material layer of one side of the sacrificial layer and part of the sacrificial layer, second masking film layers are formed on the first masking film layer, the other side of the sacrificial layer and the sacrificial layer, dry etching is carried out on the first masking film layer and the second masking film layers so that side wall masking film layers which are different in width are formed on two sides of the sacrificial layer, and the side wall masking film layers are used as masking films to carry out etching on the side wall material layers so that asymmetric side walls are formed on the two sides of the grid electrode. The method for manufacturing the semiconductor device can reduce parasitic capacitance, and meanwhile, the method for manufacturing the semiconductor device can further improve the speed of FinFET to some extent.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method of making semiconductor device.
Background technology
Constantly dwindling of dimensions of semiconductor devices is to promote the improved principal element of ic manufacturing technology.Due to the restriction of the junction depth of the thickness of adjusting gate oxide layers and source/drain electrode, very difficult planar MOSFET device with routine is contracted to the technique below 32nm, therefore, has developed multiple gate field effect transistor (Multi-Gate MOSFET).Multiple gate field effect transistor is a kind of MOSFET that a plurality of grids is incorporated into individual devices, this means, raceway groove is surrounded by a plurality of grids on a plurality of surfaces, therefore can suppress better the leakage current of " cut-off " state.In addition, multiple gate field effect transistor can also strengthen the drive current under " conducting " state.
Typical multiple gate field effect transistor is fin-shaped field effect transistor (FinFET), and it makes the size of device less, and performance is higher.FinFET comprises narrow and fin independently, and fin extends from Semiconductor substrate, for example, etches in the silicon layer of Semiconductor substrate.The raceway groove of FinFET is formed in this fin, and on fin and both sides are with grid.
Because source/drain electrode in FinFET can be elevated, therefore cause forming parasitic capacitance between source/drain electrode and grid.In order to reduce parasitic capacitance, usually can increase the thickness of gate lateral wall.Yet the thickness of sidewall has determined the doped region of source/drain electrode to the distance of grid, if increase the thickness of gate lateral wall, can reduce the speed of FinFET.
Therefore, be badly in need of at present a kind of method of making semiconductor device, to address the above problem.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method of making semiconductor device, comprise: Semiconductor substrate a) is provided, be formed with fin on described Semiconductor substrate and vertically stride across the grid of described fin, also be formed with sacrifice layer on described grid, the described grid on described Semiconductor substrate and the both sides of described sacrifice layer are formed with the side-wall material layer; B) described side-wall material layer is carried out etch-back technics, so that the upper surface of described sacrifice layer is higher than the upper surface of described side-wall material layer; C) form the first mask layer, described the first mask layer covers the described side-wall material layer of described sacrifice layer one side and the part of described sacrifice layer; D) form the second mask layer on the opposite side of described the first mask layer, described sacrifice layer and described sacrifice layer; E) described the first mask layer and described the second mask layer are carried out dry etching, form the sidewall mask layer with different in width with the both sides at described sacrifice layer; And f) take described sidewall mask layer as mask, described side-wall material layer is carried out etching, to form asymmetrical sidewall in described grid both sides.
Mask layer when preferably, described sacrifice layer is for the described grid of formation.
Preferably, the material of described sacrifice layer is silicon oxynitride or metal.
Preferably, the upper surface of described sacrifice layer is higher than the upper surface 5-15nm of described side-wall material layer.
Preferably, the material of described the first mask layer is one or more in silica, silicon nitride, advanced pattern formed material and siliceous bottom anti-reflective material.
Preferably, the material of described the second mask layer is one or more in silica, silicon nitride, advanced pattern formed material and siliceous bottom anti-reflective material
Preferably, described the first mask layer and described the second mask layer are to be formed by identical material.
Preferably, described method is at described f) also comprise the step of removing described sidewall mask layer after step.
Preferably, the device architecture of described a) step obtains by the following method: Semiconductor substrate is provided; Form fin on described Semiconductor substrate; Forming the grid that strides across described fin and the sacrifice layer that is positioned on described grid on described Semiconductor substrate; And the both sides of the described grid on described Semiconductor substrate and described sacrifice layer form the side-wall material layer.
Preferably, described Semiconductor substrate is silicon-on-insulator.
The present invention forms asymmetrical sidewall by the both sides at grid, not only can reduce parasitic capacitance, simultaneously can also reduce the doped region of source electrode or drain electrode to the distance of grid, improve the migration rate of conducting particles, therefore improve to a certain extent the speed of FinFET.In addition, method of the present invention can also be used for having the different source electrode and the drain electrode that mix up distance (distance of source/drain-to-gate) in grid both sides formation, and can be used for carrying out the situation of the Implantation of different angles.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 makes the semiconductor device technology flow chart according to one embodiment of the present invention;
Fig. 2 A-2K is for making the cutaway view of the device that in the semiconductor device technology flow process, each step obtains according to one embodiment of the present invention; And
Fig. 3 is the vertical view according to the semiconductor device of one embodiment of the present invention making.
Embodiment
Next, in connection with accompanying drawing, the present invention is described more intactly, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, perhaps can have between two parties element or layer.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, do not have between two parties element or layer.
Fig. 1 shows according to one embodiment of the present invention and makes the semiconductor device technology flow chart, Fig. 2 A-2K shows the cutaway view of making the device that in the semiconductor device technology flow process, each step obtains according to one embodiment of the present invention, and Fig. 3 is the vertical view according to the semiconductor device of one embodiment of the present invention making.Wherein, the cutaway view of Fig. 2 A-2K for dissecing along fin is namely along the cutaway view shown in the A-A line in Fig. 3.Should be noted in the discussion above that the part of devices structure in semiconductor device can make flow process manufacturing by CMOS, therefore before method of the present invention, among or can provide extra technique afterwards, and wherein some technique is only done simple description at this.Describe manufacture method of the present invention in detail below in conjunction with Fig. 1 and Fig. 2 A-2K.
Execution in step 101 provides Semiconductor substrate, is somebody's turn to do the grid that be formed with fin and vertically strode across fin on Semiconductor substrate, also is formed with sacrifice layer on grid, and the grid on Semiconductor substrate and the both sides of sacrifice layer are formed with the side-wall material layer.
As shown in Fig. 2 A, Semiconductor substrate 200 is provided, and what Semiconductor substrate 200 can be in the following material of mentioning is at least a: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferably, Semiconductor substrate 200 is silicon-on-insulator.Can be formed with doped region and/or isolation structure in Semiconductor substrate 200, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Also be formed with cmos device in Semiconductor substrate 200, cmos device is for example transistor (for example, NMOS and/or PMOS) etc.In order to simplify, only represent Semiconductor substrate 200 with a blank herein.In addition, the upper surface of Semiconductor substrate 200 also comprises the insulating barrier (not shown), and insulating barrier can comprise silica, sapphire and/or other insulating material that is fit to.
Be formed with fin 201 on Semiconductor substrate 200, as example, fin 201 can obtain by Semiconductor substrate 200 being carried out etching.In addition, also be formed with the grid 202 that vertically strides across fin 201 on Semiconductor substrate 200, wherein, the material of grid 202 can be polysilicon.Can also be formed with the gate oxide layers (not shown) between grid and Semiconductor substrate.Can also be formed with sacrifice layer 203 on grid 202.Preferably, sacrifice layer 203 is the mask layer when forming grid 202, to reduce processing step.As example, the material of sacrifice layer 203 is silicon oxynitride or metal.
As shown in Fig. 2 B, form side-wall material layer 204 on the device architecture shown in Fig. 2 A, side-wall material layer 204 should be enough thick so that carry out after flatening process its energy surface can be contour with sacrifice layer 203.
As shown in Fig. 2 C, carry out chemical mechanical milling tech, to the upper surface that exposes sacrifice layer 203, be formed with side-wall material layer 204 with the both sides of the grid 202 on Semiconductor substrate 200 and sacrifice layer 203.
Execution in step 102, the oppose side wall material layer is carried out etch-back technics, so that the upper surface of sacrifice layer is higher than the upper surface of side-wall material layer.
As shown in Fig. 2 D, oppose side wall material layer 204 is carried out etch-back technics, so that the upper surface of sacrifice layer 203 is higher than the upper surface of side-wall material layer 204.Wherein, this etch-back technics can be dry etching.In order to form the sidewall of suitable width through subsequent technique, preferably, the upper surface of sacrifice layer 203 is higher than the upper surface 5-15nm of side-wall material layer 204.
Execution in step 103 forms the first mask layer, the side-wall material layer of this first mask layer cover gate one side and the part of grid.
As shown in Fig. 2 E, form the first mask layer 205 on sacrifice layer 203 and side-wall material layer 204.Preferably, the material of the first mask layer 205 can be silica, silicon nitride, advanced pattern (Advanced Pattern Film, APF) one or more in material and siliceous bottom anti-reflective (Si-BARC) material, in order to can be removed at an easy rate after its function is completed, material layer below it has very high selection ratio when removing simultaneously, to avoid damaging following material layer.
As shown in Fig. 2 F, form photoresist layer 206 on the first mask layer 205, wherein, photoresist layer 206 covers the side-wall material layer 204 of sacrifice layer 203 1 sides and the part of sacrifice layer 203.Then, take photoresist layer 206 as mask, the first mask layer 205 is carried out etching, with on design transfer to the first mask layer 205.
As shown in Fig. 2 G, remove photoresist layer 206, with the first mask layer 205 of the part that forms the side-wall material layer 204 that covers sacrifice layer 203 1 sides and sacrifice layer 203.
Need to prove, the method for the first mask layer 205 of the side-wall material layer 204 of above-mentioned formation covering sacrifice layer 203 1 sides and the part of sacrifice layer 203 is only exemplary, therefore, is not construed as limiting the invention.
Execution in step 104 forms the second mask layer on the opposite side of the first mask layer, sacrifice layer and sacrifice layer.
As shown in Fig. 2 H, form the second mask layer 206 on the opposite side of the first mask layer 205, sacrifice layer 203 and sacrifice layer 203.Preferably, the material of the second mask layer 206 can be silica, silicon nitride, advanced pattern (Advanced Pattern Film, APF) one or more in material and siliceous bottom anti-reflective (Si-BARC) material, in order to can be removed at an easy rate after its function is completed, material layer below it has very high selection ratio when removing simultaneously, to avoid damaging following material layer.
The first mask layer 205 and the second mask layer 206 can be to be formed by identical material, can be also to be formed by different materials.Preferably, the first mask layer 205 and the second mask layer 206 are to be formed by identical material, in order to can complete the etching of the first mask layer 205 and the second mask layer 206 through a step etching technics, and remove the first mask layer 205 and the second mask layer 206 through step removal technique.
Execution in step 105 is carried out dry etching to the first mask layer and the second mask layer, forms the sidewall mask layer with different in width with the both sides that are formed on sacrifice layer.
As shown in Fig. 2 I, the first mask layer 205 and the second mask layer 206 are carried out dry etching, form sidewall mask layer 207 with the both sides at sacrifice layer 203.Because the side at sacrifice layer 203 only is formed with the second mask layer 206, and be formed with simultaneously the first mask layer 205 and the second mask layer 206 at the opposite side of sacrifice layer 203, therefore, can form the sidewall mask layer 207 with different in width in the both sides of sacrifice layer 203 after dry etching.
Execution in step 106 is carried out etching take the sidewall mask layer as mask oppose side wall material layer, to form asymmetrical sidewall in grid both sides.
As shown in Fig. 2 J, carry out etching take sidewall mask layer 207 as mask oppose side wall material layer 204, to form asymmetrical sidewall 208 (as shown in Figure 3) in grid 202 both sides.Have different width because the sidewall mask layer 207 of sacrifice layer 203 both sides forms, therefore, can form in grid 202 both sides asymmetrical sidewall 208, namely form the sidewall 208 with different in width.
Form asymmetrical sidewall 208 in the both sides of grid 202 and can reduce parasitic capacitance, reduce simultaneously the doped region of source electrode or drain electrode to the distance of grid, improve the migration rate of conducting particles, therefore improved to a certain extent the speed of FinFET.In addition, method of the present invention can also be used for having the different source electrode and the drain electrode that mix up distance (distance of source/drain-to-gate) in grid both sides formation, and can be used for carrying out the situation of the Implantation of different angles.
The method according to this invention also comprises the step of removing sidewall mask layer 207, as shown in Fig. 2 K.As example, the first mask layer 205 and the second mask layer 206 are formed by the APF material, can remove with the method for ashing, can select O
2, N
2Base or H
2The fogging agent of base.As example, the first mask layer 205 and the second mask layer 206 are formed by the Si-BARC material, can remove with wet method.In addition, if also have remaining sacrifice layer 203 on grid 202 after to the first mask layer 205 and the second mask layer 206 execution dry etchings, method of the present invention also comprises the step of removing sacrifice layer 203.
Need to prove, although accompanying drawing only illustrates principle of the present invention with a fin 201, can comprise a plurality of fins 201 on Semiconductor substrate 200.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. method of making semiconductor device comprises:
A) provide Semiconductor substrate, be formed with fin on described Semiconductor substrate and vertically stride across the grid of described fin, also be formed with sacrifice layer on described grid, the described grid on described Semiconductor substrate and the both sides of described sacrifice layer are formed with the side-wall material layer;
B) described side-wall material layer is carried out etch-back technics, so that the upper surface of described sacrifice layer is higher than the upper surface of described side-wall material layer;
C) form the first mask layer, described the first mask layer covers the described side-wall material layer of described sacrifice layer one side and the part of described sacrifice layer;
D) form the second mask layer on the opposite side of described the first mask layer, described sacrifice layer and described sacrifice layer;
E) described the first mask layer and described the second mask layer are carried out dry etching, form the sidewall mask layer with different in width with the both sides at described sacrifice layer; And
F) take described sidewall mask layer as mask, described side-wall material layer is carried out etching, to form asymmetrical sidewall in described grid both sides.
2. the method for claim 1, is characterized in that, described sacrifice layer is the mask layer when forming described grid.
3. method as claimed in claim 2, is characterized in that, the material of described sacrifice layer is silicon oxynitride or metal.
4. the method for claim 1, is characterized in that, the upper surface of described sacrifice layer is higher than the upper surface 5-15nm of described side-wall material layer.
5. the method for claim 1, is characterized in that, the material of described the first mask layer is one or more in silica, silicon nitride, advanced pattern formed material and siliceous bottom anti-reflective material.
6. method as claimed in claim 5, is characterized in that, the material of described the second mask layer is one or more in silica, silicon nitride, advanced pattern formed material and siliceous bottom anti-reflective material.
7. the method for claim 1, is characterized in that, described the first mask layer and described the second mask layer are to be formed by identical material.
8. the method for claim 1, is characterized in that, described method is at described f) also comprise the step of removing described sidewall mask layer after step.
9. the method for claim 1, is characterized in that, the device architecture of described a) step obtains by the following method:
Semiconductor substrate is provided;
Form fin on described Semiconductor substrate;
Forming the grid that strides across described fin and the sacrifice layer that is positioned on described grid on described Semiconductor substrate; And
Described grid on described Semiconductor substrate and the both sides of described sacrifice layer form the side-wall material layer.
10. the method for claim 1, is characterized in that, described Semiconductor substrate is silicon-on-insulator.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106601618A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof and electronic device |
| CN107968053A (en) * | 2016-10-20 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107978526A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor structure |
| CN109698163A (en) * | 2017-10-20 | 2019-04-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN111863619A (en) * | 2019-04-29 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112017961A (en) * | 2019-05-30 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106601618A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof and electronic device |
| CN106601618B (en) * | 2015-10-15 | 2019-12-10 | 中芯国际集成电路制造(上海)有限公司 | semiconductor device, manufacturing method thereof and electronic device |
| CN107968053A (en) * | 2016-10-20 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107978526A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor structure |
| CN107978526B (en) * | 2016-10-25 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor structure |
| CN109698163A (en) * | 2017-10-20 | 2019-04-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN111863619A (en) * | 2019-04-29 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112017961A (en) * | 2019-05-30 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112017961B (en) * | 2019-05-30 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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