CN110729245A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN110729245A
CN110729245A CN201810778082.0A CN201810778082A CN110729245A CN 110729245 A CN110729245 A CN 110729245A CN 201810778082 A CN201810778082 A CN 201810778082A CN 110729245 A CN110729245 A CN 110729245A
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layer
fin
region
forming
semiconductor device
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201810778082.0A priority Critical patent/CN110729245A/en
Publication of CN110729245A publication Critical patent/CN110729245A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor device and a method of manufacturing the same, the method including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, and the first fin and the second fin comprise an Si layer and an SiGe layer which are alternately stacked; forming a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; forming first grooves at two sides of the first pseudo grid electrode, and forming second grooves at two sides of the second pseudo grid electrode; removing part of the SiGe layer exposed on the side wall of the first groove to form a first groove, and removing part of the SiGe layer exposed on the side wall of the second groove to form a second groove; forming a first sidewall filling the first groove; a first stress layer is formed in the first trench. The semiconductor device and the manufacturing method thereof provided by the invention can reduce the parasitic capacitance between the grid electrode and the stress layer and improve the performance of the semiconductor device.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, as the semiconductor industry has progressed to the point of nanotechnology process in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limitations.
As CMOS device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs, such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET is an advanced semiconductor device for process nodes of 20nm and below, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, a grid electrode in the FinFET is arranged around the fin, so that static electricity can be controlled from three surfaces, and the performance in the aspect of static electricity control is more outstanding.
However, as semiconductor device density and size continue to increase and shrink, the conventional finfet process cannot meet the demand of shrinking process nodes. The fully-surrounding gate field effect transistor is used as a new device structure and can reach 7/5nm process nodes. However, the parasitic capacitance between the epitaxial layer and the metal gate of a Gate All Around (GAA) field effect transistor is large, thereby adversely affecting the performance of the semiconductor device.
Therefore, in order to solve the above problems, it is necessary to provide a new semiconductor device and a method for manufacturing the same.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, and the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked;
forming a first dummy gate crossing the first fin and a second dummy gate crossing the second fin;
forming a first trench in the first fin on both sides of the first dummy gate, and forming a second trench in the second fin on both sides of the second dummy gate;
removing the part of the SiGe layer exposed by the side wall of the first groove to form a first groove, and removing the part of the SiGe layer exposed by the side wall of the second groove to form a second groove;
forming a first sidewall filling the first groove;
a first stress layer is formed in the first trench.
Illustratively, the method of forming the first sidewall includes:
forming a sidewall material layer covering the first trench, the first dummy gate, the second trench and the second dummy gate;
forming a mask layer covering the second area;
and removing the part, outside the first groove, of the side wall material layer in the first area to form a first side wall.
Illustratively, after the step of forming the first stress layer, the method further comprises:
forming a cap layer covering the first region;
removing the part, outside the second groove, of the side wall material layer in the second area to form a second side wall;
and forming a second stress layer in the second groove.
Illustratively, after the step of forming the first sidewall and before the step of forming the first stress layer, the method further comprises: and removing the exposed part of the Si layer on the side wall of the first groove.
Illustratively, the sidewall material layer includes an oxide layer or a silicon nitride layer.
Illustratively, the first stress layer comprises a boron doped SiGe layer.
Illustratively, the second stress layer comprises a SiP layer or a SiCP layer.
Illustratively, the first region is a PMOS region and the second region is an NMOS region.
The present invention also provides a semiconductor device including:
the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked, and the width of the SiGe layers is smaller than that of the Si layers;
first side walls formed on two sides of the SiGe layer in the first fin;
a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; and
and the first stress layer is formed in the first fins at two sides of the first dummy gate.
Illustratively, the semiconductor device further includes:
second side walls formed on two sides of the SiGe layer in the second fin; and
and the second stress layer is formed in the second fins at two sides of the second dummy gate.
Illustratively, the width of the Si layer in the first fin is less than the width between the outer edges of the adjacent first sidewalls.
Illustratively, the material of the first sidewall and/or the second sidewall comprises oxide or silicon nitride.
Illustratively, the first stress layer comprises a boron doped SiGe layer.
Illustratively, the second stress layer comprises a SiP layer or a SiCP layer.
Illustratively, the first region is a PMOS region and the second region is an NMOS region.
The semiconductor device and the manufacturing method thereof provided by the invention can reduce the parasitic capacitance between the grid electrode and the stress layer and improve the performance of the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 shows a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2A-2L are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
With the continuous increase of the density and the continuous reduction of the size of semiconductor devices, the existing fin field effect transistor manufacturing process cannot meet the requirement of continuously reduced process nodes. The all-around gate field effect transistor can reach a 7nm process node. A method of manufacturing a fully-wrapped-gate field effect transistor includes: firstly, forming a fin formed by Si/SiGe alternate stacking, then selectively removing a SiGe layer after removing a dummy gate electrode and a dummy gate dielectric layer, and forming a metal gate surrounding a Si channel and stress layers positioned on two sides of the metal gate. However, the fully-wrapped-gate field effect transistor formed by the method has a large parasitic capacitance between the stress layer and the metal gate.
In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, and the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked; forming a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; forming a first trench in the first fin on both sides of the first dummy gate, and forming a second trench in the second fin on both sides of the second dummy gate; removing the part of the SiGe layer exposed by the side wall of the first groove to form a first groove, and removing the part of the SiGe layer exposed by the side wall of the second groove to form a second groove; forming a first sidewall filling the first groove; a first stress layer is formed in the first trench.
The present invention also provides a semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked, and the width of the SiGe layers is smaller than that of the Si layers; first side walls formed on two sides of the SiGe layer in the first fin; a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; and a first stress layer formed in the first fin at two sides of the first dummy gate.
The semiconductor device and the manufacturing method thereof provided by the invention can reduce the parasitic capacitance between the grid electrode and the stress layer and improve the performance of the semiconductor device.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to fig. 1 and fig. 2A to 2L. Fig. 2A to 2B are cross-sectional views of the semiconductor device perpendicular to the extending direction of the fins, and fig. 2C to 2L are cross-sectional views of the semiconductor device perpendicular to the extending direction of the gates.
First, step 101 is performed, as shown in fig. 2A, a semiconductor substrate 200 is provided, the semiconductor substrate includes a first region and a second region, a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, and the first fin and the second fin include an Si layer 204 and an SiGe layer 203 which are alternately stacked.
Wherein the semiconductor substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment, the semiconductor substrate 200 is a single crystal silicon substrate.
In this embodiment, the semiconductor substrate 200 includes a first region and a second region, wherein the first region is a PMOS region and the second region is an NMOS region, and a PMOS device and an NMOS device are formed in the first region and the second region, respectively.
Next, the Si layer 204 and the SiGe layer 203 are alternately stacked on the semiconductor substrate. In the present embodiment, the alternately stacked Si layers 204 and SiGe layers 203 are Si/SiGe/Si stacks. The SiGe layer 203 in the stack is used to form the gate later and the Si layer 203 is used to form the channel layer of the GAA transistor. An epitaxial process may be used to form the stack.
The alternating stack of Si layers 204 and SiGe layers 203 is then etched to form the fins. Specifically, the fins include a first fin formed in the PMOS region and a second fin formed in the NMOS region. The etching method comprises an anisotropic dry etching process. The dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method may be used, or more than one etching method may be used.
Illustratively, after the fin is formed, a linear oxide layer 201 is formed on the sidewall of the fin, so that the surface of the fin is smooth and the crystal lattice quality is improved. Moreover, the formed linear oxide layer is also beneficial to improving the interface performance between the subsequently formed isolation layer 202 and the fin.
Next, spacers 202 are formed between the fins. The spacer layer 202 serves to electrically isolate adjacent fins. The isolation layer 202 is made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 202 is made of silicon oxide, and the isolation layer 202 may be formed by using a Flowable Chemical Vapor Deposition (FCVD) or a high aspect ratio chemical vapor deposition (HARP CVD). Then, a portion of the thickness of the spacer 202 is removed to expose the fins. The isolation layer 202 may be etched to remove a portion of the thickness by a dry etching process, a wet etching process, or a combination of dry etching and wet etching.
Next, step 102 is performed, as shown in fig. 2B and 2C, a first dummy gate crossing the first fin and a second dummy gate crossing the second fin are formed. The first dummy gate and the second dummy gate are formed in the PMOS region and the NMOS region, respectively.
Specifically, a dummy gate dielectric layer 205 is first formed overlying the fins. The material of the dummy gate dielectric layer comprises silicon oxide or high-k dielectric material. Next, a dummy gate electrode layer 206 is formed. The material of the dummy gate electrode layer 206b includes polysilicon, silicon nitride, or amorphous carbon, and polysilicon is selected in this embodiment. Next, a patterned hard mask layer is formed on the dummy gate electrode layer 206b, and the dummy gate electrode layer 206b is etched using the hard mask layer as a mask.
Further, as an example, spacer structures 207 are also formed on both sides of the first and second dummy gates. In one embodiment, the spacer structure 207 comprises at least an oxide layer and a nitride layer.
Next, step 103 is performed, as shown in fig. 2D, a first trench 208 is formed in the first fin on both sides of the first dummy gate, and a second trench 209 is formed in the second fin on both sides of the second dummy gate. The trench may be formed by dry etching, wet etching, or a process of first dry etching and then wet etching. The sidewalls of the trench expose the Si layer 204 and the SiGe layer 203 that make up the fin.
Step 104 is performed, as shown in fig. 2E, to remove a portion of the SiGe layer 203 exposed by the sidewall of the first trench to form a first recess, and to remove a portion of the SiGe layer 203 exposed by the sidewall of the second trench to form a second recess.
Specifically, a wet etching process may be used to selectively remove a portion of the SiGe layer 203 via the sidewalls of the trench by using an etching selectivity between the Si layer 204 and the SiGe layer 203, thereby forming a groove extending in a lateral direction between adjacent Si layers 204.
Next, step 105 is performed to form a first sidewall filling the first groove.
Specifically, first, as shown in fig. 2F, a sidewall material layer 210 covering the first trench, the first dummy gate, the second trench, and the second dummy gate is formed. The sidewall material layer 210 fills the first and second recesses. In one embodiment, the sidewall material layer 210 is a silicon oxide material layer formed using an Atomic Layer Deposition (ALD) process. In another embodiment, the sidewall material layer 210 is a silicon nitride material layer formed by a Chemical Vapor Deposition (CVD) process.
Next, as shown in fig. 2G, a mask layer 211 covering the second region is formed. Illustratively, the mask layer 211 is a patterned photoresist layer. A photoresist layer may be spin-coated on the surface of the device, and then the photoresist layer may be patterned by exposure, development, and the like to cover the second region, with the window corresponding to the first region.
Next, the portion of the sidewall material layer 210 outside the first groove in the first region is removed to form a first sidewall. Specifically, the mask layer 211 is used as a mask to etch the sidewall material layer 210, and the etching process includes an anisotropic dry etching process. The dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method may be used, or more than one etching method may be used. The etch removes portions of the sidewall material layer 210 in the first region outside the first recess, thereby forming first sidewalls in the first recess in the first fin, which abut both sides of the SiGe layer 203.
Optionally, as shown in fig. 2H, after forming the first sidewall, removing the exposed portion of the Si layer 204 on the sidewall of the first trench 208 is further included. This step may be used to adjust the width of the subsequently formed Si channel. Next, ashing or the like may be used to remove the mask layer 211.
Next, step 106 is performed, as shown in fig. 2I, a first stress layer 212 is formed in the first trench.
Illustratively, when the first region is a PMOS region, the first stress layer 212 comprises a boron doped silicon germanium layer. The embedded sige layer 212 may be formed to completely fill the first trench using a selective epitaxial growth process, which may use one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE), the formed embedded sige layer 212 may be doped with boron.
Next, as shown in fig. 2J and 2K, a cap layer 213 is formed to cover the first region.
Specifically, first, as shown in fig. 2J, a cap layer 213 is deposited to cover the first region and the second region. The material of the cap layer 213 includes silicon nitride, and the cap layer 213 may be formed by using a chemical vapor deposition, a physical vapor deposition, or an atomic layer deposition.
Next, as shown in fig. 2K, an etching process is performed to remove the cap layer 213 formed in the second region. The etching process includes, but is not limited to, a dry etching process or a wet etching process.
Next, with reference to fig. 2K, the portion of the sidewall material layer 210 outside the second groove in the second region is removed to form a second sidewall. Specifically, the sidewall material layer 210 is etched by using the capping layer 213 as a mask, and the etching process includes an anisotropic dry etching process. The etch removes portions of the sidewall material layer 210 in the second region outside the second recess, thereby forming second sidewalls in the second recess in the second fin, which abut both sides of the SiGe layer 203.
Next, as shown in fig. 2L, a second stress layer 214 is formed in the second trench.
When the second region is an NMOS region, the second stress layer 214 includes a SiP layer or a SiCP layer. A SiP layer or a SiCP layer may be formed using a selective epitaxial growth process to completely fill the second trench. The selective epitaxial growth process may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above-described steps but also other necessary steps before, during or after the above-described steps, which are included in the scope of the manufacturing method of the present embodiment.
Other preceding steps, intermediate steps or subsequent steps are also required for the manufacturing process of the complete semiconductor device, such as a back-end-of-line process (BEOL) for forming an interconnect structure electrically connected to the gate structure and the source/drain region, respectively, and are not described herein again.
The manufacturing method of the semiconductor device provided by the invention can reduce the parasitic capacitance between the grid electrode and the stress layer and improve the performance of the semiconductor device.
Referring to fig. 2L, a schematic cross-sectional view of a semiconductor device provided in accordance with an embodiment of the present invention is shown. The semiconductor device may be manufactured by the above-described method.
As shown, the semiconductor device includes: a semiconductor substrate 200 including a first region and a second region, on which a first fin and a second fin are formed, respectively, the first fin and the second fin including a Si layer 204 and a SiGe layer 203 alternately stacked, wherein a width of the SiGe layer 203 is smaller than a width of the Si layer 204; first sidewalls formed on both sides of the SiGe layer 204 in the first fin; a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; and a first stress layer 212 formed in the first fin at both sides of the first dummy gate. In one embodiment, the semiconductor device further includes: second sidewalls formed on both sides of the SiGe layer 203 in the second fin; and a second stress layer 214 formed in the second fin on both sides of the second dummy gate. The first region is a PMOS region, and the second region is an NMOS region.
In one embodiment, the width of the Si layer 204 in the first fins is less than the width between the outer edges of the adjacent first sidewalls.
Illustratively, the material of the first sidewall and/or the second sidewall comprises oxide or silicon nitride. The first stress layer 212 comprises a boron doped SiGe layer. The second stress layer 214 includes a SiP layer or a SiCP layer.
The specific structure of the semiconductor device may refer to the description of the corresponding parts above, and is not described herein again for brevity.
The semiconductor device provided by the invention can reduce the parasitic capacitance between the grid electrode and the stress layer and improve the performance of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (15)

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, and the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked;
forming a first dummy gate crossing the first fin and a second dummy gate crossing the second fin;
forming a first trench in the first fin on both sides of the first dummy gate, and forming a second trench in the second fin on both sides of the second dummy gate;
removing the part of the SiGe layer exposed by the side wall of the first groove to form a first groove, and removing the part of the SiGe layer exposed by the side wall of the second groove to form a second groove;
forming a first sidewall filling the first groove;
a first stress layer is formed in the first trench.
2. The method of manufacturing of claim 1, wherein the method of forming the first sidewall comprises:
forming a sidewall material layer covering the first trench, the first dummy gate, the second trench and the second dummy gate;
forming a mask layer covering the second area;
and removing the part, outside the first groove, of the side wall material layer in the first area to form a first side wall.
3. The method of manufacturing of claim 2, further comprising, after the step of forming the first stress layer:
forming a cap layer covering the first region;
removing the part, outside the second groove, of the side wall material layer in the second area to form a second side wall;
and forming a second stress layer in the second groove.
4. The method of manufacturing of claim 1, wherein after the step of forming the first sidewall and before the step of forming the first stress layer, further comprising: and removing the exposed part of the Si layer on the side wall of the first groove.
5. The method of manufacturing of claim 2, wherein the layer of sidewall material comprises a layer of oxide or silicon nitride.
6. The method of manufacturing of claim 1, wherein the first stress layer comprises a boron doped SiGe layer.
7. The method of manufacturing of claim 1, wherein the second stress layer comprises a SiP layer or a SiCP layer.
8. The method of claim 1, wherein the first region is a PMOS region and the second region is an NMOS region.
9. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein a first fin and a second fin are respectively formed on the semiconductor substrate of the first region and the second region, the first fin and the second fin comprise Si layers and SiGe layers which are alternately stacked, and the width of the SiGe layers is smaller than that of the Si layers;
first side walls formed on two sides of the SiGe layer in the first fin;
a first dummy gate crossing the first fin and a second dummy gate crossing the second fin; and
and the first stress layer is formed in the first fins at two sides of the first dummy gate.
10. The semiconductor device according to claim 9, further comprising:
second side walls formed on two sides of the SiGe layer in the second fin; and
and the second stress layer is formed in the second fins at two sides of the second dummy gate.
11. The semiconductor device of claim 9, wherein a width of the Si layer in the first fins is less than a width between outer edges of adjacent first sidewalls.
12. The semiconductor device of claim 10, wherein a material of the first sidewall and/or the second sidewall comprises an oxide or silicon nitride.
13. The semiconductor device of claim 9, wherein the first stress layer comprises a boron doped SiGe layer.
14. The semiconductor device of claim 10, wherein the second stress layer comprises a SiP layer or a SiCP layer.
15. The semiconductor device of claim 9, wherein the first region is a PMOS region and the second region is an NMOS region.
CN201810778082.0A 2018-07-16 2018-07-16 Semiconductor device and manufacturing method thereof Pending CN110729245A (en)

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