CN104637817B - The method for making asymmetric FinFET - Google Patents
The method for making asymmetric FinFET Download PDFInfo
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- CN104637817B CN104637817B CN201310567526.3A CN201310567526A CN104637817B CN 104637817 B CN104637817 B CN 104637817B CN 201310567526 A CN201310567526 A CN 201310567526A CN 104637817 B CN104637817 B CN 104637817B
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Abstract
The invention discloses a kind of method for making asymmetric FinFET, including：SOI substrate is provided, the SOI substrate includes Semiconductor substrate, the buried insulator layer in Semiconductor substrate and the semiconductor material layer in buried insulator layer；The first opening for exposing buried insulator layer is formed in semiconductor material layer；The first dielectric layer is formed in the side wall of the semiconductor material layer exposed in the first opening；The second opening for being different from the first opening is formed in semiconductor material layer, the semiconductor material layer between the first opening and the second opening is formed as fin；The second dielectric layer is formed in the side wall of the semiconductor material layer exposed in the second opening, wherein the thickness of the second dielectric layer is different from the thickness of the first dielectric layer.This method can form the gate dielectric of different-thickness in fin both sides, to solve the problems, such as the deterioration of the S slopes in some devices.Fin can be completed while the gate dielectric of different-thickness is formed to make, and simplify processing step.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of method for making asymmetric FinFET.
Background technology
The continuous diminution of dimensions of semiconductor devices is to promote the improved principal element of ic manufacturing technology.Due to adjustment
The limitation of the thickness of gate oxide layers and the junction depth of source/drain, it is difficult to which the planar MOSFET devices of routine are contracted into 32nm
Following technique, therefore, multiple gate field effect transistor is developed（Multi-Gate MOSFET）.Multiple gate field effect
Transistor is a kind of MOSFET that multiple grids are incorporated into individual devices, it means that, raceway groove is multiple on multiple surfaces
Grid surrounds, therefore can preferably suppress the leakage current for " ending " state.In addition, multiple gate field effect transistor can also strengthen
Driving current under " conducting " state.
Typical multiple gate field effect transistor is fin-shaped field effect transistor（FinFET）, it causes the size of device more
Small, performance is higher.FinFET includes narrow and independent fin, and fin extends on the surface of Semiconductor substrate, for example, etching into
In the silicon layer of Semiconductor substrate.FinFET raceway groove is formed in the fin, and on fin and both sides carry grid.
Fig. 1 schematically shows the stereogram of the semiconductor devices 100 including existing bigrid or FinFET.Such as figure
Middle to be described, the device 100 may include the buried insulator layer of substrate 101 and formation on the substrate 101（Buried
Insulating Layer）102.Fin 110 is formed in buried insulator layer 102, and it is, for example, by being formed in buried insulation
What the silicon layer on layer 102 was formed through photoetching process.Fin 110 may include source electrode and drain electrode 111 and channel region（It is not shown）.Should
Channel region can be covered by grid 120A and 120B.Grid 120A and 120B are formed in the relative side wall with fin 110 respectively, and
Grid 120A and 120B can include gate dielectric and gate material layers respectively.By taking grid 120A as an example, it includes shape successively
Into the gate dielectric 121A and gate material layers 122A in the side wall in fin 110.The top surface of fin 110 can be by block
Layer（Cap Layer）112 coverings, the cap 112 can be formed by nitride or similar material.As illustrated in the drawing, can pass through
Electrode material connection the grid 120A and 120B formed in cap 112.
Grid 120A is main grid, and grid 120B is auxiliary grid, and it is used for the threshold voltage for adjusting main grid pole 120A, with
Just FinFET threshold voltage is dynamically changed.Leakage current-main gate voltage curve（That is Id-Vg1 curves）With auxiliary grid
Voltage Vg2 increase and smoothly drift about.However, the 4T with this class formation（4-Terminal）- FinFET is compared to 3T-
FinFET, S- slope（S-slope）Deterioration occurs.
Therefore, in order to solve the problem, the present invention provides a kind of method for making asymmetric FinFET.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of method for making asymmetric FinFET,
Including：a）SOI substrate is provided, the SOI substrate includes Semiconductor substrate, the buried insulator layer in the Semiconductor substrate
And the semiconductor material layer in the buried insulator layer；b）Formed in the semiconductor material layer and expose the burial
First opening of insulating barrier；c）The first dielectric is formed in the side wall of the semiconductor material layer exposed in the described first opening
Layer；d）In the semiconductor material layer formed be different from first opening second opening, wherein it is described first opening and it is described
Semiconductor material layer between second opening is formed as fin；And e）The semiconductor material exposed in the described second opening
The second dielectric layer is formed in the side wall of the bed of material, wherein the thickness of the thickness of second dielectric layer and first dielectric layer is not
Together.
Preferably, the b）The method of first opening is formed in step to be included：The shape on the semiconductor material layer
Into the core-material for having patterning；Clearance wall is formed in the side wall of the core-material of the patterning；With the pattern
The core-material of change and the clearance wall are that mask carries out the first etching to the semiconductor material layer, to form described first
Opening.
Preferably, the width of the core-material of the patterning is 10nm to 100nm, and/or the core of the patterning
The thickness of the heartwood bed of material is 20nm to 200nm.
Preferably, the core-material of the patterning is nitride.
Preferably, the d）The method of second opening is formed in step to be included：Remove the core material of the patterning
The bed of material；The second etching is carried out to the semiconductor material layer by mask of the clearance wall, to form second opening.
Preferably, second etching is the wet etching carried out using tetramethyl ammonium hydroxide solution.
It is further preferred that the mass percent concentration of the ammonium hydroxide solution is 2%-20%.
Preferably, silicon, first dielectric layer and second dielectric layer are contained in the semiconductor material layer using existing
What at least one of field steam generation annealing and rapid thermal treatment were formed.
Preferably, the thickness of first dielectric layer is 10A-100A, and/or the thickness of second dielectric layer is 5A-
50A。
Preferably, the semiconductor material layer is the silicon-on-insulator in 110 faces.
Method provided by the invention can form the gate dielectric of different-thickness in fin both sides, to solve prior art
In be present in some devices S- slopes deterioration the problem of.In addition, this method is forming the gate dielectric of different-thickness
The making of fin can be completed simultaneously, therefore simplifies processing step.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the stereogram of the semiconductor devices of the prior art including bigrid or FinFET；
Fig. 2 shows the process chart that asymmetric FinFET is made according to one embodiment of the present invention；And
Fig. 3 A-3I show each step in the technological process that asymmetric FinFET is made according to one embodiment of the present invention
The sectional view of the device obtained.
Embodiment
Next, the present invention will be more fully described by with reference to accompanying drawing, shown in the drawings of embodiments of the invention.But
It is that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide
These embodiments will make disclosure thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.
In accompanying drawing, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent phase from beginning to end
Same element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.
S- slopes are relevant with relationship below：
S=60（1+γ）,
Wherein γ=3Tox1/(3Tox2+Tgate), TgateFor the width of grid；Tox1For the first grid in two grid FinFET
The thickness of the gate dielectric of pole；Tox2 is the thickness of the gate dielectric of the second grid in two grid FinFET.
On this basis, the present invention proposes asymmetric finfet technology, existing to solve even if Tox1 is not equal to Tox2
Problem present in technology.In different FinFETs, the thickness of the gate dielectric of main grid pole can be made to be more than auxiliary
The thickness of the gate dielectric of grid, or make the thickness of the gate dielectric of main grid pole be less than the gate dielectric of auxiliary grid
Thickness.Specifically, the present invention provides a kind of method for making asymmetric FinFET.
Fig. 2 shows the process chart that asymmetric FinFET is made according to one embodiment of the present invention, and Fig. 3 A-3I show
Cuing open for the device that each step is obtained in the technological process according to the asymmetric FinFET of one embodiment of the present invention making is gone out
View.It should be noted that the part of devices structure in FinFET can be manufactured by CMOS Making programmes, therefore at this
Before the method for invention, among or extra technique can be provided afterwards, and some of which technique only makees simple description herein.
The preparation method for describing the present invention in detail below in conjunction with Fig. 2 and Fig. 3 A-3I.
Perform step 201, there is provided SOI substrate, the SOI substrate include Semiconductor substrate, in the Semiconductor substrate
Buried insulator layer and the semiconductor material layer in the buried insulator layer.
As shown in Figure 3A, SOI substrate includes Semiconductor substrate 300, buried insulator layer 301 and semiconductor material layer 302.
Doped region and/or isolation structure are could be formed with Semiconductor substrate 300, the isolation structure is isolated for shallow trench（STI）
Structure or selective oxidation silicon（LOCOS）Isolation structure.Cmos device, cmos device example are also formed with Semiconductor substrate 300
Transistor in this way（For example, NMOS and/or PMOS）Deng.To put it more simply, only represent Semiconductor substrate with space rectangles herein
300。
Formed with buried insulator layer 301 in Semiconductor substrate 300.In the normal operation period, buried insulator layer 301 helps
It buffer action between fin is played, can additionally reduce the junction capacity of parasitism, and then improve the speed of device.Bury exhausted
Edge layer 301 can include oxide, nitride or oxynitride.Preferably, buried insulator layer 301 is buried oxide
（Buried Oxide）Layer.Buried insulator layer 301, which can include a layer, either has identical or different component multiple layers.
Formed with semiconductor material layer 302 in buried insulator layer 301.Semiconductor material layer 302 is used for through follow-up light
Carving technology forms the fin of FinFET, and semiconductor material layer 302 is by the semi-conducting material shape for example comprising silicon and/or germanium
Into.Preferably, semiconductor material layer 302 is the silicon-on-insulator in 110 faces.
Step 202 is performed, the first opening for exposing buried insulator layer is formed in semiconductor material layer.
The mode of the opening of formation first has a variety of in semiconductor material layer 302.As an example, can be in semi-conducting material
Photoresist layer is formed on layer 302, there is the first patterns of openings wherein in photoresist layer.Then, using photoresist layer as mask, half-and-half
Conductor material layer 302 is performed etching to buried insulator layer 301 is exposed, to transfer a pattern in semiconductor material layer 302, half
The first opening is formed in conductor material layer 302.
With reference to subsequent process steps provided by the invention, a kind of mode for preferably forming the first opening is herein proposed, should
Method contributes to the second opening and fin in subsequent technique（It will hereafter will be described in）Making.The method for optimizing include with
Lower step：
First, referring to Fig. 3 B, the core-material 303 formed with patterning on semiconductor material layer 302, patterning
There is opening 304 in core-material 303.The core-material 303 of patterning can be nitride, in follow-up etching
Mask effect is played in semiconductor material layer 302.The width w of opening 3041Between defining indirectly between adjacent fin
Every, will hereinafter mention, the interval between fin also with the side wall to be formed in the core-material 303 of patterning between
Gap wall is relevant.In addition, it can be appreciated that the core-material 303 of patterning from the subsequent step being discussed in detail below
Width w2The spacing between adjacent fin is directly defined, so, according between fin in FinFET to be formed
Interval and fin width, can reasonably set opening 304 and patterning core-material 303 sizes.As
Example, the width w of the core-material of patterning1Can be 10nm to 100nm.The height h of the core-material 303 of patterning
Can be 20nm to 200nm.
Traditional photoetching process or the following figure occurred can be used by forming the method for the core-material 303 of patterning
Case chemical industry skill.As an example, for example form core-material on semiconductor material layer 302, the then shape on core-material
Into the photoresist layer of patterning, core-material is performed etching using photoresist layer as mask, to form the core material of patterning
The bed of material 303.
Then, as shown in Figure 3 C, clearance wall 305 is formed in the side wall of the core-material 303 of patterning.Clearance wall
305 material is different from the core-material 303 of patterning, so as to remove patterning follow-up core-material 303 when not
Clearance wall 305 can be had an impact.In the case where the core-material 303 of patterning is nitride, clearance wall 305 can be
Oxide.Specifically, the forming method of clearance wall 305 is included in the core-material 303 of semiconductor material layer 302 and patterning
Upper formation spacer material layer（It is not shown）, then remove on semiconductor material layer 302 and pattern using dry etching
Spacer material layer on core-material 303, only form gap in the side wall of the both sides of core-material 303 of patterning
Wall 305.As mentioned above, the width w of clearance wall 3053It is relevant with the spacing of fin, in addition, it is also straight with the width of fin
Correlation is connect, therefore the width w3 of clearance wall 305 is reasonably set according to fin size to be formed.As an example, clearance wall
305 width w3Can be 10nm-100nm.
Then, as shown in Figure 3 D, it is mask to semi-conducting material with the core-material 303 of patterning and clearance wall 305
Layer 302 carries out the first etching, to form the first opening 306.First etching technics can use dry etching or wet etching.
As an example, the etching gas of dry etching can include HBr, O2And Cl2, wherein HBr flow velocity can be 50-500sccm,
O2Flow velocity can be 2-20sccm, Cl2Flow velocity can be 5-50sccm.As an example, the etching solution of wet etching can be with
Including ammonium hydroxide（TMAH）Solution.Preferably, its mass concentration percentage can be 2%-20%.
It should be noted that the method for the above-mentioned opening of formation first 306 is only exemplary and preferable, therefore should not incite somebody to action
It is interpreted as limitation of the present invention.
Step 203 is performed, the first dielectric layer is formed in the side wall of the semiconductor material layer exposed in the first opening.As
Example, the first dielectric layer can be oxide skin(coating), and the first dielectric layer can be using oxidizing process, sedimentation or sputtering method etc. come shape
Into.
It is excellent with reference to Fig. 3 E in the semiconductor material layer 302 made with above-mentioned preferred embodiment with the first opening 306
Selection of land, it can be generated by insitu moisture（In-situ steam generation, ISSG）Annealing or rapid thermal treatment
（Rapid thermal processing, RTP）The side wall for the both sides of semiconductor material layer 302 exposed in the first opening 306
Upper formation dielectric layer 307.Insitu moisture generation annealing is a kind of low pressure Quick Oxidation thermal annealing technology, thin to deposition oxide
Oxidation growth is compensated while film thermal annealing.Device is heated rapidly to design temperature by rapid thermal treatment, carries out the short time
The method of rapid thermal treatment, heat treatment time are typically smaller than 1-2 minutes.
Step 204 is performed, the second opening for being different from the first opening is formed in semiconductor material layer, wherein the first opening
And second opening between semiconductor material layer be formed as fin.
With the opening of formation first similarly, the mode of the opening of formation second also has a variety of in semiconductor material layer 302.Make
For example, photoresist layer can be formed on semiconductor material layer 302, there is the second patterns of openings wherein in photoresist layer.So
Afterwards, using photoresist layer as mask, semiconductor material layer 302 is performed etching to buried insulator layer 301 is exposed, pattern is shifted
To semiconductor material layer 302, the second opening is formed in semiconductor material layer 302.
On the basis of the preferred embodiment that the making first being provided above is open, the invention provides make the second opening
Preferred embodiment.The preferred embodiment comprises the following steps：
As illustrated in Figure 3 F, the core-material 303 of patterning is removed.As an example, in the core-material 303 of patterning
In the case of for nitride, it can be removed it using wet method, for example with phosphoric acid solution.In the core-material of patterning
In the case that 303 is known other materials layers, it can be removed using known other manner.
As shown in Figure 3 G, it is that mask carries out the second etching to semiconductor material layer 302 with clearance wall 305, to form second
Opening 308.Meanwhile form fin 310 between the first opening 306 and the second opening 308.Second etching technics can be adopted
With dry etching or wet etching.Preferably, the second etching technics is performed using wet etching.Used etching agent is four
Ammonium hydroxide solution, semiconductor material layer 302, which is performed etching, using tetramethyl ammonium hydroxide solution can obtain edge
Straight opening.Preferably, the mass percent concentration of ammonium hydroxide solution is 2%-20%.
Step 205 is performed, the second dielectric layer is formed in the side wall of the semiconductor material layer exposed in the second opening, wherein
The thickness of second dielectric layer is different from the thickness of the first dielectric layer.
As an example, the photoresist layer for exposing the second opening can be only formed on semiconductor material layer, then using oxygen
The second dielectric layer is formed in the side wall for the semiconductor material layer that change method, sedimentation, sputtering method etc. expose in the second opening, and
Make the first dielectric layer and the second dielectric layer that there is different thickness.The thickness of first dielectric layer can be 10A-100A, and second is situated between
The thickness of electric layer can be 5A-50A.
Preferably, there is the second opening 308 in the semiconductor material layer 302 that reference is made with above-mentioned preferred embodiment
Fig. 3 H, can utilize on insitu moisture generation annealing or dielectric layer 307 the methods of rapid thermal treatment in the first opening 306 with
And second form dielectric layer 309 in the side wall of the both sides of semiconductor material layer 302 exposed in opening 308.
In the preferred embodiment, the dielectric layer 307 and 309 in the first opening 306 is the first dielectric layer, and second is open
Dielectric layer 309 in 308 is the second dielectric layer.Because the first dielectric layer is formed by oxidizing process twice, and the second dielectric
Layer is formed by once oxidation method, therefore both have different thickness.Have the first of dielectric layer 307 and 309 simultaneously
Dielectric layer may be used as the gate dielectric of one in the main grid pole and auxiliary grid that subsequently form, only with dielectric layer 309
The second dielectric layer may be used as another gate dielectric in the main grid pole and auxiliary grid that subsequently form.According to treating shape
Into the first dielectric layer and the thickness of the second dielectric layer the thickness of dielectric layer 307 and 309 can be reasonably set.
It should be noted that, although accompanying drawing illustrates the principle of the present invention, but this using the method for forming four fins 310
Invention not limited to this, the quantity of fin 310 can be less than four or more than four.
In order to complete the making of FinFET, the preferred method provided by the invention of above-mentioned offer can also include removing
The step of clearance wall 305, to obtain the device architecture shown in Fig. 3 I.Formed with fin 310 on buried insulator layer 301, often
The both sides of individual fin 310 are respectively formed with the different gate dielectric of thickness.Wherein, the first dielectric layer includes the He of dielectric layer 307
309, and the second dielectric layer only includes dielectric layer 309.
Further, method provided by the invention may additionally include the grid that fin 310 is formed across on fin 310.Due to
Therefore the step, it is known that be no longer described in detail herein.
Method provided by the invention can form the gate dielectric of different-thickness in fin both sides, to solve prior art
In be present in some devices S- slopes deterioration the problem of.In addition, this method is forming the gate dielectric of different-thickness
The making of fin can be completed simultaneously, therefore simplifies processing step.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of method for making asymmetric FinFET, including：
A) SOI substrate is provided, the SOI substrate includes Semiconductor substrate, the buried insulator layer in the Semiconductor substrate
And the semiconductor material layer in the buried insulator layer；
B) the first opening for exposing the buried insulator layer is formed in the semiconductor material layer；
C) the first dielectric layer is formed in the side wall of the semiconductor material layer exposed in the described first opening；
D) in the semiconductor material layer formed be different from first opening second opening, wherein it is described first opening and it is described
Semiconductor material layer between second opening is formed as fin；And
E) the semiconductor material exposed on first dielectric layer in the described first opening and in second opening
The second dielectric layer is formed in the side wall of the bed of material, is thus formed in two side walls of fin and is situated between by the first dielectric layer, second respectively
The gate dielectric that electric layer collectively forms, and the gate dielectric being made up of the second dielectric layer.
2. the method as described in claim 1, it is characterised in that the method bag of first opening is formed in the b) step
Include：
The core-material formed with patterning on the semiconductor material layer；
Clearance wall is formed in the side wall of the core-material of the patterning；
First etching is carried out to the semiconductor material layer as mask using the core-material of the patterning and the clearance wall,
To form first opening.
3. method as claimed in claim 2, it is characterised in that the width of the core-material of the patterning arrives for 10nm
100nm, and/or the thickness of the core-material of the patterning is 20nm to 200nm.
4. method as claimed in claim 2, it is characterised in that the core-material of the patterning is nitride.
5. method as claimed in claim 2, it is characterised in that the method bag of second opening is formed in the d) step
Include：
Remove the core-material of the patterning；
The second etching is carried out to the semiconductor material layer by mask of the clearance wall, to form second opening.
6. method as claimed in claim 5, it is characterised in that second etching is to be entered using tetramethyl ammonium hydroxide solution
Capable wet etching.
7. method as claimed in claim 6, it is characterised in that the mass percent concentration of the ammonium hydroxide solution is
2%-20%.
8. the method as described in claim 1, it is characterised in that contain silicon, first dielectric in the semiconductor material layer
What layer and second dielectric layer were formed using at least one of insitu moisture generation annealing and rapid thermal treatment.
9. the method as described in claim 1, it is characterised in that the thickness of first dielectric layer is 10A-100A, and/or institute
The thickness for stating the second dielectric layer is 5A-50A.
10. the method as described in claim 1, it is characterised in that the semiconductor material layer is the silicon-on-insulator in 110 faces.
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