CN107665823A - A kind of semiconductor devices and preparation method, electronic installation - Google Patents
A kind of semiconductor devices and preparation method, electronic installation Download PDFInfo
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- CN107665823A CN107665823A CN201610607601.8A CN201610607601A CN107665823A CN 107665823 A CN107665823 A CN 107665823A CN 201610607601 A CN201610607601 A CN 201610607601A CN 107665823 A CN107665823 A CN 107665823A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 238000009434 installation Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 94
- 239000000463 material Substances 0.000 claims abstract description 81
- 239000012298 atmosphere Substances 0.000 claims abstract description 61
- 238000004380 ashing Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 125000006850 spacer group Chemical group 0.000 claims abstract description 32
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 229920000642 polymer Polymers 0.000 abstract description 19
- 238000004140 cleaning Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 238000005530 etching Methods 0.000 description 18
- 150000004767 nitrides Chemical class 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000003467 diminishing effect Effects 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method, electronic installation.Methods described includes：Semiconductor substrate is provided, on the semiconductor substrate the spacer material layer formed with grid structure and the covering grid structure；The spacer material layer is etched, to form clearance wall in the side wall of the grid structure；Including H2Atmosphere in the clearance wall is ashed；Perform wet clean step.Methods described first carries out high temperature ashing to the clearance wall after the etch, then wet-cleaning is carried out, the problem of to remove the polymer residue, while the loss in current technique to material in the source-drain area is also avoid, further increase the performance and yield of the semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and system
Preparation Method, electronic installation.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is not mainly by
The disconnected size for reducing IC-components is to improve its speed to realize.At present, due to height
The demand of device density, high-performance and low cost, semi-conductor industry have advanced to nanometer technology
Process node, the preparation of semiconductor devices are limited by various physics limits.
With the continuous diminution of dimensions of semiconductor devices, the width of grid structure constantly reduces, grid
Channel length under structure also constantly reduces, in order to effectively prevent short-channel effect, generally
Clearance wall is formed in the side wall of the grid structure, is grown with improving the raceway groove of the transistor formed
Degree, reduce short-channel effect and the hot carrier's effect caused by short-channel effect.
Generally O is selected in the preparation process of the clearance wall2Plasma treatment, between reduction
The influence of the polymer formed in gap wall preparation process, but O2Plasma treatment would generally be led
Cause yield to reduce, such as loss in source and drain, reduction of dopant dose etc. can be caused.
Therefore, how to solve the influence of the polymer, while the yield for improving device turns into mesh
Before need to solve the problems, such as.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In order to overcome the problem of presently, there are, the invention provides a kind of preparation of semiconductor devices
Method, methods described include：
Semiconductor substrate is provided, on the semiconductor substrate formed with grid structure and covering institute
State the spacer material layer of grid structure；
The spacer material layer is etched, to form gap in the side wall of the grid structure
Wall；
Including H2Atmosphere in the clearance wall is ashed；
Perform wet clean step.
Alternatively, the spacer material layer is etched from pulsed etch method, with described in formation
Clearance wall.
Alternatively, the dutycycle of power output is 10%-80% in the pulsed etch method,
Frequency is 1KHz-10KHz.
Alternatively, in H2And N2The clearance wall is ashed in atmosphere.
Alternatively, wherein the H2In H2And N2Volume ratio in atmosphere is 5%-40%.
Alternatively, the temperature of the ashing is more than 250 DEG C.
Alternatively, repeatedly alternately in H2In atmosphere and in N2And NF3To institute in atmosphere
Clearance wall is stated to be ashed；
Or repeatedly alternately in H2In atmosphere and in NH3And NF3To between described in atmosphere
Gap wall is ashed.
Alternatively, the temperature of the ashing is 300-400 DEG C.
Present invention also offers a kind of semiconductor devices, the semiconductor devices passes through claim
The above method is prepared.
The invention discloses a kind of electronic installation, the electronic installation includes above-mentioned semiconductor device
Part.
In order to solve above mentioned problem present in current technique, the invention provides a kind of semiconductor
The preparation method of device, methods described is after the clearance wall is etched in order to eliminate in clearance wall
The influence of caused polymer, is improved methods described in etching process, in the erosion
The clearance wall is first carried out after quarter high temperature ashing, wet-cleaning is then carried out, to remove
The problem of stating polymer residue, while also avoid in current technique to material in the source-drain area
Loss, further increase the performance and yield of the semiconductor devices.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
In order to solve above mentioned problem present in current technique, the invention provides a kind of semiconductor
The preparation method of device, methods described include：
Semiconductor substrate is provided, on the semiconductor substrate formed with grid structure and covering institute
State the spacer material layer of grid structure；
The spacer material layer is etched, to form gap in the side wall of the grid structure
Wall；
The clearance wall is ashed；
Perform wet clean step.
Specifically, methods described can include：
Semiconductor substrate is provided, on the semiconductor substrate formed with grid structure and covering institute
State the spacer material layer of grid structure；
The spacer material layer is etched from pulsed etch method, with the grid structure
Clearance wall is formed in side wall；
In H2And N2The clearance wall is carried out in atmosphere high temperature ashing；
Perform wet clean step.
In this step in order to reduce in the etched gap wall material bed of material formation of polymer and residual
Stay, the spacer material layer is etched from pulsed etch method.
Specifically, the dutycycle of power output is 10%-80% in the pulsed etch, frequency
For 1KHz-10KHz.
It is high temperature ashing to clearance wall progress after the clearance wall is formed, so that described poly-
Compound is ashed, wherein the temperature of the ashing is more than 250 DEG C.
For example, the temperature of the ashing is 300-400 DEG C.
Wherein, in this application in order to avoid it is described it is high temperature ashing in shadow is caused to other materials
Ring, in H2And N2The clearance wall is ashed in atmosphere.
Alternatively, wherein H2In H2And N2Volume ratio in atmosphere is 5%-40%, certainly
It is not limited to the scope.
As a kind of alternative embodiment, methods described can include：
Semiconductor substrate is provided, on the semiconductor substrate formed with grid structure and covering institute
State the spacer material layer of grid structure；
The spacer material layer is etched, to form gap in the side wall of the grid structure
Wall；
In H2Atmosphere and N2And NF3Alternate cycles to the gap in the atmosphere of combination
Wall carries out high temperature ashing；Or in H2Atmosphere and NH3And NF3Handed in the atmosphere of combination
The clearance wall is carried out for circulation high temperature ashing；
Perform wet clean step.
In this step in order to reduce in the etched gap wall material bed of material formation of polymer and residual
Stay, the spacer material layer is etched from pulsed etch method.
Specifically, the dutycycle of power output is 10%-80% in the pulsed etch, frequency
For 1KHz-10KHz.
In addition, conventional engraving method can also be selected in this embodiment, such as dry etching
Or wet etching is to form the clearance wall.
Then repeatedly alternately in H2Atmosphere and N2And NF3To between described in the atmosphere of combination
Gap wall is ashed；
Such as in H2Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination
--- in H2Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination --- in H2
Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination, is circulated described in performing
Cineration step at least more than 5 times.
Or repeatedly alternately in H2Atmosphere and NH3And NF3To described in the atmosphere of combination
Clearance wall is ashed.
Such as in H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination
--- in H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination ---
H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination, circulation perform
The cineration step at least more than 5 times.
Wherein, the NH3And NF3Combination and N2And NF3The atmosphere of combination will not be half-and-half
Either other materials has any impact or lost oxide in conductor device, so as to avoid
The loss of caused other materials in current technique.
Alternatively, the temperature of the ashing is 300-400 DEG C.
The high temperature ashing loss that can not only prevent other materials layer in the process, also
It can further be hardened in the high temperature ashing technique, improve the hardness of the material layer.
In order to solve above mentioned problem present in current technique, the invention provides a kind of semiconductor
The preparation method of device, methods described is after the clearance wall is etched in order to eliminate in clearance wall
The influence of caused polymer, is improved methods described in etching process, in the erosion
The clearance wall is first carried out after quarter high temperature ashing, wet-cleaning is then carried out, to remove
The problem of stating polymer residue, while also avoid in current technique to material in the source-drain area
Loss, further increase the performance and yield of the semiconductor devices.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, schemed
1 shows the preparation technology flow chart of semiconductor devices of the present invention.
The present invention provides a kind of preparation method of semiconductor devices, as shown in figure 1, the preparation side
The key step of method includes：
Step S1：Semiconductor substrate is provided, on the semiconductor substrate formed with grid knot
Structure and the spacer material layer for covering the grid structure；
Step S2：The spacer material layer is etched, with the side wall of the grid structure
Form clearance wall；
Step S3：Including H2Atmosphere in the clearance wall is ashed；
Step S4：Perform wet clean step.
Below, the embodiment of the preparation method of the semiconductor devices of the present invention is done in detail
Explanation.
First, step 1 is performed, there is provided Semiconductor substrate, formed on the semiconductor substrate
There is grid structure and cover the spacer material layer of the grid structure.
Specifically, the Semiconductor substrate can be in the following material being previously mentioned in this step
At least one：Silicon, silicon-on-insulator (SOI), silicon (SSOI), absolutely is laminated on insulator
On edge body be laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and absolutely
Germanium (GeOI) etc. on edge body.
Semiconductor substrate selects silicon in this embodiment.
In addition, active area can be defined in Semiconductor substrate.It can also wrap on the active region
Containing other active devices, for convenience, do not indicated in shown figure.
Then fleet plough groove isolation structure, the shallow trench isolation are formed in the Semiconductor substrate
The forming method of structure can select method commonly used in the prior art, such as first, partly lead
The first oxide skin(coating) and the first nitride layer are sequentially formed on body substrate.Then, dry method is performed to carve
Etching technique, the first nitride layer, the first oxide skin(coating) and Semiconductor substrate are performed etching successively
To form groove.Specifically, the figuratum photoresist of tool can be formed on the first nitride layer
Layer, dry etching is carried out to the first nitride layer using the photoresist layer as mask, pattern is turned
The first nitride layer is moved to, and is aoxidized using photoresist layer and the first nitride layer as mask to first
Nitride layer and Semiconductor substrate perform etching, to form groove.Certainly other methods can also be used
To form groove, because the technique is thought known in the art, therefore no longer it is described further.
Then, shallow trench isolated material is filled in groove, to form fleet plough groove isolation structure.
Specifically, shallow trench isolated material can be formed on the first nitride layer and in groove, it is described
Shallow trench isolated material can be that silica, silicon oxynitride and/or other existing low dielectrics are normal
Number material；Perform chemical mechanical milling tech and stop on the first nitride layer, to be formed
State fleet plough groove isolation structure.
The Semiconductor substrate can be divided into different by the shallow trench isolation in the present invention
Functional area.
Then, grid structure on the semiconductor substrate.
Specifically, oxide insulating layer, grid material are sequentially depositing on the semiconductor substrate
Then the oxide insulating layer, gate material layers are performed etching to obtain grid structure by layer.
Wherein, the oxide insulating layer is preferably silica, and its forming method can be heavy
Semiconductor substrate described in silicon dioxide material layer or high-temperature oxydation is accumulated to form insulating barrier, it is described
Gate material layers may include silicon or polysilicon layer.
Preferably, the both sides that methods described may further include the grid structure are formed partially
Move side wall (offset spacer).The material of the offset side wall is, for example, silicon nitride, silica or
The insulating materials such as person's silicon oxynitride.With further diminishing for device size, the raceway groove of device is grown
Spend less and less, the particle of source-drain electrode injection depth is also less and less, and offset side wall acts on
In to improve the channel length of the transistor formed, reduce short-channel effect and because short channel is imitated
Should caused hot carrier's effect.The technique of offset side wall is formed in grid structure both sides to be
Chemical vapor deposition, in the present embodiment, the thickness of the offset side wall may diminish to 80 angstroms.
Alternatively, LDD ion implantings step is performed in the both sides of the grid structure and is activated.
Spacer material layer is formed in the both sides of the grid structure, the spacer material layer can
Think that a kind of in silica, silicon nitride, silicon oxynitride or they combine and formed.
As embodiment in the one of the present embodiment, the clearance wall is that silica, silicon nitride are common
With composition, concrete technology is：Silicon oxide layer and silicon nitride layer are formed on a semiconductor substrate.
Step 2 is performed, the spacer material layer is etched from pulsed etch method, with institute
State and clearance wall is formed in the side wall of grid structure.
In this step in order to reduce in the etched gap wall material bed of material formation of polymer and residual
Stay, the spacer material layer is etched from pulsed etch method.
Specifically, the dutycycle of power output is 10%-80% in the pulsed etch, frequency
For 1KHz-10KHz.
After clearance wall is formed, methods described can further include in the grid structure
The step of source and drain is formed in the source and drain of both sides, such as partly led in the described of the grid structure both sides
Groove is formed in body substrate, alternatively, the groove is " ∑ " connected in star, in this step
Source-drain area described in dry etching can be selected, CF can be selected in the dry etching4、
CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas stream
Measure as CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm,
The etching pressure is 30-150mTorr, etching period 5-120s.
Then, the epitaxial growth semiconductor material layer in the groove, to form source-drain area.
Further, the semiconductor material layer selects SiGe or SiC layer in the present invention,
Can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, point
One kind of the outer Yanzhong of beamlet forms the semiconductor material layer.
Step 3 is performed, in H2And N2The clearance wall is carried out in atmosphere high temperature ashing.
It is high temperature ashing to clearance wall progress after the clearance wall is formed, so that described poly-
Compound is ashed, wherein the temperature of the ashing is more than 250 DEG C.
For example, the temperature of the ashing is 300-400 DEG C.
Wherein, in this application in order to avoid it is described it is high temperature ashing in shadow is caused to other materials
Ring, in H2And N2The clearance wall is ashed in atmosphere.
Alternatively, wherein H2In H2And N2Volume ratio in atmosphere is 5%-40%, certainly
It is not limited to the scope.
The high temperature ashing loss that can not only prevent other materials layer in the process, also
It can further be hardened in the high temperature ashing technique, improve the hardness of the material layer.
Step 4 is performed, performs wet clean step.
Wherein, polymerization of the wet clean step for removal by high temperature ashing residual afterwards
Thing.
The wet clean step can select conventional technique, it is not limited to a certain.
So far, Jie of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed
Continue.After the above step, other correlation steps can also be included, here is omitted.And
And in addition to the foregoing steps, the preparation method of the present embodiment can also be in above-mentioned each step
Among or different steps between include other steps, these steps can pass through prior art
In various techniques realize that here is omitted.
In order to solve above mentioned problem present in current technique, the invention provides a kind of semiconductor
The preparation method of device, methods described is after the clearance wall is etched in order to eliminate in clearance wall
The influence of caused polymer, is improved methods described in etching process, in the erosion
The clearance wall is first carried out after quarter high temperature ashing, wet-cleaning is then carried out, to remove
The problem of stating polymer residue, while also avoid in current technique to material in the source-drain area
Loss, further increase the performance and yield of the semiconductor devices.
Embodiment two
Another method for preparing the semiconductor devices, including following step is provided below
Suddenly：
First, step 1 is performed, there is provided Semiconductor substrate, formed on the semiconductor substrate
There is grid structure and cover the spacer material layer of the grid structure.
Specifically, the Semiconductor substrate can be in the following material being previously mentioned in this step
At least one：Silicon, silicon-on-insulator (SOI), silicon (SSOI), absolutely is laminated on insulator
On edge body be laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and absolutely
Germanium (GeOI) etc. on edge body.
Semiconductor substrate selects silicon in this embodiment.
In addition, active area can be defined in Semiconductor substrate.It can also wrap on the active region
Containing other active devices, for convenience, do not indicated in shown figure.
Then fleet plough groove isolation structure, the shallow trench isolation are formed in the Semiconductor substrate
The forming method of structure can select method commonly used in the prior art, such as first, partly lead
The first oxide skin(coating) and the first nitride layer are sequentially formed on body substrate.Then, dry method is performed to carve
Etching technique, the first nitride layer, the first oxide skin(coating) and Semiconductor substrate are performed etching successively
To form groove.Specifically, the figuratum photoresist of tool can be formed on the first nitride layer
Layer, dry etching is carried out to the first nitride layer using the photoresist layer as mask, pattern is turned
The first nitride layer is moved to, and is aoxidized using photoresist layer and the first nitride layer as mask to first
Nitride layer and Semiconductor substrate perform etching, to form groove.Certainly other methods can also be used
To form groove, because the technique is thought known in the art, therefore no longer it is described further.
Then, shallow trench isolated material is filled in groove, to form fleet plough groove isolation structure.
Specifically, shallow trench isolated material can be formed on the first nitride layer and in groove, it is described
Shallow trench isolated material can be that silica, silicon oxynitride and/or other existing low dielectrics are normal
Number material；Perform chemical mechanical milling tech and stop on the first nitride layer, to be formed
State fleet plough groove isolation structure.
The Semiconductor substrate can be divided into not same district by the shallow trench isolation in the present invention
Domain, such as NMOS area and PMOS area.
Then, grid structure on the semiconductor substrate.
Specifically, oxide insulating layer, grid material are sequentially depositing on the semiconductor substrate
Then the oxide insulating layer, gate material layers are performed etching to obtain grid structure by layer.
Wherein, the oxide insulating layer is preferably silica, and its forming method can be heavy
Semiconductor substrate described in silicon dioxide material layer or high-temperature oxydation is accumulated to form insulating barrier, it is described
Gate material layers may include silicon or polysilicon layer.
Preferably, the both sides that methods described may further include the grid structure are formed partially
Move side wall (offset spacer).The material of the offset side wall is, for example, silicon nitride, silica or
The insulating materials such as person's silicon oxynitride.With further diminishing for device size, the raceway groove of device is grown
Spend less and less, the particle of source-drain electrode injection depth is also less and less, and offset side wall acts on
In to improve the channel length of the transistor formed, reduce short-channel effect and because short channel is imitated
Should caused hot carrier's effect.The technique of offset side wall is formed in grid structure both sides to be
Chemical vapor deposition, in the present embodiment, the thickness of the offset side wall may diminish to 80 angstroms.
Alternatively, LDD ion implantings step is performed in the both sides of the grid structure and is activated.
Spacer material layer is formed in the both sides of the grid structure, the spacer material layer can
Think that a kind of in silica, silicon nitride, silicon oxynitride or they combine and formed.
As embodiment in the one of the present embodiment, the clearance wall is that silica, silicon nitride are common
With composition, concrete technology is：Silicon oxide layer and silicon nitride layer are formed on a semiconductor substrate.
Step 2 is performed, the spacer material layer is etched, with the side wall of the grid structure
Upper formation clearance wall.
In this step in order to reduce in the etched gap wall material bed of material formation of polymer and residual
Stay, the spacer material layer is etched from pulsed etch method.
Specifically, the dutycycle of power output is 10%-80% in the pulsed etch, frequency
For 1KHz-10KHz.
In addition, conventional engraving method can also be selected in this embodiment, such as dry etching
Or wet etching is to form the clearance wall.
After clearance wall is formed, methods described can further include in the grid structure
The step of source and drain is formed in the source and drain of both sides, such as partly led in the described of the grid structure both sides
Groove is formed in body substrate, alternatively, the groove is " ∑ " connected in star, in this step
Source-drain area described in dry etching can be selected, in the dry etching can select CF4,
CHF3, in addition plus N2、CO2、O2In it is a kind of as etching atmosphere, wherein gas stream
Measure as CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm,
The etching pressure is 30-150mTorr, etching period 5-120s.
Then, the epitaxial growth semiconductor material layer in the groove, to form source-drain area.
Further, the semiconductor material layer selects SiGe or SiC layer in the present invention,
Can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, point
One kind of the outer Yanzhong of beamlet forms the semiconductor material layer.
Step 3 is performed, the clearance wall is carried out high temperature ashing.
Specifically, repeatedly alternately in H2Atmosphere and N2And NF3To institute in the atmosphere of combination
Clearance wall is stated to be ashed；
Such as in H2Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination
--- in H2Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination --- in H2
Atmosphere is high temperature ashing --- in N2And NF3The atmosphere high temperature ashing of combination, is circulated described in performing
Cineration step at least more than 5 times.
Or repeatedly alternately in H2Atmosphere and NH3And NF3To described in the atmosphere of combination
Clearance wall is ashed.
Such as in H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination
--- in H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination ---
H2Atmosphere is high temperature ashing --- in NH3And NF3The atmosphere high temperature ashing of combination, circulation perform
The cineration step at least more than 5 times.
Wherein, the NH3And NF3Combination and N2And NF3The atmosphere of combination will not be half-and-half
Either other materials has any impact or lost oxide in conductor device, so as to avoid
The loss of caused other materials in current technique.
Alternatively, the temperature of the ashing is 300-400 DEG C.
The high temperature ashing loss that can not only prevent other materials layer in the process, also
It can further be hardened in the high temperature ashing technique, improve the hardness of the material layer.
Step 4 is performed, performs wet clean step.
Wherein, polymerization of the wet clean step for removal by high temperature ashing residual afterwards
Thing.
The wet clean step can select conventional technique, it is not limited to a certain.
So far, Jie of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed
Continue.After the above step, other correlation steps can also be included, here is omitted.And
And in addition to the foregoing steps, the preparation method of the present embodiment can also be in above-mentioned each step
Among or different steps between include other steps, these steps can pass through prior art
In various techniques realize that here is omitted.
In order to solve above mentioned problem present in current technique, the invention provides a kind of semiconductor
The preparation method of device, methods described is after the clearance wall is etched in order to eliminate in clearance wall
The influence of caused polymer, is improved methods described in etching process, in the erosion
The clearance wall is first carried out after quarter high temperature ashing, wet-cleaning is then carried out, to remove
The problem of stating polymer residue, while also avoid in current technique to material in the source-drain area
Loss, further increase the performance and yield of the semiconductor devices.
Embodiment three
Present invention also offers a kind of semiconductor devices, the semiconductor devices passes through embodiment
One or the methods described of embodiment two be prepared, methods described is after the clearance wall is etched
The influence of the caused polymer during spacer etch is eliminated, methods described carried out
Improve, the clearance wall is first carried out after the etch high temperature ashing, then carry out wet method
Cleaning, the problem of to remove the polymer residue, while it also avoid in current technique to institute
The loss of material in source-drain area is stated, further increases the performance of the semiconductor devices and good
Rate.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.
Example IV
An alternative embodiment of the invention provides a kind of electronic installation, and it includes semiconductor devices,
The semiconductor devices is the semiconductor devices in previous embodiment three, or according to embodiment one or real
Apply the semiconductor devices obtained by the preparation method of the semiconductor devices described in example two.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, camera, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment or there is above-mentioned semiconductor
The intermediate products of device, such as：Cell phone mainboard with the integrated circuit etc..
Due to including semiconductor devices part there is higher performance, the electronic installation equally has
Above-mentioned advantage.
Wherein, Fig. 2 shows the example of mobile phone handsets.Mobile phone handsets 200 are set
It is equipped with the display portion 202 being included in shell 201, operation button 203, external connection terminal
Mouth 204, loudspeaker 205, microphone 206 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or according to embodiment one
Semiconductor devices obtained by the preparation method of described semiconductor devices, the semiconductor devices
Draw in preparation process after the clearance wall is etched in order to eliminate during spacer etch
The influence of the polymer risen, is improved methods described, after the etch to described
Clearance wall first carries out high temperature ashing, wet-cleaning is then carried out, to remove the polymer residue
The problem of, while the loss in current technique to material in the source-drain area is also avoid, enter one
Step improves the performance and yield of the semiconductor devices.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with grid structure and covering institute
State the spacer material layer of grid structure；
The spacer material layer is etched, to form gap in the side wall of the grid structure
Wall；
Including H2Atmosphere in the clearance wall is ashed；
Perform wet clean step.
2. according to the method for claim 1, it is characterised in that from pulsed etch side
Method etches the spacer material layer, to form the clearance wall.
3. according to the method for claim 2, it is characterised in that the pulsed etch side
The dutycycle of power output is 10%-80%, frequency 1KHz-10KHz in method.
4. according to the method for claim 2, it is characterised in that in H2And N2Atmosphere
In the clearance wall is ashed.
5. according to the method for claim 4, it is characterised in that wherein described H2
H2And N2Volume ratio in atmosphere is 5%-40%.
6. according to the method described in any one of foregoing claim, it is characterised in that the ash
The temperature of change is more than 250 DEG C.
7. according to the method for claim 1, it is characterised in that repeatedly alternately in H2
In atmosphere and in N2And NF3The clearance wall is ashed in atmosphere；
Or repeatedly alternately in H2In atmosphere and in NH3And NF3To between described in atmosphere
Gap wall is ashed.
8. according to the method for claim 7, it is characterised in that the temperature of the ashing
For 300-400 DEG C.
9. a kind of semiconductor devices, it is characterised in that the semiconductor devices will by right
One of 1 to 8 methods described is asked to be prepared.
10. a kind of electronic installation, it is characterised in that the electronic installation includes claim 9
Described semiconductor devices.
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| CN117339063A (en) * | 2023-12-06 | 2024-01-05 | 杭州迪视医疗生物科技有限公司 | Micro needle tube and manufacturing method of micro injection needle |
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| CN105575900A (en) * | 2014-10-13 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device with semiconductor device |
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| CN103972094A (en) * | 2013-01-30 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
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