CN104752181A - Pseudo gate removing method - Google Patents
Pseudo gate removing method Download PDFInfo
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- CN104752181A CN104752181A CN201310745827.0A CN201310745827A CN104752181A CN 104752181 A CN104752181 A CN 104752181A CN 201310745827 A CN201310745827 A CN 201310745827A CN 104752181 A CN104752181 A CN 104752181A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 93
- 238000001020 plasma etching Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 105
- 239000000758 substrate Substances 0.000 claims description 29
- 239000007789 gas Substances 0.000 claims description 17
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001307 helium Substances 0.000 claims description 8
- 229910052734 helium Inorganic materials 0.000 claims description 8
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 8
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 8
- 229910052735 hafnium Inorganic materials 0.000 claims description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 4
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 4
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 abstract description 12
- 239000007787 solid Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000036962 time dependent Effects 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Abstract
The invention provides a pseudo gate removing method. In a pseudo gate removing step, pulse plasma etching is adopted to conduct first etching on a pseudo gate, and then second etching is conducted on the residual pseudo gate. When the pulse plasma etching is adopted to conduct the first etching on the pseudo gate, an etching machine outputs source power in a pulse mode to etch the pseudo gate in an intermittent mode, source power output time and vacant time are both short, a polymer and solid produced in etching are discharged out of an opening formed through etching within the interval time of source power vacancy, the pulse plasma etching rates adopted for pseudo gates different in size are equal under the condition that no polymer blockage exists, a gate electrode dielectric layer with large-sized pseudo gates can be kept in a good shape when first etching is completed, and further the performance of the gate electrode dielectric layer can be improved.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of method removing pseudo-grid.
Background technology
In the high K dielectric/rear metal gate engineering of transistor, complete high annealing carry out ion-activated after, need pseudo-grid (as polysilicon gate) removal, recharge metal gates subsequently, to form high K dielectric/rear metal-gate structures.
With reference to figure 1 and Fig. 2, show a kind of method removing pseudo-grid of prior art.As shown in Figure 1, first pseudo-grid structure 20A, the second pseudo-grid structure 20B in substrate 01, described first pseudo-grid structure 20A comprises the first side wall 13A of first grid dielectric layer 11A bottom the first pseudo-grid 12A, the first pseudo-grid 12A, the first pseudo-grid 12A sidewall; Described second pseudo-grid structure 20B comprises the second side wall 13B of second grid dielectric layer 11B bottom the second pseudo-grid 12B, the second pseudo-grid 12B, the second pseudo-grid 12B sidewall.Wherein, the width of the first pseudo-grid 12A is less than the width of the second pseudo-grid 12B, and namely the first pseudo-grid structure 20A is different from the size of the second pseudo-grid structure 20B.The substrate 10 that first pseudo-grid structure 20A, the second pseudo-grid structure 20B expose also is formed with interlayer dielectric layer 14.
With reference to figure 2, according to existing rear grid technique, need to remove described first pseudo-grid 12A, the second pseudo-grid 12B, to form metal gates in the opening formed at removal first pseudo-grid 12A, the second pseudo-grid 12B.First pseudo-grid 12A, the second pseudo-grid 12B adopt polysilicon to be formed usually, and prior art general using plasma etching removal first pseudo-grid 12A, the second pseudo-grid 12B, to the pseudo-grid of different size, the speed of etching is different.In general, larger-size pseudo-grid etch rate is very fast, and the less pseudo-grid etch rate of size is slower.Therefore, as shown in Figure 2, when the first pseudo-grid 12A that size is less is etched clean, the pseudo-grid of larger-size second pseudo-grid 12B are removed already and expose second grid dielectric layer 11B prematurely, described second grid dielectric layer 11B is subject to the effect of plasma etching and damages, after filling metal gates in the opening, the insulating properties between metal gates and substrate 10 is poor.When transistor is NMOS, gate dielectric layer impaired will be serious the time breakdown characteristic (Time Dependent Dielectric Breakdown, TDDB) affecting NMOS.Therefore, a kind of urgently method removing pseudo-grid, after the pseudo-grid removing different size, the gate dielectric layer below pseudo-grid keeps good pattern.
Summary of the invention
The present invention solve problem be to provide a kind of method removing pseudo-grid, with reduce remove pseudo-grid process to the damage of gate dielectric layer.
For solving the problem, the invention provides a kind of method removing pseudo-grid, comprising:
Substrate is provided;
Form pseudo-grid structure at described substrate surface, described pseudo-grid structure comprises and is positioned at gate dielectric layer on described substrate successively and pseudo-grid;
Pulsed plasma etching is adopted to carry out the first etching to described pseudo-grid;
Second etching is carried out to the pseudo-grid of remnants.
Optionally, in the step forming pseudo-grid structure, the material of described pseudo-grid is polysilicon, silicon nitride or amorphous carbon.
Optionally, the step forming pseudo-grid structure comprises: on substrate, form hafnium layer and titanium nitride cap cap layers successively, to form described gate dielectric layer.
Optionally, in the step forming pseudo-grid structure, described method also comprises: on the substrate that pseudo-grid structure is exposed, form the interlayer dielectric layer flushed with pseudo-grid structure.
Optionally, the material of described interlayer dielectric layer is silica.
Optionally, in employing pulsed plasma etching, the step that described pseudo-grid carry out the first etching is comprised: etching machine adopts pulse mode output source power.
Optionally, pulsed plasma etching is adopted to comprise the step that described pseudo-grid carry out the first etching: the etching gas of the first etching comprises hydrogen bromide, oxygen and helium.
Optionally, pulsed plasma etching is adopted to comprise the step that described pseudo-grid carry out the first etching: to carry out the first etching to described pseudo-grid, until expose gate dielectric layer surface.
Optionally, the step of carrying out the second etching comprises: adopt continuumpiston etching to etch the pseudo-grid of remnants, etching gas comprises hydrogen bromide, oxygen and helium.
Optionally, after described second etching, also comprise: carry out dry method cleaning to gate dielectric layer surface, the gas for dry method cleaning comprises nitrogen.
Optionally, for the gas of dry method cleaning also comprise in carbon tetrafluoride, Nitrogen trifluoride and sulphur hexafluoride one or more.
Optionally, in the step forming pseudo-grid structure, described pseudo-grid are the pseudo-grid of NMOS, and the pseudo-grid surface of described NMOS is also formed with oxide layer.
Optionally, before carrying out the first etching, also comprise: the oxide layer removing the pseudo-grid surface of described NMOS.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the step removing pseudo-grid, by adopting pulsed plasma etching, the first etching is carried out to described pseudo-grid, then the second etching is carried out to the pseudo-grid of remnants, carry out in the process of the first etching in employing pulsed plasma etching to described pseudo-grid, etching machine adopts pulse mode output source power, thus time of exporting of source power and vacant time-interleavedly to carry out, in the off time that source power is vacant, the polymer etching generation in the time that source power can be exported is discharged in time, and reduce the problem that the open surfaces formed in etching forms polymer, like this under the condition of non-polymer stop, there is not the problem that polymer blocks etching in the open surfaces that the pseudo-grid removing different size are formed, so the etch rate of plasma etching to the different pseudo-grid of size is consistent, gate dielectric layer under larger-size pseudo-grid can not expose too early thus can ensure good pattern, and then improve the performance of gate dielectric layer.
Further, described gate dielectric layer comprises hafnium layer from bottom to top and titanium nitride cap cap layers, after described second etching, dry method cleaning is carried out with the oxide removing gate dielectric layer surface to gate dielectric layer surface, gas for dry method cleaning comprises nitrogen, because the plasma of nitrogen ionization can deposit and replenish in the gap of titanium nitride cap cap layers, thus, the gas comprising the dry method cleaning of nitrogen can also play the effect of repairing titanium nitride cap cap layers while removing gate dielectric layer oxide on surface, improve the performance of gate dielectric layer.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is a kind of schematic diagram removing the method for pseudo-grid of prior art;
Fig. 3 is the flow chart that the present invention removes method one embodiment of pseudo-grid;
Fig. 4 to Fig. 7 be embodiment illustrated in fig. 3 in the end view of each step.
Embodiment
In the method for the pseudo-grid of existing removal, the mode of usual employing dry etching removes pseudo-grid, but different to the removal speed of the pseudo-grid of different size when dry etching removes pseudo-grid, particularly, speed is removed to larger-size pseudo-grid very fast, and slower to the pseudo-grid removal speed that size is less.When pseudo-grid less for size are removed clean, gate dielectric layer below larger-size pseudo-grid easily sustains damage because exposing too early, fill metal gates in the opening removing the formation of pseudo-grid after, insulating properties between metal gates and substrate is poor, when transistor is NMOS, the impaired time breakdown characteristic (Time Dependent Dielectric Breakdown, TDDB) that seriously will affect NMOS of gate dielectric layer.
Analyze the process removing pseudo-grid, for larger-size pseudo-grid, the opening formed on pseudo-grid surface when etching starts is larger, polymer ratio is easier to get rid of from described opening, thus have open surfaces and less block, and then it is also faster to the etching speed of the pseudo-grid that opening exposes, and for the less pseudo-grid of size, the opening formed on pseudo-grid surface when etching starts is less, polymer is not easy to get rid of from described opening, thus have open surfaces and more block, so also slower to the etching speed of the pseudo-grid that opening exposes.
In order to solve the problems of the technologies described above, the invention provides a kind of Transistor forming method, in the step removing pseudo-grid, by adopting pulsed plasma etching, the first etching is carried out to described pseudo-grid, then the second etching is carried out to the pseudo-grid of remnants, remove pseudo-grid by the method for step etching, improve the problem that pseudo-grid lower gate dielectric layer damages by etching affects.
With reference to figure 3, show the flow chart that the present invention removes method one embodiment of pseudo-grid, the method that the present embodiment removes pseudo-grid roughly comprises the following steps:
Step S1, provides substrate;
Step S2, forms pseudo-grid structure at described substrate surface, and described pseudo-grid structure comprises the gate dielectric layer, the pseudo-grid that are positioned on described substrate successively;
Step S3, adopts pulsed plasma etching to carry out the first etching to described pseudo-grid;
Step S4, carries out the second etching to the pseudo-grid of remnants.
In the step removing pseudo-grid, by adopting pulsed plasma etching, the first etching is carried out to described pseudo-grid, then the second etching is carried out to the pseudo-grid of remnants, carry out in the process of the first etching in employing pulsed plasma etching to described pseudo-grid, etching machine adopts pulse mode output source power, in the mode of being interrupted, pseudo-grid are etched, time that source power exports and vacant time-interleavedly to carry out, in the time that source power is vacant, the polymer that etching produces is discharged in time from the opening that etching is formed, the open surfaces that the pseudo-grid removing different size are formed does not have polymer and blocks etching, so the etch rate of plasma etching to the different pseudo-grid of size can be consistent, gate dielectric layer under larger-size pseudo-grid can not expose too early thus can ensure preferable quality.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 4, perform step S1, substrate 100 is provided.
Particularly, in the present embodiment, described substrate 100 is silicon substrate, and in other embodiments, described substrate 100 can also be other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, does not do any restriction to this present invention.
Please continue to refer to Fig. 4, perform step S2, form pseudo-grid structure on the substrate 100, described pseudo-grid structure comprises the gate dielectric layer, the pseudo-grid that are positioned on described substrate successively.
In the present embodiment, described substrate 100 is formed the pseudo-grid structure of NMOS, the pseudo-grid structure of described NMOS comprises the first pseudo-grid structure 110A, the second pseudo-grid structure 110B, described first pseudo-grid structure 110A comprises the first pseudo-grid 103A of first grid dielectric layer, first grid dielectric layer surface, the first side wall 104A of the first pseudo-grid 103A sidewall; Described second pseudo-grid structure 110B comprises the second pseudo-grid 103B of second grid dielectric layer, second grid dielectric layer surface, the second side wall 104B of the second pseudo-grid 103B sidewall.In this example, the first pseudo-grid structure 110A, the second pseudo-grid structure 110B are removed in step afterwards, and the first pseudo-grid structure 110A and the second pseudo-grid structure 110B is non-conterminous, and the size of the second pseudo-grid 103B is greater than the size of the first pseudo-grid 103A.
In the present embodiment, the step forming first grid dielectric layer comprises: form the first hafnium layer 101A and the first titanium nitride cap cap layers 102A successively, thus makes the final first grid dielectric layer formed comprise the first hafnium layer 101A from bottom to top and the first titanium nitride cap cap layers 102A.Similarly, described second grid dielectric layer comprises the second hafnium layer 101B from bottom to top and the second titanium nitride cap cap layers 102B, in other embodiments, described first grid dielectric layer, second grid dielectric layer can also be that single layer structure or other materials are formed, and the present invention is not restricted this.
In the present embodiment, the material of described first pseudo-grid 103A, the second pseudo-grid 103B is polysilicon, the material of described side wall is silicon nitride, but the concrete material of the present invention to the first pseudo-grid 103A, the second pseudo-grid 103B, the first side wall 104A, the second side wall 104B does not limit, in other embodiments, the material of described first pseudo-grid 103A, the second pseudo-grid 103B can also be silicon nitride or amorphous carbon, and the material of the first side wall 104A, the second side wall 104B can also be silicon oxynitride.
After the pseudo-grid structure of formation NMOS, before removing pseudo-grid, also at described substrate 100 surface and the first pseudo-grid structure 110A, the second pseudo-grid structure 110B sidewall formation etching barrier layer 106, etching barrier layer 106 between the pseudo-grid structure of NMOS forms the interlayer dielectric layer 105 flushed with the first pseudo-grid structure 110A, the second pseudo-grid structure 110B, the material of described etching barrier layer 106 is silicon nitride, the material of interlayer dielectric layer 105 is silica, but the material of the present invention to etching barrier layer 106, interlayer dielectric layer 105 does not limit.
It should be noted that, in the present embodiment, the pseudo-grid body structure surface of NMOS is also formed with oxide layer (not shown), and described oxide layer is before removing the pseudo-grid in the pseudo-grid structure of NMOS, is formed in the process of PMOS metal gates formed by rear grid technique.So, before carrying out the first etching, also comprise: the oxide layer removing the pseudo-grid surface of described NMOS.
With reference to figure 5, perform step S3, adopt pulsed plasma etching to carry out the first etching, until expose the surface of first grid dielectric layer, second grid dielectric layer respectively to described first pseudo-grid 103A and the second pseudo-grid 103B.
Particularly, etching machine adopts pulse mode output source power, in the mode of being interrupted to the first pseudo-grid 103A, second pseudo-grid 103B etches, such benefit is, time that source power exports and vacant time-interleavedly to carry out, in the off time that source power is vacant, the polymer that etching produces is discharged in time from the opening that etching is formed, under the condition that non-polymer stops, the etch rate of plasma etching to the different pseudo-grid of size is equal, in the process of the first etching, the first pseudo-grid 103A that size is different, second pseudo-grid 103B exposes first grid dielectric layer simultaneously, the surface of second grid dielectric layer, at the end of the first etching, the second hafnium layer 102A under larger-size second pseudo-grid 103B and the second titanium nitride cap cap layers 102B can ensure good pattern, and then improve first grid dielectric layer, the performance of second grid dielectric layer.
The etching gas that first etching adopts comprises hydrogen bromide, oxygen and helium, wherein hydrogen bromide is reacting gas, helium is assist gas, the effect adding oxygen is, oxygen can produce the oxide layer being attached to interlayer dielectric layer 105 surface, to reduce the damage of interlayer dielectric layer 105 upper surface in the process of etching.
In conjunction with reference to figure 5 and Fig. 6, perform step S4, the second etching is carried out to the pseudo-grid of remnants.
Particularly, after the first etching, because pulsed plasma etching has discontinuity, the intensity of etching is more weak, remaining the first pseudo-grid 103A, the second pseudo-grid 103B may be also had not to be removed at the bottom margin of the opening of etching first pseudo-grid 103A, the second pseudo-grid 103B formation.
The present embodiment, the step of carrying out the second etching comprises: adopt first pseudo-grid 103A, the second pseudo-grid 103B of continuumpiston etching to remnants, namely etching machine adopts continuation mode output source power and bias power, under the condition that power is constant, the intensity that the intensity of continuumpiston etching etches compared with pulsed plasma is higher, can pseudo-for first of the bottom margin remnants of opening grid 103A, the second pseudo-grid 103B be removed clean, because the time of the second etching is very short, substantially obvious damage can not be caused to first grid dielectric layer, second grid dielectric layer.But the mode of the present invention to the second etching is not restricted, and may not be continuumpiston etching.
The etching gas of described second etching comprises hydrogen bromide, oxygen, helium, and wherein hydrogen bromide is reacting gas, and helium is assist gas.The effect adding oxygen is, oxygen can produce the oxide layer being attached to interlayer dielectric layer 105 surface, to reduce the damage of interlayer dielectric layer 105 upper surface in the process of etching.
In the present embodiment, for farthest protecting described first grid dielectric layer, second grid dielectric layer, the first etching of pulsed plasma etching is adopted to proceed to until expose first grid dielectric layer respectively, the surface of second grid dielectric layer, that is the etch amount of the first etching accounts for the first pseudo-grid 103A, more than 90% of second pseudo-grid 103B, and the second etching is to the first pseudo-grid 103A, the etch amount of the second pseudo-grid 103B accounts for the first pseudo-grid 103A, the ratio of the second pseudo-grid 103B is very little, but the present invention is not restricted this, in other embodiments, the etch amount of the first etching can also account for the first pseudo-grid 103A, more than 50% of second pseudo-grid 103B.
With reference to figure 7, after the first pseudo-grid 103A, the second pseudo-grid 103B are removed, in order to improve the quality of first grid dielectric layer, second grid dielectric layer further, dry method cleaning is carried out to first, second gate dielectric layer surface, gas 108 for dry method cleaning comprises nitrogen, also comprises one or more in carbon tetrafluoride, Nitrogen trifluoride and sulphur hexafluoride.
Wherein the effect of carbon tetrafluoride, Nitrogen trifluoride and sulphur hexafluoride is cleaning agent, can will be attached to the pollutant removal of first grid dielectric layer, second grid dielectric layer surface, and the plasma of nitrogen ionization can replenish in the gap of the first titanium nitride cap cap layers 101A, the second titanium nitride cap cap layers 101B, the effect of repairing titanium nitride cap cap layers can be played, further increase the performance of first grid dielectric layer, second grid dielectric layer.
It should be noted that, in the present embodiment, in order to contrast the removal process of the different pseudo-grid of size, illustrate the pseudo-grid structure that two sizes are different: the first pseudo-grid structure 110A, the second pseudo-grid structure 110B, but the present invention does not limit to the size of pseudo-grid structure and quantity.
Metal gates is formed in the opening that the method through the pseudo-grid of above-mentioned removal is formed, and the nmos pass transistor forming source-drain area in the substrate and formed, because the quality of gate dielectric layer is higher, the time breakdown characteristic of nmos pass transistor is better.
Above-described embodiment is described for NMOS, but the method for the pseudo-grid of removal of the present invention is not limited to be applied in NMOS, in other embodiments, the method that the present invention can also be adopted to remove pseudo-grid removes the pseudo-grid in PMOS or other transistors adopting rear grid technique to be formed.
In other embodiments, when being the pseudo-grid of the pseudo-grid structure of PMOS when needing the pseudo-grid removed, the pseudo-grid superstructure of described PMOS is also provided with hard mask layer and bottom anti-reflection layer, before the pseudo-grid removing the pseudo-grid structure of PMOS, first remove the hard mask layer and bottom anti-reflection layer that are positioned at the pseudo-grid superstructure of described PMOS.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. remove a method for pseudo-grid, it is characterized in that, comprising:
Substrate is provided;
Form pseudo-grid structure at described substrate surface, described pseudo-grid structure comprises and being positioned on described substrate successively
Gate dielectric layer and pseudo-grid;
Pulsed plasma etching is adopted to carry out the first etching to described pseudo-grid;
Second etching is carried out to the pseudo-grid of remnants.
2. the method for claim 1, is characterized in that, in the step forming pseudo-grid structure, the material of described pseudo-grid is polysilicon, silicon nitride or amorphous carbon.
3. the method for claim 1, is characterized in that, the step forming pseudo-grid structure comprises: on substrate, form hafnium layer and titanium nitride cap cap layers successively, to form described gate dielectric layer.
4. the method for claim 1, is characterized in that, in the step forming pseudo-grid structure, described method also comprises: on the substrate that pseudo-grid structure is exposed, form the interlayer dielectric layer flushed with pseudo-grid structure.
5. method as claimed in claim 4, it is characterized in that, the material of described interlayer dielectric layer is silica.
6. the method for claim 1, is characterized in that, comprises: etching machine adopts pulse mode output source power in employing pulsed plasma etching to the step that described pseudo-grid carry out the first etching.
7. the method for claim 1, is characterized in that, adopts pulsed plasma etching to comprise the step that described pseudo-grid carry out the first etching: the etching gas of the first etching comprises hydrogen bromide, oxygen and helium.
8. the method for claim 1, is characterized in that, adopts pulsed plasma etching to comprise the step that described pseudo-grid carry out the first etching: to carry out the first etching to described pseudo-grid, until expose gate dielectric layer surface.
9. the method for claim 1, is characterized in that, the step of carrying out the second etching comprises: adopt continuumpiston etching to etch the pseudo-grid of remnants, etching gas comprises hydrogen bromide, oxygen and helium.
10. the method for claim 1, is characterized in that, after described second etching, also comprise: carry out dry method cleaning to gate dielectric layer surface, the gas for dry method cleaning comprises nitrogen.
11. methods as claimed in claim 10, is characterized in that, the gas for dry method cleaning also comprise in carbon tetrafluoride, Nitrogen trifluoride and sulphur hexafluoride one or more.
12. the method for claim 1, is characterized in that, in the step forming pseudo-grid structure, described pseudo-grid are the pseudo-grid of NMOS, and the pseudo-grid surface of described NMOS is also formed with oxide layer.
13. methods as claimed in claim 12, is characterized in that, before carrying out the first etching, also comprise: the oxide layer removing the pseudo-grid surface of described NMOS.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106373868A (en) * | 2016-10-10 | 2017-02-01 | 昆山龙腾光电有限公司 | Fabrication method of array substrate |
| CN106504982A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of substrate |
| CN107665823A (en) * | 2016-07-28 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010058538A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | A method for forming damascene gate of semiconductor device |
| CN101038870A (en) * | 2006-03-14 | 2007-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid structure of semiconductor device |
| CN101631897A (en) * | 2007-02-21 | 2010-01-20 | 应用材料股份有限公司 | The pulsed plasma system that is used for etching semiconductor structures with pulsed sample bias |
| CN101908475A (en) * | 2009-06-04 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Method for fabricating a semiconductor device |
| US20130052833A1 (en) * | 2011-08-25 | 2013-02-28 | Tokyo Electron Limited | Method for etching high-k dielectric using pulsed bias power |
-
2013
- 2013-12-30 CN CN201310745827.0A patent/CN104752181B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010058538A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | A method for forming damascene gate of semiconductor device |
| CN101038870A (en) * | 2006-03-14 | 2007-09-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grid structure of semiconductor device |
| CN101631897A (en) * | 2007-02-21 | 2010-01-20 | 应用材料股份有限公司 | The pulsed plasma system that is used for etching semiconductor structures with pulsed sample bias |
| CN101908475A (en) * | 2009-06-04 | 2010-12-08 | 台湾积体电路制造股份有限公司 | Method for fabricating a semiconductor device |
| US20130052833A1 (en) * | 2011-08-25 | 2013-02-28 | Tokyo Electron Limited | Method for etching high-k dielectric using pulsed bias power |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106504982A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of substrate |
| CN106504982B (en) * | 2015-09-07 | 2020-07-17 | 北京北方华创微电子装备有限公司 | Substrate etching method |
| CN107665823A (en) * | 2016-07-28 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
| CN106373868A (en) * | 2016-10-10 | 2017-02-01 | 昆山龙腾光电有限公司 | Fabrication method of array substrate |
| CN106373868B (en) * | 2016-10-10 | 2020-03-10 | 昆山龙腾光电股份有限公司 | Manufacturing method of array substrate |
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