JP2623661B2 - Bipolar transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor that can operate at high speed and at high current.

[Prior Art] Conventionally, a semiconductor device having a conductivity type opposite to the substrate 1 on the P-type silicon substrate 1 as shown in Figure 4 from the need to electrically isolate the device having a bipolar transistor N ^-
The epitaxial layer 4 is grown, and the P ⁺ type base region 7 and the N ⁺ type emitter region 9 are formed in the epitaxial layer 4 using the epitaxial layer 4 as a collector region. Then, in order to reduce the series resistance between the transistor operating region of the device and the collector electrode, an N ⁺ type buried collector layer 2 is formed at the boundary between the epitaxial layer 4 and the substrate 1 and the periphery of the device is formed. The P-type channel stopper layer 3 was provided as an insulating isolation region.

[Problems to be Solved by the Invention] Generally, in order to increase the speed of a bipolar transistor, it is effective to decrease the depth of the base region 7 to shorten the traveling distance of carriers. At the time of current operation, the effective base depth becomes large due to a phenomenon called the Kirk effect. Therefore, it is necessary to suppress the above phenomenon by increasing the impurity concentration in the epitaxial layer 4 as the collector region.

However, in order to reduce the depth of the base region 7, it is necessary to increase the impurity concentration in the base region 7 so that the withstand voltage such as punch-through between the emitter and the collector does not decrease. Further, as described above, since the impurity concentration in the epitaxial layer 4 is increased, the junction capacitance between the collector and the base is significantly increased. For this reason, the structure of the conventional bipolar transistor has a major drawback in increasing the speed of the bipolar transistor. In addition, the high concentration of the epitaxial layer 4 also requires that the concentration of the channel stopper layer 3 in the element isolation region be high, and further increases the capacitance in forming a MOS transistor. Increasing the concentration of the epitaxial layer 4 in this way has been a major drawback not only in increasing the speed of the bipolar transistor but also in combining it with other devices.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a bipolar transistor capable of operating at a high speed and operating at a high current.

[Means for Solving the Problems] A bipolar transistor according to the present invention includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type covering the semiconductor substrate, and a semiconductor layer of the second conductivity type. A second conductivity type high-concentration buried collector region selectively formed in a boundary portion of the semiconductor substrate; a first conductivity type first base region selectively formed in the semiconductor layer; And a second conductivity type emitter region formed above the base region of the bipolar transistor, wherein the first base region immediately below the emitter region is formed to be in contact with the high-concentration buried collector region. And the first
A second base region having an impurity concentration of a first conductivity type lower than that of the base region is formed at a position not directly below the emitter region and in contact with the second conductivity type buried collector region;
Above the base region, the first base region
A third base region having a high conductivity type impurity concentration is formed.

[Operation] In the present invention, the first base region immediately below the emitter region is formed so as to be in contact with the high-concentration buried collector region, and the second base region having a first conductive type impurity concentration lower than that of the first base region. Is formed in contact with the buried collector region at a position not directly below the emitter region, and a third base region having a higher impurity concentration of the first conductivity type than the first base region is located above the second base region. Is formed.

As described above, since the low-concentration second base region is in contact with the high-concentration buried collector region, the capacitance between the base and the collector is reduced. In addition, since the third base region can have a high concentration, the base resistance value is low. Further, since the first base region is in contact with the high-concentration buried collector region, a so-called Kirk effect can be suppressed. Therefore, in the present invention, the speed and current of the bipolar transistor can be increased.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a longitudinal sectional view showing a bipolar transistor according to an embodiment of the present invention.

An N ⁺ -type buried collector layer 2 is provided on a P-type silicon substrate 1, and a P ⁻ -type base region 6 and a P ⁺ -type base region 7 are formed in contact with it. Then, the P ^- type base region 6 has P
⁺⁺ type base region 8 is formed, and P ⁺ type base region 7
An N ⁺ type emitter region 9 is formed thereon. Further, a P-type channel stopper layer 3 is provided as an insulating isolation region so as to surround the element formation region.

In the bipolar transistor thus configured, the P ⁺ -type base region 7 immediately below the N ⁺ -type emitter region 9
A lower concentration P ^- type base region 6 is replaced with an N ⁺ type buried collector layer 2.
, The capacitance between the base and the collector can be reduced.

On the low concentration P ⁻ -type base region 6, a high concentration P −
^{Since the ++} type base region 8 is provided, the base resistance is reduced.

Further, the P ⁺ -type base region 7 immediately below the N ⁺ -type emitter region 9
Is in contact with the high concentration N ⁺ type buried collector layer 2,
The so-called Kirk effect is suppressed, and high-speed and high-current operation is possible.

Next, a method of manufacturing the above-described bipolar transistor will be described.

FIG. 2 is a sectional view showing this manufacturing method in the order of steps.
First, as shown in FIG.
For example, an N ⁺ -type buried collector layer 2 and a P-type channel stopper layer 3 are formed by ion implantation of, for example, arsenic and boron.

Next, as shown in FIG. 2 (b), an N ⁻ -type epitaxial layer 4 is grown, and the photoresist 11 is used as a mask to cover portions other than the emitter and collector forming regions, for example,
A P ⁻ type base region 6 is formed by ion implantation of boron.

Next, as shown in FIG. 2 (c), after the oxide film 5 is formed by a normal LOCOS method, a photoresist 11 covering a portion other than the region where the base region is formed is applied again.
Then, for example, a P ⁺⁺ type base region 8 and a P ⁺ type base region 8 which are shallower and have a higher concentration than the P ⁻ type base region 6 are formed by ion implantation of boron.

Thereafter, as shown in FIG. 2 (d), using the newly formed photoresist 11 as a mask, the N ⁺ -type emitter region 9 is formed on the surface side of the P ⁺ -type base region 7 by arsenic ion implantation, for example. To form Next, a normal contact is opened in the oxide film 5 and a wiring layer of the metal electrode 10 is formed, whereby a bipolar transistor having the structure shown in FIG. 1 is obtained.

3A to 3D are cross-sectional views showing another method of manufacturing the bipolar transistor having the above-described structure in the order of steps. As shown in FIG. 3A, in order to form an N ⁺ -type buried collector layer 2 and a P-type channel stopper layer 3 on a P-type silicon substrate 1, a process similar to that shown in FIG. Then, arsenic and boron ions are implanted into the substrate surface, respectively.

Next, as shown in FIG. 3 (b), after an N ⁻ -type epitaxial layer 4 is formed, an oxide film 5 is formed by a normal LOCOS method.
To form

Thereafter, as shown in FIG. 3 (c), the region other than the emitter and collector formation regions is masked with a photoresist 11, for example, ion implantation of low concentration and high concentration of boron and ion implantation of high concentration are performed. By performing ion implantation of low-concentration boron, a P ⁻ type base region 6 and a P ⁺⁺ type base region 8 are formed.

Next, as shown in FIG. 3 (d), a photoresist 11 having an opening in the emitter formation region is newly formed, and the photoresist 11 is used as a mask in the emitter formation region in the step of FIG. 3 (c). By implanting boron at a concentration between the two boron ion implantation concentrations, P ⁺
A mold base region 7 is formed. Thereafter, a shallow N ⁺ -type emitter region 9 is formed by, for example, arsenic ion implantation.
By employing such a method, the bipolar transistor according to the embodiment of the present invention can be manufactured.

[Effect of the Invention] As described above, according to the present invention, the second base region having a lower concentration than the first base region immediately below the emitter region is provided so as to be in contact with the high-concentration buried collector layer. Since the capacitance between the base and the collector can be reduced and the concentration of the third base region above the low-concentration second base region can be increased, the base resistance value decreases.
Further, since the first base region below the emitter region is in contact with the high-concentration buried collector layer, the so-called Kirk effect phenomenon can be suppressed. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a bipolar transistor according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are cross sections showing a method of manufacturing a bipolar transistor according to an embodiment of the present invention in the order of steps. FIGS. 3 (a) to 3 (d) are cross-sectional views showing another manufacturing method in the order of steps, and FIG. 4 is a cross-sectional view showing a conventional bipolar transistor. 1; P-type silicon substrate; 2; N ⁺ -type buried collector layer; 3; P-type channel stopper layer; 4; N ^- epitaxial layer; 5; oxide film; 6;
P ^- type base region, 7; P ⁺ type base region, 8; P ⁺⁺ type base region, 9; N ⁺ type emitter region, 10; metal electrode, 11; photoresist

Claims (1)

(57) [Claims] A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type covering the semiconductor substrate, and a semiconductor layer selectively formed at a boundary between the semiconductor layer of the second conductivity type and the semiconductor substrate. A two-conductivity-type high-concentration buried collector region; a first base region of a first conductivity type selectively formed in the semiconductor layer; and a second conductivity type formed above the first base region And a first base region immediately below the emitter region is formed so as to be in contact with the high-concentration buried collector region, and a first conductive region is formed between the first base region and the first base region. A second base region having a low impurity concentration is formed at a position not directly below the emitter region and in contact with the buried collector region of the second conductivity type; and above the second base region, the first base region is formed. Than The impurity concentration of the first conductivity type high third
A bipolar transistor, wherein a base region is formed.