JPH05299591A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance a BiCMOS integrated circuit device in operation speed and degree of integration by a method wherein an epitaxial growth process is eliminated from a manufacturing process, and a well small in manufacturing dispersion of impurity concentration distribution is formed. CONSTITUTION:Ions are implanted into all the surface of a P<-> silicon substrate 1 for the formation of an N<+> buried region 2 inside the substrate 1, an NPN transistor T3 is formed on a first N well 3 formed on an N<+> buried region 2, and an NMOS transistor T1 is formed on a retrograde well 6 on the N<+> buried region 2. A buried material 9 filled into a groove provided to the P<-> silicon substrate 1 penetrating the N<+> buried region 2 is used for the element isolation of the NPN transistor T3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to an ECLI / O or EC
The present invention relates to an element isolation method for a BiCMOS integrated circuit device having L logic.

[0002]

2. Description of the Related Art FIG. 5 shows a structural cross section of a conventional BiCMOS integrated circuit. An N epitaxial region 24 is provided on the P ⁻ silicon substrate 1 via an N ⁺ buried region 25 and a P ⁺ buried region 26. N epitaxial region 24
An NPN transistor T ₃ is formed on the second N well 4 and the P well 6, and a PMOS transistor T ₂ is formed on the second N well 4 and the P well 6.
And an NMOS transistor T ₁ are formed.

For isolation between NPN transistors and isolation between NPN transistors and MOS transistors, P well 27, P ⁺ buried region 26, and P by P ⁻ silicon substrate 1 are used.
N separation is used.

Since the P well 6 in which the NMOS transistor T ₁ is formed is electrically isolated from the P ⁻ silicon substrate 1 by the N ⁺ buried region 25 and the N epitaxial region 24, the power supply voltage of the ECL logic is reduced. The potential of the P well 6 can be set independently of V _EE .

[0005]

This conventional BiCMO
In the structure of the S integrated circuit, the P ⁺ buried region 26 for the purpose of element isolation and the N ⁺ buried region 25 mainly for the purpose of reducing the collector resistance of the NPN transistor T ₃ are provided, so that the manufacturing process is performed. A step of growing the N epitaxial region 24 is required. Epitaxial growth of silicon in an LSI manufacturing process is usually performed at a high temperature of about 1100 ° C.

Therefore, in order to prevent lowering of breakdown voltage and increase of capacity (between collector and sub) due to lateral diffusion of impurities in the buried regions 25 and 26 during formation of the N epitaxial region 24, the buried region is buried. It is necessary to separate elements with a margin in the area interval. As a result, there is a limit to the miniaturization and high integration of integrated circuits in this PN separation method.

Further, as the performance of an integrated circuit becomes higher, not only the element size but also the manufacturing variation must be scaled, but it is difficult to reduce the variation in the film thickness and the specific resistance of the epitaxial growth film. For example, if the film thickness of the N epitaxial region 24 varies, it becomes difficult to set the concentration of the P well 6 (retro grade well). To avoid this, if the film thickness is increased, the collector resistance of the NPN transistor T ₃ increases. There is a problem.

Further, if the specific resistance of the N epitaxial region 24 varies, the characteristics and the breakdown voltage of the NPN transistor T ₃ will largely change. Furthermore, epitaxial growth is a process in which there are more manufacturing problems than other processes such as ion implantation and heat treatment, and this process is a bottleneck in improving the manufacturing yield.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel semiconductor integrated circuit device and its which can solve the above problems inherent in the prior art. It is to provide a manufacturing method.

[0010]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a first conductivity type silicon substrate and a second substrate provided in the silicon substrate.
A conductive type high-concentration buried region, a groove provided in the silicon substrate and reaching a region deeper than the high-concentration buried region, an insulator buried in the groove, and surrounded by the insulator. A first region, a second well of the second conductivity type provided on the high-concentration buried region of the first region, and a second region electrically isolated from the first region by the insulator. A second well of the first conductivity type provided on the high-concentration buried region of the second region, a bipolar transistor provided in the first region and having the first well as a collector, And a semiconductor element provided in the region.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be specifically described with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a sectional view showing the structure of a first embodiment according to the present invention.

[0013] Referring to FIG. 1, P ^- there are N ⁺ buried region 2 into the silicon substrate 1, a 1N on N ⁺ buried region 2
An NPN transistor T ₃ is formed on the well 3 to form N ⁺
NMO is formed on the P well 6 on the buried region 2 and the second N well 4
An S transistor T ₁ and a PMOS transistor T ₂ are formed respectively. An embedding material 9 which penetrates the N ⁺ embedding region 2 and is embedded in a groove provided in the P ⁻ silicon substrate 1 is used for isolation between NPN transistors and between NPN transistors and MOS transistors. P well 6
Are electrically isolated from the P ⁻ silicon substrate 1 by the N ⁺ buried region 2 and the buried material 9.

A manufacturing method for realizing the structure according to the first embodiment will be described below with reference to the drawings.

2 (a) and 2 (b) and FIGS. 3 (a) to 3 (c).
3A to 3D are schematic process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device (especially, the first embodiment) according to the present invention.

2 and 3, the impurity concentration 10
After forming a silicon oxide film having a thickness of about 50 mm on the surface of P ⁻ silicon substrate 1 of ¹⁵ to 10 ¹⁶ cm ⁻³ , an acceleration voltage of 1 to 3 MV and a dose amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^{− 2}
The N ⁺ buried region 2 is formed by the phosphorus ion implantation (FIG. 2A).

Then, RT at a temperature of 1000 to 1200 ° C.
Heat treatment is performed by method A. Next, acceleration voltage 100 to 20
After forming the P well 6 by ion implantation of boron at 0 KV and a dose amount of 5 × 10 ¹² to 1 × 10 ¹³ cm ⁻² , an acceleration voltage of 100 to 200 KV and a dose amount of 2 × 10 ¹² to 1 × 1 are formed.
The second N well 4 is formed by performing phosphorus ion implantation twice under the condition of 0 ¹³ cm ⁻² , the acceleration voltage of about 500 KV, and the dose amount of 1 to 2 × 10 ¹³ cm ⁻² . Then, using the photoresist 5 having a thickness of 2 to 4 μm as a mask, an acceleration voltage of about 150 KV and a dose of 1 to 5 × 10 ¹² c.
^Two phosphorus ion implantations are performed under the condition of m ^-2 , the acceleration voltage of 500 to 700 KV, and the dose of about 1 x 10 ¹⁴ cm ^-2.
The first N well 3 is formed by repeating the process (FIG. 2).
(B)).

Next, a silicon nitride film and polycrystalline silicon are used to select a thickness of 0.
A field oxide film 7 having a thickness of 4 to 0.8 μm is formed (see FIG. 2).
(C)).

Next, the field oxide film 7 and silicon are etched to form a groove having a depth of 4 to 6 μm, and a P ⁺ region 8 is formed by ion implantation of boron. (Fig. 3
(A)).

Further, after forming an oxide film having a thickness of 10 to 50 nm on the surface of the groove, the groove is filled with an embedding material 9 made of, for example, a BPSG film or polycrystalline silicon, and a thickness of 50 to 200 n.
The surface of the embedding material 9 is covered with m silicon nitride film 10. Then, accelerating voltage 70-150KV, dose 1x
After forming the collector phosphorus region 11 by ion implantation of phosphorus of 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2 , accelerating voltage of 250 to 500
By ion-implanting boron into the P well 6 with a KV and a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^-2 ,
We are trying to make a retrograde well (Fig. 3 (b)).

Thereafter, the channel doping to the second N well 4 and the P well 6 and the thickness of 10 to 2 are performed by using a known technique.
Formation of 0 nm gate oxide film 12 and gate electrode 13, L
N ⁺ SD area 14 and P ⁺ SD area 15 having a DD structure
1 is formed, and a P-type base region 16, a P ⁺ GB region 17, an emitter polysilicon 19 and an N ⁺⁺ emitter region 18 are formed, and an NMOS transistor T ₁ , a PMOS transistor T ₂ , and an NPN transistor T ₃ are formed. The structure of is realized.

Next, a second embodiment according to the present invention will be described with reference to FIG.

FIG. 4 is a structural sectional view showing a second embodiment according to the present invention.

Referring to FIG. 4, unlike the above-described first embodiment, a collector P ⁺ region 20, an N-type base region 21, and an N-type base region 21, N are formed in the P well 6 electrically isolated from the P ⁻ silicon substrate 1. ^{A +} GB region 22 and a P ⁺ emitter region 23 are provided, and a PNP transistor T ₄ is formed.

In the first N well 2, the above-mentioned first
The NPN transistor T ₃ is formed in the same manner as in the above embodiment.

In the structure using the conventional epitaxial growth film, if the concentration of the deep region of the P well 6 is increased in order to improve the performance of the PNP transistor, the variation in the film thickness of the epitaxial growth film greatly affects the characteristics of the PNP transistor. Therefore, in order to obtain stable characteristics of the PNP transistor, it is necessary to thicken the epitaxial growth film, and as a result, the performance of the NPN transistor is sacrificed. However, such a problem does not occur in the above-described structure according to the second embodiment, so that it is possible to simultaneously improve the performance of the PNP transistor T ₄ and the NPN transistor T ₃ .

[0027]

As described above, according to the present invention,
The element isolation of the first region and the second region is performed by the high-concentration buried region and the insulator buried in the groove provided so as to surround the first region. Since the high-concentration buried region is formed by ion-implanting the entire surface in the silicon substrate, it is not necessary to provide an epitaxial growth film of silicon. Therefore, NP
It is possible to improve the performance of the N-transistor and stabilize the characteristics of the NMOS transistor at the same time.

For example, in the conventional structure, the epitaxial growth film has a thickness of 1 μm in order to obtain a high performance NPN transistor.
When the thickness is set to the following, it is difficult to stably retrograde the P well forming the NMOS transistor and the characteristics of the NMOS transistor are varied. Since it is possible to control the concentration of the well region, it is possible to easily obtain a high-performance NPN transistor and an NMOS transistor having characteristics with small manufacturing variations.

Further, the technique of the present invention can be applied to the field of analog, and the manufacturing variation can be kept small while N
It is also possible to improve the performance of the PN transistor and the PNP transistor.

Further, according to the present invention, since the steps of epitaxial growth, which often cause accidents in the manufacturing process, are eliminated,
The effect of improving the yield can also be obtained.

According to the technique of the present invention, since the trench provided in the silicon substrate is used for element isolation between the bipolar transistors, the area required for isolation is reduced by 30% or more as compared with the conventional PN isolation method. be able to. Therefore, a great effect can be obtained for high integration of the LSI.

[Brief description of drawings]

FIG. 1 is a structural sectional view showing a first embodiment according to the present invention.

FIG. 2 is a schematic process sectional view showing the manufacturing method of the first embodiment shown in FIG.

FIG. 3 is a schematic process sectional view (continuation to FIG. 2) showing the manufacturing method of the first embodiment shown in FIG.

FIG. 4 is a structural sectional view showing a second embodiment according to the present invention.

FIG. 5 is a structural cross-sectional view of a conventional BiCMOS integrated circuit.

[Explanation of symbols]

1 ... P ^- type silicon substrate 2 ... N ⁺ buried region 3 ... 1st N well 4 ... 2nd N well 5 ... Photoresist 6 ... P well 7 ... Field oxide film 8 ... P ⁺ region 9 ... Buried material 10 ... Silicon nitride Film 11 ... Collector phosphorus region 12 ... Gate oxide film 13 ... Gate electrode 14 ... N ⁺ SD region 15 ... P ⁺ SD region 16 ... P type base region 17 ... P ⁺ GB region 18 ... N ⁺⁺ emitter region 19 ... Emitter poly Silicon 20 ... Collector P ⁺ region 21 ... N type base region 22 ... N ⁺ GB region 23 ... P ⁺ emitter region 24 ... N epitaxial region 25 ... N ⁺ buried region 26 ... P ⁺ buried region 27 ... P well 2

Claims (4)

[Claims] 1. A silicon substrate of a first conductivity type, and a high-concentration buried region of a second conductivity type provided in the silicon substrate,
A groove provided in the silicon substrate and reaching the high-concentration buried region, an insulator buried in the groove, a first region surrounded by the insulator, and the high-concentration region in the first region. A second well of the second conductivity type provided on the buried region,
A second region electrically isolated from the first region by the insulator, a second well of the first conductivity type provided on the high concentration buried region of the second region, and the first region A semiconductor integrated circuit device comprising: a bipolar transistor provided therein, the collector being the first well; and a semiconductor element provided in the second region. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor element is a MOS transistor having a second conductivity type channel. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor element comprises a bipolar transistor having the second well as a collector. 4. A step of forming a second-conductivity-type high-concentration buried region on the entire surface by a high-energy implantation method in a first-conductivity-type silicon substrate; Forming a trench in the silicon substrate so as to reach a region deeper than the buried region; filling the trench with an insulator; and a collector region of a bipolar transistor on the high-concentration buried region in the first region. The first of the second conductivity type
Forming a well, and forming a second well of the first conductivity type in which a semiconductor element is formed on the high-concentration buried region of the second region electrically separated from the first region by the insulator. A method of manufacturing a semiconductor integrated circuit device, comprising: