JPS63136660A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the efficiency of a position hole injection and transportation from an emitter and also increase an hFE by forming a p-type diffused layer that turns into an n-type layer surface emitter and collector using an n-type semiconductor layer as a base located below a recessed part, thereby making up a horizontal pnp transistor after connecting the above p-type diffused layer to the n<+> type buried layer. CONSTITUTION:An Sb diffusion is carried out in advance at a part of the surface of a p-Si substrate 1 and a silicon layer 2 is formed on the p-Si substrate by burying an n<+> buried layer 3 in the p-Si substrate. Then, recessed parts (grooves) 9a and 9b are formed by etching silicon. Subsequently, a p-layer 12 that turns into an isolation part as well as the p-layer 8 that turns into an emitter and collector of a pnp transistor are respectively formed at the surface of an epitaxial n<-> layer 2 including the above recessed parts. And further, n-layers 10 that turn into a collector takeoff part of an npn transistor and a base takeoff part of the pnp transistor as well as a collector peripheral part are formed. Moreover, after performing As<+> ion implantation and its diffusion, an n<+> layer 5 that turns into the emitter of the npn transistor and the n<+> layer 6 that turns into a collector-contact are formed; besides, the n<+> layer 11 that turns into a base-contact of the pnp transistor is formed as well. Thus, the above approach can improve the efficiency of transportation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a lateral pnp (pnp) transistor coexists on the surface of one semiconductor substrate.

[Prior art]

Bipolar vertical n on one Si (silicon) semiconductor substrate
When a pn) transistor and a lateral pnp) transistor coexist, an epitaxial n-8i layer 2 is formed on a p'''' type Si substrate (substrate) 1, with reference to FIG. n+ buried layer 3 at the bottom of layer 2
is buried, and the rehashed p+ layer 4, emitter n+ layer 5, and collector extraction n+ layer 6 are diffused on the surface of one region of this n-8i layer 2 by selective diffusion to form an npn) transistor. <It is usual to form an 0 layer 8, which will become a collector, on the surface of the other region of the n-3i layer, alongside or surrounding the 9 layer 7, which will become an emitter.

[Problem that the invention seeks to solve].

A conventional lateral pnp) transistor having the structure described above is a thick (1
, 5 to 2.3 μm) is formed on the surface of the epitaxial Si layer 2, and during transistor operation, holes (holes = h) from the emitter to the collector are mostly injected below the emitter, as shown in Figure 10. As a result, the injection distribution to the collector in the lateral direction becomes relatively small.

In other words, the hole transport efficiency per unit area is low, and therefore the hFE of the horizontal pnp transistor is low. Further, in the above structure, fT and hFE become small due to the wide base width W. Even if the base width is made smaller, the n''' Si layer has a low concentration.
VCEO (breakdown voltage) decreases.

By the way, the present applicant has partially thinned the epitaxial semiconductor layer by forming a recessed groove in a part of the semiconductor substrate, and provided a linear element such as an npn transistor in the thicker part, while installing an isolator in the thinned part. It has been proposed to provide a ration (element isolation) section and an IL (implantation integration logic) element (Japanese Patent Laid-Open No. 58-79752).

According to this method, the epitaxial layer can be made partially thin (and the isolation width can be narrowed), and the I
It is possible to secure the operating margin and increase the speed of the IL element.

The present invention further develops the technique of partially thinning the epitaxial layer described above and solves the problems of the lateral transistor described above.

Therefore, it is an object of the present invention to improve hole injection efficiency and transport efficiency from the emitter in a lateral transistor, thereby improving hFE and BVCEO.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an epitaxial n-type semiconductor layer is formed on one main surface of a p-type semiconductor substrate, and an n-type semiconductor layer is formed below this n-type semiconductor layer.
A +-type buried layer is buried, a recess is made in a part of the surface of the n-type semiconductor layer, and the n-type semiconductor layer under the recess is used as a base to form a p-type diffusion layer that becomes the emitter and collector on the surface of this n-type layer. A lateral pnp transistor is formed by forming layers and connecting them to an n+ type buried layer. or,
A collector periphery n+ layer is provided in contact with the collector periphery.

[Effect]

According to the above-mentioned means, p becomes a collector and an emitter.
By connecting the diffusion layer to the n+ buried layer, holes can only be injected from the emitter in the lateral direction, improving transport efficiency, and providing an n+ layer around the collector reduces B
VCEO is improved and the above objective can be achieved.

〔Example〕

FIG. 1 is a sectional view of a horizontal pnp (pnp) transistor showing one embodiment of the present invention.

1 is a p-8i substrate, 2 is an epitaxial n-8i layer, and the thickness thereof is approximately 1.5 to 2.0 μm. 3 is an n+ buried layer.

Reference numeral 9 denotes a recess formed in the surface of the epitaxial n layer 2, and its depth is approximately 0.8 μm.

Reference numeral 7 denotes a p+ diffusion layer serving as an emitter, and is provided so as to be connected to the n+ buried layer 31C from the surface of the n layer 2 in the recessed portion 9.

Reference numeral 8 denotes a p diffusion layer which becomes a collector, and surrounds the emitter p+ layer 7 along with its periphery.
It is provided so as to be connected to the buried layer 3.

IO is provided around the collector 9 layer 8 in contact with the collector 9 layer 8 in the collector periphery B+ diffusion layer.

Reference numeral 11 denotes a base-extracting n-layer, which is provided on the surface of the n-layer 2 within the recessed portion.

In this embodiment, the following effects can be obtained by adopting the above-mentioned configuration.

+11 By forming the concave portion, the thickness of the epitaxial Si layer is reduced to about 1.0 μm, and the bottoms of the emitter p+ layer 7 and the collector layer 8 are diffused so as to be connected to the n+ buried layer 3. I can do it.

With this K, the amount of holes injected downward from the emitter becomes smaller, and most of them are deflected laterally as shown by the arrow (h) and injected into the collector, improving the transport efficiency.

(2) By providing B+diffusion layer 10 around the collector, the extension of the depletion layer from the collector is suppressed and BVCEO
can be improved.

FIG. 2 shows an application example of the present invention, and is a cross-sectional view of a semiconductor device in which a single semiconductor substrate [NPN] transistor and a lateral PNP transistor coexist.

In the figure, the n-8i region under the concave portion 9a has a horizontal pn
p) A transistor is provided, and in the n-8i region under the other recessed portion 9b, an n+ layer 6 for taking out the collector of the npn transistor and an eye frame layer 12 are provided.

In the n-8i region where no recess is formed, a base p diffusion layer 4 and an emitter n+ diffusion layer 5 of the npn transistor/transistor are provided. The collector extraction n+ layer 6 is connected to the n+ buried layer 3.

3 to 8 are cross-sectional views of the process for manufacturing the semiconductor device of the embodiment shown in FIG. 2. The process will be explained below.

[11p-8i substrate (substrate) 1 has a part of its surface subjected to sb diffusion, and an n+ buried layer 3 is buried thereon, and an n-5j layer 2 is epitaxially grown thereon.
It is formed to a thickness of about 5 μm (Fig. 3).

(2) The photoresist-treated oxide film 13 is masked with KSi
A recess (groove) 9 a with a depth of 0.8 μm is etched.
+9 b is formed (Fig. 4).

(3) Epitaxial n-7i2i including concave parts
B ions are selectively implanted using the newly formed oxide film 14 on the ffi as a mask, and the nine layers 12 that will become the isolator part are formed.
, pnp) nine layers 8 are formed to serve as the emitter and collector of the transistor (FIG. 5).

(4) Using the oxide film mask 16, selectively implant P (phosphorous) ions to form the n layer that will become the collector extraction part of the npn transistor, the n layer that will become the base extraction part of the pnp transistor, and the collector peripheral area. Form n#10 (
Figure 6).

(5) B+ ions are selectively implanted and diffused to form the p+ layer 4 which will become the base of the npn) transistor and the p+ layer 7 which will become the pnp) transistor (FIG. 7).

(Selectively implanting and diffusing 61As+ ions to form the emitter n layer 5 and the n+ layer 6 that will become the collector contact of the npn transistor, as well as forming the n+ layer 11 that will become the base contact of the pnp transistor) (
Figure 8).

Thereafter, although not shown, an insulating film such as CVD-PSG is formed on the entire surface, and contact photoetching is performed to complete the semiconductor device in which electrodes are provided by vapor deposition of A stone in the window-opened portions.

According to this example process, the following effects can be obtained.

(Using pSi etch, the epitaxial thickness can be reduced to the most appropriate thickness.

At the same time, this makes it possible to form an isolation section in a narrow space, and it is possible to form an isolation section in a narrow space.
np) Transistor can increase transport efficiency.

(2) Isolation p diffusion, npn) Each step of transistor base p+ diffusion and collector n diffusion is directly p
np) It can be used for emitter/collector diffusion of transistors, and all diffusion can be realized without adding new steps.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

The present invention can be used for bipolar ICs in general.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, horizontal pnp) with coexisting npn) transistors.
In transistors, the hole transport rate, injection efficiency, BV CK O, and fT can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a horizontal PNP device showing an embodiment of the present invention. FIG. 2 shows an npn element and a pn element showing an applied example of the present invention.
1 is a cross-sectional view of a semiconductor device having a p-element. 3 to 8 are process cross-sectional views showing the manufacturing process of the semiconductor device shown in FIG. 2. FIG. 9 is a sectional view showing a conventional example of a semiconductor device having an NPN element and a PNP element on one substrate. FIG. 10 is a front cross-sectional and oblique view showing the operation mode of holes in a conventional example of a PNP element. 1...p-8i substrate, 2...epitaxial n''S
i layer, 3...n+ buried layer, 4...npn) base p+ layer of transistor, 5... emitter n+ layer, 6...
・Collector extraction n layer, 7...pnp) transistor emitter p+ layer, 8...collector extraction, 10
...N layer around collector, 11...Base extraction n+
Layer, 12...Isowarf 1F 9 layers. , r- Agent Patent Attorney Katsuo Ogawa / Figure 1 Figure 2 """ PytP Tk'3 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A high concentration buried layer of a second conductivity type is buried between the first conductivity type semiconductor substrate and a second conductivity type semiconductor layer epitaxially grown on one principal surface thereof, A recess is formed in the surface of the conductive type semiconductor layer, and the second conductive type semiconductor layer under the recess is used as a base, and two first conductive type diffusion layers are formed side by side on the surface of the second conductive type semiconductor layer. A semiconductor device characterized in that one of the layers is an emitter and the other is a collector, and these first conductivity type diffusion layers are connected to the second conductivity type heavily doped buried layer. 2. The semiconductor device according to claim 1, wherein the first conductivity type diffusion layer serving as the emitter has a higher concentration than the first conductivity type diffusion layer serving as the collector. 3. The first conductivity type diffusion layer serving as the collector is surrounded by a highly concentrated second conductivity type layer around the collector.
3. The semiconductor device according to item 1 or 2. 4. Epitaxially grow an n^-type silicon layer on a p-type silicon substrate, and etch a part of the surface of this n^-type silicon layer to form a recess to form n^-type silicon without a recess. In forming a vertical npn semiconductor element on the surface of the layer and also forming an isolation part and a horizontal pnp semiconductor element on the surface of the silicon layer in which the recessed part is formed, the isolation p-type diffusion is used to form the pnp semiconductor element. Manufacture of a semiconductor device characterized by forming a p-type diffusion layer to serve as an emitter and a collector, and forming an emitter p^+-type diffusion layer of a pnp semiconductor element using base p^+-type diffusion of an npn semiconductor element. Law.