JPH0834244B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0834244B2 JPH0834244B2 JP60133391A JP13339185A JPH0834244B2 JP H0834244 B2 JPH0834244 B2 JP H0834244B2 JP 60133391 A JP60133391 A JP 60133391A JP 13339185 A JP13339185 A JP 13339185A JP H0834244 B2 JPH0834244 B2 JP H0834244B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- buried layer
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は半導体集積回路（IC）に用いられる埋込層の
改良に関する。Description: (a) Field of Industrial Application The present invention relates to an improvement in a buried layer used in a semiconductor integrated circuit (IC).
（ロ） 従来の技術 埋込層は例えば特開昭59−189665号公報第６図に示さ
れているように、ICの寄生効果を防止する手段として良
く用いられている。(B) Conventional Technology The buried layer is often used as a means for preventing the parasitic effect of IC as shown in FIG. 6 of JP-A-59-189665.
第３図はこのような埋込層を備えたNPNトランジスタ
を示し、Ｐ型半導体基板（１）上に形成したＮ型エピタ
キシャル層（２）と、基板（１）とエピタキシャル層
（２）との間に選択的に設けられたN+型埋込層（３）
と、この埋込層（３）を囲むようにエピタキシャル層
（２）を貫通したP+型の分離領域（４）と、分離領域
（４）により島状に分離された島領域（５）と、島領域
（５）表面に形成したＰ型のベース領域（６）と、ベー
ス領域（６）表面に形成したN+型のエミッタ領域（７）
と、N+型のコレクタコンタクト領域（８）と、エピタキ
シャル層（２）表面を被覆する酸化膜（９）と、この酸
化膜（９）の電極孔を介して各領域とオーミック接触す
る電極（10）とで構成されている。FIG. 3 shows an NPN transistor having such a buried layer, which comprises an N-type epitaxial layer (2) formed on a P-type semiconductor substrate (1), a substrate (1) and an epitaxial layer (2). N + type buried layer selectively provided between (3)
A P + -type isolation region (4) penetrating the epitaxial layer (2) so as to surround the buried layer (3), and an island region (5) isolated by the isolation region (4) in an island shape. , A P-type base region (6) formed on the surface of the island region (5) and an N + -type emitter region (7) formed on the surface of the base region (6)
An N + -type collector contact region (8), an oxide film (9) covering the surface of the epitaxial layer (2), and an electrode (which makes ohmic contact with each region through the electrode hole of the oxide film (9) ( 10) and are composed of.
斯る構造の埋込層（３）は、基板（１）にあらかじめ
Ｎ型不純物をドープしておいてからエピタキシャル層
（２）を形成し、後の分離領域（４）拡散工程により、
先にドープしたＮ型不純物を上下方向に拡散させて形成
する。従って埋込層（３）内における濃度プロファイル
は基板（１）表面部（図示破線部）が最も高くなり、埋
込層（３）底部又はエピタキシャル層（２）と接する上
面部が最も低くなる。そして斯上した構造における分離
耐圧は、その接合が他の接合より高い不純物濃度領域ど
うしの接合になるので、基板（１）と埋込層（３）との
接合により決まっていた。In the buried layer (3) having such a structure, the substrate (1) is doped with N-type impurities in advance, and then the epitaxial layer (2) is formed.
It is formed by diffusing the previously doped N-type impurities in the vertical direction. Therefore, the concentration profile in the buried layer (3) is highest at the surface portion of the substrate (1) (shown by the broken line in the figure), and lowest at the bottom portion of the buried layer (3) or the top surface in contact with the epitaxial layer (2). The isolation breakdown voltage in the above structure is determined by the junction between the substrate (1) and the buried layer (3) because the junction is a junction between the impurity concentration regions having a higher concentration than the other junctions.
（ハ） 発明が解決しようとする問題点 しかしながら、前記した如く埋込層（１）内おいては
図示点線部が最も高濃度になるので、分離耐圧は埋込層
（３）側面の基板（１）表面部（図示Ａ部）で決められ
てしまい、埋込層（３）自身の不純物濃度を下げても高
い分離耐圧が得られないという欠点があった。(C) Problems to be Solved by the Invention However, as described above, in the buried layer (1), the dotted line portion in the drawing has the highest concentration. 1) The surface portion (A portion in the drawing) is determined, and there is a drawback that a high isolation breakdown voltage cannot be obtained even if the impurity concentration of the buried layer (3) itself is lowered.
（ニ） 問題点を解決するための手段 本発明は斯上した欠点に鑑みてなされ、分離耐圧を向
上した半導体集積回路装置を得ることを目的とし、第１
の埋込層（13）の側面を覆う様に、第１の埋込層（13）
より低不純物濃度の第２の埋込層（14）を設けたことを
特徴とする。(D) Means for Solving Problems The present invention has been made in view of the above drawbacks, and an object thereof is to obtain a semiconductor integrated circuit device having an improved isolation breakdown voltage.
The first buried layer (13) so as to cover the side surface of the buried layer (13) of
The second buried layer (14) having a lower impurity concentration is provided.
（ホ） 作用 本発明によれば、分離耐圧を決める接合の中で最も耐
圧の低い部分に第１の埋込層（13）より低不純物濃度の
第２の埋込層（14）を設けているので、この部分では空
乏層が広がりやすくなり、その幅が広がった分だけ耐圧
が向上する。(E) Operation According to the present invention, the second buried layer (14) having a lower impurity concentration than the first buried layer (13) is provided in the portion having the lowest breakdown voltage in the junction that determines the isolation breakdown voltage. Therefore, the depletion layer easily spreads in this portion, and the breakdown voltage improves as the width increases.
（ヘ） 実施例 以下本発明を図面を参照しながら詳細に説明する。(F) Examples The present invention will be described in detail below with reference to the drawings.
第１図は本発明による埋込層を用いたNPNトランジス
タを示し、Ｐ型半導体基板（１）上に形成したＮ型エピ
タキシャル層（２）と、基板（１）とエピタキシャル層
（２）との間に埋込まれたN+型の第１の埋込層（13）
と、第１の埋込層（13）の側面を覆う様に設けたN-型の
第２の埋込層（14）と、第１及び第２の埋込層（13）
（14）を囲む様にエピタキシャル層（２）を貫通したP+
型分離領域（４）と、分離領域（４）により島状に分離
された島領域（５）と、島領域（５）表面に形成したＰ
型のベース領域（６）と、ベース領域（６）表面に形成
したN+型のエミッタ領域（７）と、N+のコレクタコンタ
クト領域（８）と、エピタキシャル層（２）表面を被覆
する酸化膜（９）と、酸化膜（９）の電極孔を介して各
領域とオーミック接触する電極（10）とで構成されてい
る。FIG. 1 shows an NPN transistor using a buried layer according to the present invention, which comprises an N-type epitaxial layer (2) formed on a P-type semiconductor substrate (1), a substrate (1) and an epitaxial layer (2). First buried layer of N + type buried between (13)
And an N − -type second burying layer (14) provided so as to cover the side surface of the first burying layer (13), and the first and second burying layers (13)
P + penetrating the epitaxial layer (2) so as to surround (14)
The mold separation region (4), the island region (5) separated into islands by the separation region (4), and the P formed on the surface of the island region (5).
-Type base region (6), N + -type emitter region (7) formed on the surface of the base region (6), N + collector contact region (8), and oxidation covering the surface of the epitaxial layer (2) It is composed of a film (9) and an electrode (10) which makes ohmic contact with each region through the electrode hole of the oxide film (9).
本発明の最も特徴とする点は、第１の埋込層（13）の
側面に第２の埋込層（14）を設けた点にある。すなわ
ち、従来最も耐圧が低かった部分に第１の埋込層（13）
より低不純物濃度の第２の埋込層（14）を設けているの
で、この部分では空乏層が広がりやすくなり、幅が広が
った分だけ耐圧が向上する。従ってこの構造によれば、
分離耐圧は第１の埋込層（13）側面部では決まらず、図
示破線部よりも不純物濃度が低い第１の埋込層（13）底
部と基板（１）との接合により決まるので、従来より高
い分離耐圧を得ることができる。The most characteristic point of the present invention is that the second burying layer (14) is provided on the side surface of the first burying layer (13). That is, the first buried layer (13) is formed in the portion where the breakdown voltage is the lowest in the past.
Since the second buried layer (14) having a lower impurity concentration is provided, the depletion layer easily expands in this portion, and the breakdown voltage improves as the width increases. Therefore, according to this structure,
The isolation breakdown voltage is not determined by the side surface of the first buried layer (13), but is determined by the junction between the bottom of the first buried layer (13) and the substrate (1) whose impurity concentration is lower than the broken line in the figure. A higher isolation breakdown voltage can be obtained.
以下本発明の製造方法の一例を第２図（イ）〜（ニ）
を用いて説明する。先ず第２図（イ）に示す如く、Ｐ型
基板（１）表面の第１の埋込層（13）となるべき領域に
酸化膜（９）をススクとしてＮ型不純物、例えばリン
（Ｐ）をドープしてN+型ドープ領域（15）を形成する。
次に第２図（ロ）に示す如く、酸化膜（９）を第１の埋
込層（13）より大きく開口し、Ｎ型不純物を例えばイオ
ン注入法によりドープしてN-型ドープ領域（16）を形成
する。続いて第２図（ハ）に示す如く、周知の気相成長
法によりエピタキシャル層（２）を形成する。さらに第
２図（ニ）に示す如く、選択拡散法を用いてＰ型不純
物、例えばボロン（Ｂ）を拡散してP+型分離領域（４）
を形成する。そしてこの時の熱拡散により、先に形成し
ていたN+型ドープ領域（15）及びN-型ドープ領域（16）
が最も上下方向に拡散され、第１及び第２の埋込層（1
3）（14）が形成される。第２の埋込層（14）は第１の
埋込層（13）まり低不純物濃度であるため、拡散速度の
違いから第１の埋込層（13）より拡散深さが浅くなる。
そうして島領域（５）表面にベース領域（６）、エミッ
タ領域（７）及びコレクタコンタクト領域（８）を選択
拡散し、各領域上に電極（10）を配設して完了する。Hereinafter, an example of the manufacturing method of the present invention will be described with reference to FIGS.
Will be explained. First, as shown in FIG. 2 (a), an N-type impurity such as phosphorus (P) is formed on the surface of the P-type substrate (1) using the oxide film (9) as a mask in a region to be the first buried layer (13). To form an N + -type doped region (15).
Next, as shown in FIG. 2B, the oxide film (9) is opened larger than the first buried layer (13), and N type impurities are doped by, for example, an ion implantation method to form an N − type doped region ( 16) to form. Subsequently, as shown in FIG. 2C, an epitaxial layer (2) is formed by a known vapor phase growth method. Further, as shown in FIG. 2D, a P type impurity such as boron (B) is diffused by a selective diffusion method to form a P + type isolation region (4).
To form. Then, due to thermal diffusion at this time, the N + -type doped region (15) and the N − -type doped region (16) that were previously formed
Are diffused most vertically, and the first and second buried layers (1
3) (14) is formed. The second buried layer (14) has a lower impurity concentration than the first buried layer (13) and therefore has a smaller diffusion depth than the first buried layer (13) due to the difference in diffusion speed.
Then, the base region (6), the emitter region (7) and the collector contact region (8) are selectively diffused on the surface of the island region (5), and the electrode (10) is arranged on each region to complete the process.
尚、上記実施例では第２の埋込層（14）をＮ型領域と
してあるが、Ｐ型領域で構成しても実施可能である。Although the second buried layer (14) is an N-type region in the above-mentioned embodiment, it can be implemented with a P-type region.
（ト） 発明の効果 以上説明した如く、本発明によれば従来最も耐圧が低
かった部分に第２の埋込層（14）を設けているので、従
来より高い分離耐圧が得られるという利点を有する。ま
た高い分離耐圧が得られるので、高耐圧を要とする半導
体集積回路が容易に設計できるという利点を有する。(G) Effect of the Invention As described above, according to the present invention, the second buried layer (14) is provided in the portion having the lowest breakdown voltage in the related art. Have. Further, since a high isolation breakdown voltage can be obtained, there is an advantage that a semiconductor integrated circuit requiring a high breakdown voltage can be easily designed.
第１図は本発明を説明するための断面図、第２図（イ）
乃至第２図（ニ）はその製造方法を説明するための断面
図、第３図は従来例を説明するための断面図である。 主な図番の説明 （１）は半導体基板、（２）はエピタキシャル層、（1
3）は第１の埋込層、（14）は第２の埋込層、（15）はN
+型ドープ領域、（16）はN-型ドープ領域である。FIG. 1 is a sectional view for explaining the present invention, and FIG. 2 (a).
2 (d) is a sectional view for explaining the manufacturing method, and FIG. 3 is a sectional view for explaining the conventional example. Description of main drawing numbers (1) is semiconductor substrate, (2) is epitaxial layer, (1
3) is the first buried layer, (14) is the second buried layer, and (15) is N
The + type doped region, (16) is the N − type doped region.
Claims (1)
型のエピタキシャル層と、 前記基板と前記エピタキシャル層との間に埋め込まれ前
記基板表面から上下方向に拡散された高濃度逆導電型の
第１の埋め込み層と、 前記第１の埋め込み層を取り囲み前記エピタキシャル層
を貫通して島状の島領域を形成する一導電型の分離領域
とを具備する半導体集積回路装置において、 前記第１の埋め込み層の側面を覆う様に、前記分離領域
とは離間して、前記基板表面から上下方向に拡散された
前記第１の埋め込み層より低不純物濃度の第２の埋め込
み層を具備したことを特徴とする半導体集積回路装置。1. An epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a high-concentration inverse conductivity type buried between the substrate and the epitaxial layer and diffused vertically from the surface of the substrate. A semiconductor integrated circuit device comprising: a first buried layer; and an isolation region of one conductivity type that surrounds the first buried layer and penetrates the epitaxial layer to form an island-shaped island region. A second burying layer having a lower impurity concentration than the first burying layer diffused vertically from the substrate surface so as to cover the side surface of the burying layer. A characteristic semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133391A JPH0834244B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133391A JPH0834244B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61290735A JPS61290735A (en) | 1986-12-20 |
| JPH0834244B2 true JPH0834244B2 (en) | 1996-03-29 |
Family
ID=15103645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60133391A Expired - Lifetime JPH0834244B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834244B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5093707A (en) * | 1988-04-27 | 1992-03-03 | Kabushiki Kaisha Toshiba | Semiconductor device with bipolar and cmos transistors |
| JP3031117B2 (en) * | 1993-06-02 | 2000-04-10 | 日産自動車株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50113476A (en) * | 1974-02-18 | 1975-09-05 | ||
| JPS50143476A (en) * | 1974-05-08 | 1975-11-18 | ||
| JPS61208235A (en) * | 1985-03-13 | 1986-09-16 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-06-19 JP JP60133391A patent/JPH0834244B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61290735A (en) | 1986-12-20 |
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