JP2002190593A - Insulated gate fet and method of manufacturing the same - Google Patents
Insulated gate fet and method of manufacturing the sameInfo
- Publication number
- JP2002190593A JP2002190593A JP2000390141A JP2000390141A JP2002190593A JP 2002190593 A JP2002190593 A JP 2002190593A JP 2000390141 A JP2000390141 A JP 2000390141A JP 2000390141 A JP2000390141 A JP 2000390141A JP 2002190593 A JP2002190593 A JP 2002190593A
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- region
- base
- base region
- semiconductor substrate
- forming
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Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000012010 growth Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 35
- 238000009792 diffusion process Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、柱状に形成された
ベース領域を有する絶縁ゲート型電界効果トランジスタ
及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor having a columnar base region and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】動作抵抗の低減化と高耐圧化の両方を高
水準に達成することを目的として絶縁ゲート型電界効果
トランジスタ（以下ＦＥＴと言う）を図１に示すように
構成することは公知である。このＦＥＴは、Ｎ形ドリフ
ト領域１とＮ＋形ドレイン領域２と複数のＰ形ベース領
域３と複数のソース領域４とから成るシリコン半導体基
体５と、ドレイン電極６と、ソース電極７と、ゲート電
極８と、ゲート絶縁膜９と、周辺保護絶縁膜１０と、層
間絶縁膜１１とを備えている。このＦＥＴのボデイ領域
又はチャネル形成領域と呼ぶことのできるベース領域３
は特異な形状を有し、ドリフト領域１の厚み方向に深く
柱状に形成されており、その底面はドリフト領域１とド
レイン領域２との界面近くまで達している。複数のベー
ス領域３を柱状に形成すると、ベース領域３とドリフト
領域１との間のＰＮ接合に高い逆方向電圧が印加された
時に複数のベース領域３の相互間のドリフト領域１が空
乏層によって埋められ、耐圧が向上する。また、図１の
構造の場合、ドリフト領域１の比抵抗を小さくして動作
抵抗の低減化を図っても比較的高耐圧を得ることができ
る。即ち、ドリフト領域１の比抵抗を、浅いベース領域
を有する従来の標準的な構造のＦＥＴのドリフト領域の
比抵抗の１／３〜１／５に設定しても、空乏層の働きで
標準的な構造のＦＥＴと同等の耐圧を得ることができ
る。2. Description of the Related Art It is known that an insulated gate field effect transistor (hereinafter referred to as an FET) is constructed as shown in FIG. 1 for the purpose of achieving both a high operating resistance and a high breakdown voltage at a high level. It is. This FET includes a silicon semiconductor substrate 5 including an N-type drift region 1, an N + -type drain region 2, a plurality of P-type base regions 3, and a plurality of source regions 4, a drain electrode 6, a source electrode 7, and a gate. An electrode 8, a gate insulating film 9, a peripheral protective insulating film 10, and an interlayer insulating film 11 are provided. A base region 3 which can be called a body region or a channel formation region of this FET.
Has a peculiar shape, is formed deeply in a columnar shape in the thickness direction of the drift region 1, and its bottom surface reaches near the interface between the drift region 1 and the drain region 2. When the plurality of base regions 3 are formed in a columnar shape, when a high reverse voltage is applied to the PN junction between the base region 3 and the drift region 1, the drift region 1 between the plurality of base regions 3 is formed by the depletion layer. It is filled and the withstand voltage is improved. Further, in the case of the structure shown in FIG. 1, a relatively high breakdown voltage can be obtained even if the specific resistance of the drift region 1 is reduced to reduce the operating resistance. That is, even if the specific resistance of the drift region 1 is set to be 1/3 to 1/5 of the specific resistance of the drift region of the conventional FET having a standard structure having a shallow base region, the standard depletion layer works. Withstand voltage equivalent to an FET having a simple structure can be obtained.
【０００３】[0003]
【発明が解決しようとする課題】ところで、図１の絶縁
ゲート型ＦＥＴにおけるベース領域３は、周知のエピタ
キシャル成長と不純物拡散を複数回繰り返して形成され
る。即ち、ドレイン領域２の上に肉薄のＮ形エピタキシ
ャル層を形成し、このエピタキシャル層にＰ形不純物を
導入してベース領域３を構成するＰ形拡散領域を形成す
る。次に、このＮ形エピタキシャル層とＰ形拡散領域の
表面を被覆するように肉薄のＮ形エピタキシャル層を形
成し、先に形成した下側Ｐ形半導体領域と連続するよう
にＰ形不純物を導入してベース領域３を構成する上側Ｐ
形拡散領域を形成する。これを複数回繰り返すことによ
って、ベース領域３が柱状に素子の厚み方向に延びるよ
うに形成された図１の絶縁ゲート型電界効果トランジス
タが得られる。このようにエピタキシャル成長と不純物
拡散を複数回繰り返してベース領域３を形成した場合、
ベース領域３を構成するＰ形拡散領域は不純物拡散とエ
ピタキシャル成長等の熱処理によって横方向に広がって
しまう。ベース領域３の横方向広がりが大きいと、相対
的に柱状ベース領域３の間に形成されたドリフト領域１
の断面積が減少するため、動作抵抗の低減化効果が損な
われる。この問題を解決するためには、Ｐ形不純物の縦
方向の拡散距離が短くても上下のＰ形拡散領域が連続す
るように、Ｎ形エピタキシャル層を十分に薄く形成する
ことが考えられる。しかし、この製造方法は、エピタキ
シャル成長の工程数が増加してコストの増加等を招来す
るため、実用的とはいえない。The base region 3 in the insulated gate FET shown in FIG. 1 is formed by repeating well-known epitaxial growth and impurity diffusion a plurality of times. That is, a thin N-type epitaxial layer is formed on the drain region 2, and a P-type impurity is introduced into the epitaxial layer to form a P-type diffusion region constituting the base region 3. Next, a thin N-type epitaxial layer is formed so as to cover the surfaces of the N-type epitaxial layer and the P-type diffusion region, and a P-type impurity is introduced so as to be continuous with the previously formed lower P-type semiconductor region. To form the base region 3
A shaped diffusion region is formed. By repeating this plural times, the insulated gate field effect transistor of FIG. 1 in which the base region 3 is formed in a columnar shape and extends in the thickness direction of the element is obtained. When the base region 3 is formed by repeating epitaxial growth and impurity diffusion a plurality of times as described above,
The P-type diffusion region forming the base region 3 is expanded in the lateral direction by heat treatment such as impurity diffusion and epitaxial growth. If the lateral spread of the base region 3 is large, the drift region 1 formed between the columnar base regions 3 is relatively large.
, The effect of reducing the operating resistance is impaired. In order to solve this problem, it is conceivable to form the N-type epitaxial layer sufficiently thin so that the upper and lower P-type diffusion regions are continuous even if the vertical diffusion distance of the P-type impurity is short. However, this manufacturing method is not practical because the number of steps of epitaxial growth is increased and the cost is increased.
【０００４】そこで、本発明の目的は、動作抵抗の低減
化と高耐圧化とを高水準に達成でき、且つ生産性にも優
れている絶縁ゲート型ＦＥＴ及びその製造方法を提供す
ることにある。It is an object of the present invention to provide an insulated gate FET capable of achieving a high level of reduction in operating resistance and high withstand voltage and excellent in productivity, and a method of manufacturing the same. .
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、ドレイン領域とドリフ
ト領域と複数のベース領域と複数のソース領域とを有す
る半導体基体と、ゲート絶縁膜と、ベース制限用絶縁膜
と、ドレイン電極と、ソース電極と、ゲート電極とを備
え、前記ドリフト領域は前記ドレイン領域の不純物濃度
よりも低い不純物濃度を有し且つ前記半導体基体の一方
の主面に露出する部分を有するように配置され、前記ド
レイン領域は前記ドリフト領域と前記半導体基体の他方
の主面との間に配置され、前記複数のベース領域は前記
ドリフト領域の中に島状に分散配置され、且つ前記半導
体基体の主面に対して垂直方向に柱状に延びている第１
のベース領域と前記半導体基体の一方の主面において前
記ドリフト領域に囲まれ且つ前記第１のベース領域に隣
接している第２のベース領域とをそれぞれ有し、前記複
数のエミッタ領域は前記複数の第２のベース領域の中に
島状に配置され、前記第１のベース領域と前記ドリフト
領域との間にベース制限用絶縁膜が配置されていること
を特徴とする絶縁ゲート型電界効果トランジスタに係わ
るものである。SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a semiconductor substrate having a drain region, a drift region, a plurality of base regions and a plurality of source regions, A film, a base limiting insulating film, a drain electrode, a source electrode, and a gate electrode, wherein the drift region has an impurity concentration lower than an impurity concentration of the drain region, and one of the main parts of the semiconductor substrate. The drain region is disposed between the drift region and the other main surface of the semiconductor substrate, and the plurality of base regions are arranged in an island shape in the drift region. First distributed and arranged in a column shape in a direction perpendicular to a main surface of the semiconductor substrate;
And a second base region which is surrounded by the drift region on one main surface of the semiconductor substrate and is adjacent to the first base region. An insulated gate field effect transistor, which is disposed in an island shape in the second base region, and a base limiting insulating film is disposed between the first base region and the drift region. It is related to.
【０００６】なお、請求項２に示すように、第１導電形
の半導体基板を用意する工程と、前記半導体基板の不純
物濃度よりも低い不純物濃度を有する第１導電形の第１
の半導体層をエピタキシャル成長法で形成する工程と、
第２導電形の第２の半導体層を前記第１の半導体層の上
にエピタキシャル成長法で形成する工程と、エッチング
によって複数の柱状半導体層から成る第２のベース領域
を形成する工程と、前記第２のベース領域の側面に絶縁
膜を形成する工程と、前記第２のベース領域を埋設する
ように前記第１及び第２の半導体層の上に前記半導体基
板よりも低い不純物濃度を有する第１導電形の第３の半
導体層を形成する工程と、前記第３の半導体層の表面に
島状に配置され且つ前記第２のベース領域に接触してい
る第２導電形の第２のベース領域を形成する工程と、前
記第２のベース領域の中に第１導電形のソース領域を形
成する工程とを備えて絶縁ゲート型電界効果トランジス
タを製造することが望ましい。According to a second aspect of the present invention, there is provided a step of preparing a semiconductor substrate of the first conductivity type, and a step of preparing a semiconductor substrate of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate.
Forming a semiconductor layer by an epitaxial growth method;
Forming a second semiconductor layer of a second conductivity type on the first semiconductor layer by an epitaxial growth method, forming a second base region composed of a plurality of columnar semiconductor layers by etching, Forming an insulating film on the side surface of the second base region; and forming a first impurity concentration lower than the semiconductor substrate on the first and second semiconductor layers so as to bury the second base region. Forming a third semiconductor layer of the conductivity type; and a second base region of the second conductivity type arranged in an island shape on the surface of the third semiconductor layer and in contact with the second base region. And a step of forming a source region of the first conductivity type in the second base region, to manufacture an insulated gate field effect transistor.
【０００７】[0007]
【発明の効果】各請求項の発明によれば、柱状の第２の
ベース領域の側面が絶縁膜で囲まれているので、第２の
ベース領域の横方向への広がりが制限され、ドリフト領
域を十分に確保することができ、動作抵抗の低いＦＥＴ
を提供することができる。また、請求項２の発明によれ
ば、少ないエピタキシャル成長工程によって柱状の第２
のベース領域を生産性良く形成することができる。According to the present invention, since the side surface of the columnar second base region is surrounded by the insulating film, the lateral extension of the second base region is limited, and the drift region is formed. FET with a low operating resistance
Can be provided. Further, according to the second aspect of the present invention, the columnar second layer is formed by a small number of epitaxial growth steps.
Can be formed with high productivity.
【０００８】[0008]
【実施形態】次に、図２〜図５を参照して本発明の実施
形態を説明する。Next, an embodiment of the present invention will be described with reference to FIGS.
【０００９】図２及び図３に示す本発明の実施形態に従
う絶縁ゲート型電界効果トランジスタ（ＦＥＴ）は、図
１の従来のＦＥＴと同様にＮ形（第１導電形）ドリフト
領域１とＮ＋形ドレイン領域２とＰ形（第２導電形）ベ
ース領域３とＮ形ソース領域４とドレイン電極６とソー
ス電極７とゲート電極８とゲート絶縁膜９と層間絶縁膜
１１と図示されていない周辺絶縁膜とを有し、更に本発
明に従うベース制限用酸化膜１２を有する。なお、ベー
ス領域３は柱状の第１のベース領域３ａと表面側の浅い
第２のベース領域３ｂとを有する。An insulated gate field effect transistor (FET) according to the embodiment of the present invention shown in FIGS. 2 and 3 has an N-type (first conductivity type) drift region 1 and an N + like the conventional FET of FIG. Drain region 2, P-type (second conductivity type) base region 3, N-type source region 4, drain electrode 6, source electrode 7, gate electrode 8, gate insulating film 9, interlayer insulating film 11, and peripherals not shown. And a base limiting oxide film 12 according to the present invention. The base region 3 has a columnar first base region 3a and a shallow second base region 3b on the surface side.
【００１０】ドリフト領域１はシリコンから成るＮ形半
導体領域であって、Ｎ＋形ドレイン領域２よりも低い不
純物濃度を有する。ドリフト領域１はドレイン領域２と
同一導電形を有するので、これをドレイン領域と呼ぶこ
ともできる。なお、図２のドリフト領域１は図１のよう
にドレイン領域２の上にＮ形半導体を多層にエピタキシ
ャル成長させたものではなく、２回のエピタキシャル成
長で形成したものである。ドリフト領域１の一部は半導
体基体５の一方の主面に露出している。このドリフト領
域１の不純物濃度は、柱状の第１のベース領域３ａを形
成しない浅い第２のベース領域３ｂのみの構成の従来の
ＦＥＴのドリフト領域の不純物濃度よりは高い。従っ
て、ドリフト領域１の抵抗率は柱状ベース領域を有さな
い従来のＦＥＴのドリフト領域の抵抗率の１／５〜１／
３である。Drift region 1 is an N-type semiconductor region made of silicon, and has a lower impurity concentration than N + -type drain region 2. Since the drift region 1 has the same conductivity type as the drain region 2, it can be called a drain region. The drift region 1 in FIG. 2 is not formed by epitaxially growing an N-type semiconductor on the drain region 2 in multiple layers as in FIG. 1, but is formed by two epitaxial growths. Part of drift region 1 is exposed on one main surface of semiconductor substrate 5. The impurity concentration of the drift region 1 is higher than the impurity concentration of the drift region of the conventional FET having only the shallow second base region 3b without forming the columnar first base region 3a. Therefore, the resistivity of the drift region 1 is 1/5 to 1/1 / the resistivity of the drift region of the conventional FET having no columnar base region.
3.
【００１１】Ｎ＋形ドレイン領域２はドリフト領域１と
半導体基体５の他方の主面との間に配置されている。な
お、ドレイン領域２とドリフト領域１との境界面は平板
状半導体基体５の他方の主面に平行である。ドレイン電
極６は例えばアルミニウム蒸着層から成り、半導体基体
５の他方の主面においてドレイン領域２に接続されてい
る。The N + type drain region 2 is arranged between the drift region 1 and the other main surface of the semiconductor substrate 5. Note that the boundary surface between the drain region 2 and the drift region 1 is parallel to the other main surface of the planar semiconductor substrate 5. The drain electrode 6 is made of, for example, an aluminum deposition layer and is connected to the drain region 2 on the other main surface of the semiconductor substrate 5.
【００１２】ベース領域３は、ボデイ領域又はチャネル
形成領域とも呼ぶことができるものであって、前述した
ように第１及び第２のベース領域３ａ、３ｂを有する。
第１のベース領域３ａは、ドリフト領域１内にその上面
から下面に向って柱状に形成されている。第１のベース
領域３ａの上面は第２のベース領域３ｂの下面に連続し
ている。第１のベース領域３ａの下面はドレイン領域２
から若干離間するように配置されている。このように若
干離間するように配置することによって第１のベース領
域３ａの下側での電界集中を緩和できると考えられる。
図３に示すように、多数の第１のベース領域３ａは平面
的に見て半導体基体５内に島状に形成され且つ均一に分
散配置されており、各々の第１のベース領域３ａは四角
形状の平面形状を有する。なお、第１のベース領域３ａ
の平面形状は四角形に限られず、円形にしてもよい。こ
の第１のベース領域３ａは、厚いエピタキシャル層をエ
ッチングすることによって形成したものであり、側面に
凹凸を有さない。第２のベース領域３ｂは、ドリフト領
域１の表面側に形成されており、その上面は半導体基体
５の一方の主面に露出しており、下面は第１のベース領
域３ａの上面に隣接している。第２のベース領域３ｂは
平面的に見て、第１のベース領域３ａに対応するように
半導体基体５内に島状（アイランド状）に形成され且つ
均一に分散配置されている。各々の第２のベース領域３
ｂの平面形状は四角形である。なお、第２のベース領域
３ｂの平面形状は四角形に限られず、円形等にしてもよ
い。第２のベース領域３ｂはドリフト領域１内に半導体
基体５の一方の主面から不純物を拡散することによって
形成されたものであり、平面的に見てその外周側は第１
のベース領域３ａよりも外側に広がっている。この第２
のベース領域３ｂは、その表面側においてソース領域４
とドリフト領域１との間にチャネルを形成するので、チ
ャネル形成領域と呼ぶこともできる。The base region 3 can be called a body region or a channel forming region, and has the first and second base regions 3a and 3b as described above.
The first base region 3a is formed in the drift region 1 in a column shape from the upper surface to the lower surface. The upper surface of the first base region 3a is continuous with the lower surface of the second base region 3b. The lower surface of the first base region 3a is the drain region 2
It is arranged so as to be slightly apart from. It is considered that the electric field concentration below the first base region 3a can be reduced by arranging them slightly apart in this manner.
As shown in FIG. 3, a large number of first base regions 3a are formed in an island shape in a semiconductor substrate 5 and are uniformly dispersed in a plan view, and each first base region 3a has a square shape. It has a planar shape. Note that the first base region 3a
Is not limited to a square, but may be a circle. The first base region 3a is formed by etching a thick epitaxial layer, and has no side surface irregularities. The second base region 3b is formed on the surface side of the drift region 1, the upper surface is exposed on one main surface of the semiconductor substrate 5, and the lower surface is adjacent to the upper surface of the first base region 3a. ing. The second base region 3b is formed in an island shape (island shape) in the semiconductor substrate 5 so as to correspond to the first base region 3a in a plan view, and is uniformly dispersed. Each second base region 3
The plane shape of b is a quadrangle. The planar shape of the second base region 3b is not limited to a quadrangle but may be a circle or the like. The second base region 3b is formed by diffusing an impurity from the one main surface of the semiconductor substrate 5 into the drift region 1 and its outer peripheral side in plan view is the first base region 3b.
Of the base region 3a. This second
Of the source region 4b on the surface side of the base region 3b.
Since a channel is formed between the semiconductor device and the drift region 1, the channel can be referred to as a channel forming region.
【００１３】Ｎ形ソース領域４は各第２のベース領域３
ｂの中に島状に形成され、半導体基体５の一方の主面に
露出している。図３ではソース領域４が環状の平面形状
を有するが、例えば特願平１１−８４５３７号に示され
ているように多数のソース領域４の群の周辺領域におい
てソース領域４をコ字状又はＬ字状の平面形状にするこ
とができる。An N-type source region 4 is provided for each second base region 3.
b is formed in an island shape and is exposed on one main surface of the semiconductor substrate 5. In FIG. 3, the source region 4 has an annular planar shape. For example, as shown in Japanese Patent Application No. 11-84537, the source region 4 is formed into a U-shape or L-shape in a peripheral region of a group of many source regions 4. It can be shaped like a letter.
【００１４】ソース電極７は、例えばアルミニウムの蒸
着層であって、各ソース領域４と各第２のベース領域３
ｂとの両方に接続され、複数のソース領域４を共通接続
するように層間絶縁膜１１の上にも設けられている。The source electrode 7 is, for example, a deposited layer of aluminum, and is formed of each source region 4 and each second base region 3.
b, and is also provided on the interlayer insulating film 11 so as to connect the plurality of source regions 4 in common.
【００１５】ゲート絶縁膜９は少なくとも第２のベース
領域３ｂにおける前述したチャネル形成部分を覆うよう
に形成されたシリコン酸化膜から成る。The gate insulating film 9 is made of a silicon oxide film formed so as to cover at least the above-mentioned channel forming portion in the second base region 3b.
【００１６】ゲート電極８は、例えば周知の化学的気相
成長法で形成された多結晶シリコンから成り、ゲート絶
縁膜９の上に形成されている。このゲート電極８は平面
的に見て格子状に形成され、図示されていない金属製ゲ
ート端子に接続されている。The gate electrode 8 is made of, for example, polycrystalline silicon formed by a known chemical vapor deposition method, and is formed on the gate insulating film 9. The gate electrode 8 is formed in a lattice shape when viewed in plan, and is connected to a metal gate terminal (not shown).
【００１７】本発明に従う柱状の第１のベース領域３ａ
とドリフト領域１との間に配置されたベース制限用絶縁
膜としての酸化膜１２はシリコン酸化膜から成り、第１
のベース領域３ａの横方向への広がりを制限している。First pillar-shaped base region 3a according to the present invention
Oxide film 12 serving as a base-limiting insulating film disposed between semiconductor device 1 and drift region 1 is made of a silicon oxide film.
Of the base region 3a in the horizontal direction is restricted.
【００１８】次に、図４及び図５を参照して図２のＦＥ
Ｔの製造方法を説明する。図２の絶縁ゲート型ＦＥＴを
製造する時には、まず図４（Ａ）に示すＮ＋形半導体基
板２ａを用意する。このＮ＋形半導体基板２ａは、図２
の絶縁ゲート型ＦＥＴのドレイン領域２を構成するもの
である。Next, referring to FIGS. 4 and 5, the FE of FIG.
A method for manufacturing T will be described. When manufacturing the insulated gate FET of FIG. 2, first, an N + type semiconductor substrate 2a shown in FIG. 4A is prepared. This N + type semiconductor substrate 2a is formed as shown in FIG.
Of the insulated gate type FET.
【００１９】次に、図４（Ｂ）に示すように、このＮ＋
形半導体基板２ａの上面にＮ形の第１の半導体層１ａを
周知のエピタキシャル成長方法によって形成する。この
第１の半導体層１ａは、図２の絶縁ゲート型ＦＥＴのド
リフト領域１の一部を構成するものである。更に、この
第１の半導体層１ａの上面にＰ形の第２の半導体層２１
を周知のエピタキシャル成長方法によって形成する。こ
のＰ形の第２の半導体層２１は、図２の絶縁ゲート型Ｆ
ＥＴの第１のベース領域３ａを構成するものである。Next, as shown in FIG. 4B, the N +
An N-type first semiconductor layer 1a is formed on the upper surface of a semiconductor substrate 2a by a well-known epitaxial growth method. The first semiconductor layer 1a forms a part of the drift region 1 of the insulated gate FET of FIG. Further, a P-type second semiconductor layer 21 is formed on the upper surface of the first semiconductor layer 1a.
Is formed by a well-known epitaxial growth method. The P-type second semiconductor layer 21 is formed of the insulated gate type F of FIG.
This constitutes a first base region 3a of the ET.
【００２０】次に、図４（Ｃ）に示すように、このＰ形
の第２の半導体層２１に異方性エッチングを施して、図
示のようにＰ形半導体領域を柱状に残存させて図２の絶
縁ゲート型ＦＥＴの第１のベース領域３ａを形成する。
この第１のベース領域３ａはＮ形の第１の半導体層１ａ
の上面にほぼ垂直に設けられている。更に、この第１の
ベース領域３ａとＮ形の第１の半導体層１ａの上面にシ
リコン酸化膜１２を形成する。酸化膜１２は、周知の熱
酸化方法によって形成することができる。Next, as shown in FIG. 4C, the P-type second semiconductor layer 21 is subjected to anisotropic etching to leave the P-type semiconductor region in a columnar shape as shown in FIG. The first base region 3a of the second insulated gate FET is formed.
The first base region 3a is an N-type first semiconductor layer 1a.
Are provided substantially vertically on the upper surface of the. Further, a silicon oxide film 12 is formed on the upper surfaces of the first base region 3a and the N-type first semiconductor layer 1a. The oxide film 12 can be formed by a known thermal oxidation method.
【００２１】次に、図５（Ａ）に示すように、異方性エ
ッチングによって第１のベース領域３ａの側面のみに酸
化膜１２を残存させて、第１のベース領域３ａとＮ形の
第１の半導体層１ａの上面に形成された酸化膜をエッチ
ング除去する。更に、第１の半導体層１ａの上面にＮ形
の第３の半導体層１ｂを周知のエピタキシャル成長方法
によって形成する。このＮ形の第３の半導体層１ｂは第
１の半導体層１ａと共に図２の絶縁ゲート型ＦＥＴのド
リフト領域１を構成するものである。第３の半導体層１
ｂは、第１のベース領域３ａの上面も被覆しており、第
１のベース領域３ａの上面側に第２のベース領域３ｂを
形成することができる厚みを有している。Next, as shown in FIG. 5A, the oxide film 12 is left only on the side surface of the first base region 3a by anisotropic etching, and the first base region 3a and the N-type The oxide film formed on the upper surface of the first semiconductor layer 1a is removed by etching. Further, an N-type third semiconductor layer 1b is formed on the upper surface of the first semiconductor layer 1a by a known epitaxial growth method. This N-type third semiconductor layer 1b constitutes the drift region 1 of the insulated gate FET of FIG. 2 together with the first semiconductor layer 1a. Third semiconductor layer 1
b also covers the upper surface of the first base region 3a, and has a thickness such that the second base region 3b can be formed on the upper surface side of the first base region 3a.
【００２２】次に、この第３の半導体領域１ｂに周知の
２重拡散技術によって、Ｐ形不純物とＮ形不純物を順次
導入して、図５（Ｂ）に示すように第２のベース領域３
ｂとソース領域４を形成する。これにより、図２と同様
にドリフト領域１、ドレイン領域２、第１及び第２のベ
ース領域３ａ、３ｂ、及びソース領域４を有する半導体
基体５が得られる。Next, a P-type impurity and an N-type impurity are successively introduced into the third semiconductor region 1b by a well-known double diffusion technique, so that the second base region 3 is formed as shown in FIG.
b and the source region 4 are formed. Thus, a semiconductor substrate 5 having the drift region 1, the drain region 2, the first and second base regions 3a and 3b, and the source region 4 is obtained as in FIG.
【００２３】その後、従来の絶縁ゲート型ＦＥＴの製造
方法と同様にして、図２に示すゲート絶縁膜９、ゲート
電極８、ソース電極７、ドレイン電極６等を形成して図
２の絶縁ゲート型ＦＥＴを完成させる。Thereafter, a gate insulating film 9, a gate electrode 8, a source electrode 7, a drain electrode 6, and the like shown in FIG. 2 are formed in the same manner as in the conventional method of manufacturing an insulated gate FET. Complete the FET.
【００２４】本実施形態の絶縁ゲート型ＦＥＴによれ
ば、第２のベース領域３ａを構成する柱状のＰ形半導体
層が筒状の酸化膜１２によって包囲されており、第２の
ベース領域３ａの断面積がこの酸化膜１２によって制限
され、熱処理等によってその断面積が増加することが防
止されている。即ち、柱状の第２のベース領域３ａを構
成するＰ形半導体層がその後のエピタキシャル成長等の
熱処理によって横方向に広がってしまうことがなく、柱
状の第２のベース領域３ａの間に形成されたドリフト領
域１の断面積が所望に確保される。従って、動作抵抗の
低減化が高水準に達成される。また、酸化膜１２は５０
０〜１０００オングストローム程度の薄い絶縁膜である
から、ベース領域３とドリフト領域１との間に逆方向の
バイアスが印加されると、この界面から空乏層が良好に
広がってベース領域の間のドリフト領域１を埋め、電界
集中を良好に緩和することができる。このため、耐圧向
上効果も高水準に達成される。更に、本実施例の絶縁ゲ
ート型ＦＥＴによれば、柱状の第２のベース領域３ａを
従来例のように多数のエピタキシャル成長方法と拡散を
繰り返して形成する必要がないので、ＦＥＴの生産性を
高めることができる。According to the insulated gate FET of the present embodiment, the columnar P-type semiconductor layer constituting the second base region 3a is surrounded by the cylindrical oxide film 12, and the second base region 3a The cross-sectional area is limited by the oxide film 12, and the cross-sectional area is prevented from increasing due to heat treatment or the like. That is, the P-type semiconductor layer forming the columnar second base region 3a does not spread in the lateral direction due to the subsequent heat treatment such as epitaxial growth, and the drift formed between the columnar second base regions 3a. The cross-sectional area of the region 1 is secured as desired. Therefore, a reduction in operating resistance is achieved at a high level. The oxide film 12 has a thickness of 50
Since a thin insulating film of about 0 to 1000 angstroms is applied, when a reverse bias is applied between the base region 3 and the drift region 1, the depletion layer spreads favorably from this interface and the drift between the base region The region 1 is buried, and the electric field concentration can be favorably reduced. For this reason, the withstand voltage improvement effect is also achieved at a high level. Furthermore, according to the insulated gate type FET of this embodiment, it is not necessary to form the column-shaped second base region 3a by repeating a number of epitaxial growth methods and diffusion as in the conventional example, so that the productivity of the FET is improved. be able to.
【００２５】[0025]
【変形例】本発明は上述の実施形態に限定されるもので
なく、例えば次の変形が可能なものである。 （１） 柱状ベース領域３の平面形状を島状の他に、ス
トライプ状、格子状、ハニカム形状等の種々の形状にす
ることが可能である。 （２） ドレイン電極６もソース電極７と同様に素子の
一方の主面に形成し、ラテラル構造の絶縁ゲート型電界
効果トランジスタとしても良い。 （３） 実施形態の半導体基体５の各領域はシリコンか
ら成るが、シリコン以外の半導体とすることもできる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In addition to the island shape, the columnar base region 3 can have various shapes such as a stripe shape, a lattice shape, a honeycomb shape and the like in addition to the island shape. (2) Similarly to the source electrode 7, the drain electrode 6 may be formed on one main surface of the element to form a laterally-structured insulated gate field effect transistor. (3) Each region of the semiconductor substrate 5 of the embodiment is made of silicon, but may be a semiconductor other than silicon.
【図１】従来のＦＥＴを示す断面図である。FIG. 1 is a sectional view showing a conventional FET.
【図２】本発明の実施形態に従うＦＥＴを示す断面図で
ある。FIG. 2 is a cross-sectional view illustrating an FET according to an embodiment of the present invention.
【図３】図２の半導体基体の表面を示す平面図である。FIG. 3 is a plan view showing the surface of the semiconductor substrate of FIG. 2;
【図４】図２のＦＥＴの製造工程を説明するための断面
図である。FIG. 4 is a cross-sectional view for explaining a manufacturing process of the FET of FIG. 2;
【図５】図４に続く製造工程を説明するための断面図で
ある。FIG. 5 is a cross-sectional view for explaining a manufacturing step following FIG. 4;
１ ドリフト領域 ２ ドレイン領域 ３ ベース領域 ３ａ、３ｂ 第１及び第２のベース領域 ４ ソース領域 ５ 半導体基体 １２ 酸化膜 Reference Signs List 1 drift region 2 drain region 3 base region 3a, 3b first and second base regions 4 source region 5 semiconductor substrate 12 oxide film
Claims (2)
ース領域と複数のソース領域とを有する半導体基体と、
ゲート絶縁膜と、ベース制限用絶縁膜と、ドレイン電極
と、ソース電極と、ゲート電極とを備え、 前記ドリフト領域は前記ドレイン領域の不純物濃度より
も低い不純物濃度を有し且つ前記半導体基体の一方の主
面に露出する部分を有するように配置され、 前記ドレイン領域は前記ドリフト領域と前記半導体基体
の他方の主面との間に配置され、 前記複数のベース領域は前記ドリフト領域の中に島状に
分散配置され、且つ前記半導体基体の主面に対して垂直
方向に柱状に延びている第１のベース領域と前記半導体
基体の一方の主面において前記ドリフト領域に囲まれ且
つ前記第１のベース領域に隣接している第２のベース領
域とをそれぞれ有し、 前記複数のエミッタ領域は前記複数の第２のベース領域
の中に島状に配置され、 前記第１のベース領域と前記ドリフト領域との間にベー
ス制限用絶縁膜が配置されていることを特徴とする絶縁
ゲート型電界効果トランジスタ。A semiconductor substrate having a drain region, a drift region, a plurality of base regions, and a plurality of source regions;
A gate insulating film, a base limiting insulating film, a drain electrode, a source electrode, and a gate electrode, wherein the drift region has an impurity concentration lower than an impurity concentration of the drain region; The drain region is disposed between the drift region and the other main surface of the semiconductor substrate; and the plurality of base regions are islands in the drift region. A first base region extending in a columnar shape in a direction perpendicular to the main surface of the semiconductor substrate, and a first base region surrounded by the drift region on one main surface of the semiconductor substrate; A second base region adjacent to the base region, wherein the plurality of emitter regions are arranged in an island shape in the plurality of second base regions; Insulated gate field effect transistor, wherein a base limit for the insulating film is disposed between the source region and the drift region.
と、 前記半導体基板の不純物濃度よりも低い不純物濃度を有
する第１導電形の第１の半導体層をエピタキシャル成長
法で形成する工程と、 第２導電形の第２の半導体層を前記第１の半導体層の上
にエピタキシャル成長法で形成する工程と、 エッチングによって複数の柱状半導体層から成る第２の
ベース領域を形成する工程と、 前記第２のベース領域の側面に絶縁膜を形成する工程
と、 前記第２のベース領域を埋設するように前記第１及び第
２の半導体層の上に前記半導体基板よりも低い不純物濃
度を有する第１導電形の第３の半導体層を形成する工程
と、 前記第３の半導体層の表面に島状に配置され且つ前記第
２のベース領域に接触している第２導電形の第２のベー
ス領域を形成する工程と、 前記第２のベース領域の中に第１導電形のソース領域を
形成する工程とを備えていることを特徴とする絶縁ゲー
ト型電界効果トランジスタの製造方法。A step of preparing a semiconductor substrate of a first conductivity type; and a step of forming a first semiconductor layer of a first conductivity type having an impurity concentration lower than an impurity concentration of the semiconductor substrate by an epitaxial growth method. Forming a second semiconductor layer of a second conductivity type on the first semiconductor layer by an epitaxial growth method; forming a second base region including a plurality of columnar semiconductor layers by etching; Forming an insulating film on the side surface of the second base region; and forming a first impurity concentration lower than the semiconductor substrate on the first and second semiconductor layers so as to bury the second base region. Forming a third semiconductor layer of a conductivity type; and a second base region of a second conductivity type arranged in an island shape on the surface of the third semiconductor layer and in contact with the second base region. Form And a step of forming a source region of the first conductivity type in the second base region. A method of manufacturing an insulated gate field effect transistor, comprising:
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|---|---|---|---|
| JP2000390141A JP3551251B2 (en) | 2000-12-22 | 2000-12-22 | Insulated gate field effect transistor and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000390141A JP3551251B2 (en) | 2000-12-22 | 2000-12-22 | Insulated gate field effect transistor and method of manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| JP2002190593A true JP2002190593A (en) | 2002-07-05 |
| JP3551251B2 JP3551251B2 (en) | 2004-08-04 |
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|---|---|---|---|
| JP2000390141A Expired - Fee Related JP3551251B2 (en) | 2000-12-22 | 2000-12-22 | Insulated gate field effect transistor and method of manufacturing the same |
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| JP (1) | JP3551251B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007189192A (en) * | 2005-12-15 | 2007-07-26 | Toshiba Corp | Semiconductor device |
| JP2015039010A (en) * | 2009-08-27 | 2015-02-26 | ビシェイ−シリコニクス | Super junction trench power mosfet device and manufacturing method therefor |
| US9443974B2 (en) | 2009-08-27 | 2016-09-13 | Vishay-Siliconix | Super junction trench power MOSFET device fabrication |
| US9761696B2 (en) | 2007-04-03 | 2017-09-12 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| CN109378343A (en) * | 2018-11-12 | 2019-02-22 | 深圳市富裕泰贸易有限公司 | Super-junction metal oxide field effect transistor and preparation method thereof |
| US10234486B2 (en) | 2014-08-19 | 2019-03-19 | Vishay/Siliconix | Vertical sense devices in vertical trench MOSFET |
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2000
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007189192A (en) * | 2005-12-15 | 2007-07-26 | Toshiba Corp | Semiconductor device |
| US9947770B2 (en) | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
| US9761696B2 (en) | 2007-04-03 | 2017-09-12 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
| US9443974B2 (en) | 2009-08-27 | 2016-09-13 | Vishay-Siliconix | Super junction trench power MOSFET device fabrication |
| JP2015039010A (en) * | 2009-08-27 | 2015-02-26 | ビシェイ−シリコニクス | Super junction trench power mosfet device and manufacturing method therefor |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| US10283587B2 (en) | 2014-06-23 | 2019-05-07 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| US10234486B2 (en) | 2014-08-19 | 2019-03-19 | Vishay/Siliconix | Vertical sense devices in vertical trench MOSFET |
| US10340377B2 (en) | 2014-08-19 | 2019-07-02 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| US10444262B2 (en) | 2014-08-19 | 2019-10-15 | Vishay-Siliconix | Vertical sense devices in vertical trench MOSFET |
| US10527654B2 (en) | 2014-08-19 | 2020-01-07 | Vishay SIliconix, LLC | Vertical sense devices in vertical trench MOSFET |
| CN109378343A (en) * | 2018-11-12 | 2019-02-22 | 深圳市富裕泰贸易有限公司 | Super-junction metal oxide field effect transistor and preparation method thereof |
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| Publication number | Publication date |
|---|---|
| JP3551251B2 (en) | 2004-08-04 |
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