JP3221489B2 - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JP3221489B2 JP3221489B2 JP08453799A JP8453799A JP3221489B2 JP 3221489 B2 JP3221489 B2 JP 3221489B2 JP 08453799 A JP08453799 A JP 08453799A JP 8453799 A JP8453799 A JP 8453799A JP 3221489 B2 JP3221489 B2 JP 3221489B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- regions
- base
- semiconductor substrate
- drift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 63
- 230000015556 catabolic process Effects 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 41
- 230000002093 peripheral effect Effects 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 11
- 230000012010 growth Effects 0.000 claims description 10
- 230000006872 improvement Effects 0.000 claims description 8
- 230000002708 enhancing effect Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 description 31
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高耐圧化を達成す
ることができる絶縁ゲート型電界効果トランジスタに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor capable of achieving a high breakdown voltage.
【０００２】[0002]
【従来の技術】動作抵抗の低減化と高耐圧化の両方を高
水準に達成することを目的として絶縁ゲート型電界効果
トランジスタ（以下ＦＥＴと言う）を図１に示すように
構成することは公知である。このＦＥＴは、Ｎ型ドリフ
ト領域１とＮ+ 型ドレイン領域２と複数のＰ型ベース領
域３と複数のソース領域４とから成るシリコン半導体基
体５と、ドレイン電極６と、ソース電極７と、ゲート電
極８と、ゲート絶縁膜９と、周辺保護絶縁膜１０と、層
間絶縁膜１１とを備えている。このＦＥＴのボデイ領域
又はチャネル形成領域と呼ぶことのできるベース領域３
は特異な形状を有し、ドリフト領域１の厚み方向に深く
柱状に形成されており、その底面はドリフト領域１とド
レイン領域２との界面近くまで達している。複数のベー
ス領域３を柱状に形成すると、ベース領域３とドリフト
領域１との間のＰＮ接合に高い逆方向電圧が印加された
時に複数のベース領域３の相互間のドリフト領域１が空
乏層によって埋められ、耐圧が向上する。また、図１の
構造の場合、ドリフト領域１の比抵抗を小さくして動作
抵抗の低減化を図っても比較的高耐圧を得ることができ
る。即ち、ドリフト領域１の比抵抗を、浅いベース領域
を有する従来の標準的な構造のＦＥＴのドリフト領域の
比抵抗の１／３〜１／５に設定しても、空乏層の働きで
標準的な構造のＦＥＴと同等の耐圧を得ることができ
る。2. Description of the Related Art It is known that an insulated gate field effect transistor (hereinafter referred to as an FET) is constructed as shown in FIG. 1 for the purpose of achieving both a high operating resistance and a high breakdown voltage at a high level. It is. This FET includes a silicon semiconductor substrate 5 including an N-type drift region 1, an N + -type drain region 2, a plurality of P-type base regions 3, and a plurality of source regions 4, a drain electrode 6, a source electrode 7, and a gate. An electrode 8, a gate insulating film 9, a peripheral protective insulating film 10, and an interlayer insulating film 11 are provided. A base region 3 which can be called a body region or a channel formation region of this FET.
Has a peculiar shape, is formed deeply in a columnar shape in the thickness direction of the drift region 1, and its bottom surface reaches near the interface between the drift region 1 and the drain region 2. When the plurality of base regions 3 are formed in a columnar shape, when a high reverse voltage is applied to the PN junction between the base region 3 and the drift region 1, the drift region 1 between the plurality of base regions 3 is formed by the depletion layer. It is filled and the withstand voltage is improved. Further, in the case of the structure shown in FIG. 1, a relatively high breakdown voltage can be obtained even if the specific resistance of the drift region 1 is reduced to reduce the operating resistance. That is, even if the specific resistance of the drift region 1 is set to be 1/3 to 1/5 of the specific resistance of the drift region of the conventional FET having a standard structure having a shallow base region, the standard depletion layer works. Withstand voltage equivalent to an FET having a simple structure can be obtained.
【０００３】[0003]
【発明が解決しょうとする課題】ところで、従来のこの
種のＦＥＴでは、素子の外周縁側の耐圧向上に関しての
改善が十分になされていない。このため、期待されるほ
ど高耐圧化が図れないのが実情であった。即ち、上記の
ようにベース領域３をドリフト領域１の厚み方向に深く
拡散して素子中央側（素子活性領域）の耐圧向上を図っ
ても、素子周縁側の耐圧も同様に向上しなければ素子全
体としての向上耐圧は達成されない。そこで、本願発明
者は、主接合即ち素子活性領域の外周側を包囲するよう
に周知のフィールドリミッティングリング（ＦＬＲ）を
形成して、素子周縁側の耐圧向上を図ることを試みた。
しかしながら、上記構造のＦＥＴではドリフト領域１の
比抵抗が通常のＦＥＴに比べてかなり小さくなっている
ため、従来のＦＬＲ構造では、耐圧向上を図ることがで
きなかった。However, in this type of conventional FET, improvement in withstand voltage on the outer peripheral side of the element has not been sufficiently improved. For this reason, it was a fact that the withstand voltage could not be increased as expected. That is, even if the base region 3 is deeply diffused in the thickness direction of the drift region 1 to improve the breakdown voltage on the device center side (device active region) as described above, if the breakdown voltage on the device peripheral side is not improved as well, No improved breakdown voltage is achieved as a whole. Therefore, the inventor of the present application has attempted to improve the breakdown voltage on the element peripheral side by forming a well-known field limiting ring (FLR) so as to surround the main junction, that is, the outer peripheral side of the element active region.
However, in the FET having the above-described structure, the resistivity of the drift region 1 is considerably smaller than that of a normal FET. Therefore, the withstand voltage cannot be improved in the conventional FLR structure.
【０００４】そこで、本発明の目的は、動作抵抗の低減
と耐圧向上とのいずれか一方又は両方を容易且つ良好に
達成することができる絶縁ゲート型電界効果トランジス
タを提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide an insulated gate field effect transistor which can easily and satisfactorily achieve one or both of a reduction in operating resistance and an improvement in withstand voltage.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための発明は、ドレイン領域とドリフト
領域と複数のベース領域と複数のソース領域と複数の耐
圧向上用領域と補助領域とを有する半導体基体と、ゲー
ト絶縁膜と、ドレイン電極と、ソース電極と、ゲート電
極とを備え、前記ドリフト領域は、前記ドレイン領域の
不純物濃度よりも低い不純物濃度を有し且つ前記半導体
基体の一方の主面に露出する部分を有するように配置さ
れ且つ前記ドレイン領域の上に前記ドレイン領域と同一
の導電型の複数のエピタキシャル成長層を設けたものか
ら成り、 前記ドレイン領域は前記ドリフト領域と前記
半導体基体の他方の主面との間に配置され、前記複数の
ベース領域のそれぞれは、前記ドリフト領域と反対の導
電型を有し且つ前記ドリフト領域の中に島状に分散配置
され且つ前記半導体基体の一方の主面から他方の主面に
向って柱状に延びており且つ前記ドリフト領域を形成す
る前記複数のエピタキシャル成長層に拡散で形成された
領域から成り、前記複数のソース領域のそれぞれは前記
ベース領域と反対の導電型を有し且つ前記複数のベース
領域の中に島状に配置され、前記複数の耐圧向上用領域
のそれぞれは、前記ベース領域と同一の導電型を有して
前記ドリフト領域の中に島状に形成され且つ平面的に見
て前記ベース領域の外側に分散配置され且つ前記半導体
基体の一方の主面から他方の主面に向って柱状に延びて
おり且つ前記ドリフト領域を形成する前記複数のエピタ
キシャル成長層に拡散で形成された領域から成り且つ前
記ベース領域と同じ深さを有し、前記補助領域は前記ド
リフト領域における空乏層の広がりを補助するためのも
のであって、前記耐圧向上用領域と同一の導電型を有し
且つ前記半導体基体の表面に露出するように前記ドリフ
ト領域の中に形成され且つ前記耐圧向上用領域よりも浅
く形成され且つ平面的に見て前記複数の耐圧向上用領域
の外周側を囲むように環状に形成され且つ前記複数の耐
圧向上用領域に接触している領域から成り、前記ドレイ
ン電極と前記ソース電極との間に電圧が印加された時
に、前記複数のベース領域、前記複数の耐圧向上用領
域、及び前記補助領域に隣接している前記ドリフト領域
のそれぞれの部分に生じる空乏層が互いに連続するよう
に前記複数のベース領域と前記複数の耐圧向上用領域と
前記補助領域とが配置されていることを特徴とする絶縁
ゲート型電界効果トランジスタに係わるものである。SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a drain region, a drift region, a plurality of base regions, a plurality of source regions, a plurality of breakdown voltage improving regions, and an auxiliary region. A semiconductor substrate having a gate insulating film, a drain electrode, a source electrode, and a gate electrode, wherein the drift region has an impurity concentration lower than that of the drain region and The drain region is arranged so as to have a portion exposed on one main surface and is the same as the drain region on the drain region.
With multiple epitaxial growth layers of the same conductivity type
Et made, the drain region is disposed between the other main surface of the semiconductor substrate and the drift region, each of said plurality of base regions, the opposite guiding said drift region
Having an electric pattern and distributed in an island shape in the drift region
And from one main surface of the semiconductor substrate to the other main surface.
Extending in a columnar shape and forming the drift region.
Formed in the plurality of epitaxial growth layers by diffusion.
Consists regions, wherein each of said plurality of source regions
The base region has a conductivity type opposite to that of the base region, and is arranged in an island shape in the plurality of base regions. Each of the plurality of breakdown voltage improving regions has the same conductivity type as the base region, and It is distributed on the outside of the base region look and is formed in an island shape in a plan view in the region and the semiconductor
A column extending from one main surface of the base toward the other main surface
The plurality of epilators forming the drift region
And consist region formed by diffusing the Kisharu growth layer has the same depth as the base region, the auxiliary area the de
It is for assisting the expansion of the depletion layer in the lift region , has the same conductivity type as the breakdown voltage improving region, and is formed in the drift region so as to be exposed on the surface of the semiconductor substrate; The plurality of withstand voltage improving regions are formed shallower than the withstand voltage improving regions and viewed in plan.
Is formed in an annular shape so as to surround the outer peripheral side of the
The area in contact with the pressure-improving area,
When a voltage is applied between the source electrode and the source electrode
The plurality of base regions and the plurality of withstand voltage improving regions.
Region and the drift region adjacent to the auxiliary region
So that the depletion layers that occur in each part of
The plurality of base regions and the plurality of breakdown voltage improving regions
The present invention relates to an insulated gate field effect transistor, wherein the auxiliary region is disposed .
【０００６】なお、請求項２〜６に示すように構成する
こたもできる。また、請求項６に示すように、フィール
ドプレート又は等電位リング（ＥＱＲ）を形成すること
が望ましい。It is to be noted that the present invention is configured as described in claims 2 to 6.
I can do it. Further, as shown in claim 6, it is desirable to form a field plate or equipotential ring (EQR).
【０００７】[0007]
【発明の効果】各請求項の発明によればＦＥＴ素子の周
辺耐圧を容易且つ良好に向上させることができる。即
ち、ベース領域の外周側にベース領域と同一の深さの耐
圧向上用領域を設け、更に耐圧向上用領域よりも浅い補
助領域を設けたので, ＦＥＴ素子の外周側に空乏層を良
好に広げることができ、素子周辺耐圧が良好に向上す
る。また、請求項６に示すようにフィールドプレートと
等電位リング（ＥＱＲ）とのいずれか一方又は両方を設
けると、空乏層の広がりが更に良好になる。According to the present invention, the peripheral breakdown voltage of the FET element can be easily and satisfactorily improved. That is, a withstand voltage improving region having the same depth as the base region is provided on the outer peripheral side of the base region, and an auxiliary region which is shallower than the withstand voltage improving region is provided. Therefore, the withstand voltage around the element is improved favorably. Also, providing either or both the field plate and the equipotential ring as shown in claim 6 (EQR), spread of the depletion layer is further improved.
【０００８】[0008]
【実施形態及び実施例】次に、図２〜図７を参照して本
発明の実施形態及び実施例を説明する。Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.
【０００９】[0009]
【第１の実施例】図２及び図３に示す第１の実施例の絶
縁ゲート型電界効果トランジスタ（ＦＥＴ）は、図１の
従来のＦＥＴと同様にＮ型（第１導電型）ドリフト領域
１とＮ+型ドレイン領域２とＰ型（第２導電型）ベース
領域３とＮ型ソース領域４とドレイン電極６とソース電
極７とゲート電極８とゲート絶縁膜９と周辺保護絶縁膜
１０と層間絶縁膜１１とを有する他に、シリコン半導体
基体５ａの中に設けられた柱状のＰ型耐圧向上用領域１
２及びＰ型の補助領域１３と、周辺絶縁膜１０の中に設
けたフィールドプレート１４及び等電位リング即ちＥＱ
Ｒ１５とを有し、図２のＡ−Ａ線及びＢ−Ｂ線を中心に
上下及び左右対称に形成されている。なお、図３は図２
の耐圧向上用領域１２及び補助領域１３の数を減らして
図２の一部を示すものである。 First Embodiment An insulated gate field effect transistor (FET) of a first embodiment shown in FIGS. 2 and 3 has an N-type (first conductivity type) drift region like the conventional FET of FIG. 1, an N + type drain region 2, a P type (second conductivity type) base region 3, an N type source region 4, a drain electrode 6, a source electrode 7, a gate electrode 8, a gate insulating film 9, a peripheral protective insulating film 10, In addition to having the interlayer insulating film 11, a columnar P-type breakdown voltage improving region 1 provided in the silicon semiconductor substrate 5a
2 and P type auxiliary regions 13, a field plate 14 provided in the peripheral insulating film 10, and an equipotential ring, ie, EQ.
R15 and are formed vertically and horizontally symmetrically with respect to the lines AA and BB in FIG. Note that FIG.
The number of the withstand voltage improving regions 12 and the auxiliary regions 13
3 shows a part of FIG. 2.
【００１０】ドリフト領域１はＮ型半導体領域であって
Ｎ+ 型ドレイン領域２よりも低い不純物濃度を有する。
なお、ドリフト領域１はドレイン領域２と同一導電型を
有するので、これをドレイン領域と呼ぶこともできる。
ドリフト領域１はドレイン領域２の上にＮ型半導体を多
層にエピタキシャル成長させたものから成り、その一部
は半導体基体５ａの一方の主面に露出している。このド
リフト領域１の不純物濃度は、柱状ベース領域３を形成
しない浅いベース領域の従来のＦＥＴのドリフト領域の
不純物濃度よりは高い。従って、ドリフト領域１の抵抗
率は従来のＦＥＴのドリフト領域の抵抗率の１／５〜１
／３である。Drift region 1 is an N-type semiconductor region and has a lower impurity concentration than N + -type drain region 2.
Note that, since the drift region 1 has the same conductivity type as the drain region 2, it can be called a drain region.
Drift region 1 is formed by epitaxially growing an N-type semiconductor in multiple layers on drain region 2, and a part thereof is exposed on one main surface of semiconductor substrate 5a. The impurity concentration of the drift region 1 is higher than the impurity concentration of the drift region of the conventional FET in the shallow base region where the columnar base region 3 is not formed. Therefore, the resistivity of the drift region 1 is 1/5 to 1 of the resistivity of the drift region of the conventional FET.
/ 3.
【００１１】Ｎ+ 型ドレイン領域２はドリフト領域１と
半導体基体５ａの他方の主面との間に配置されている。
なお、ドレイン領域２とドリフト領域１との境界面は平
板状半導体基体５ａの他方の主面に平行である。ドレイ
ン電極６は例えばアルミニウム蒸着層から成り、半導体
基体５ａの他方の主面においてドレイン領域２に接続さ
れている。N + type drain region 2 is arranged between drift region 1 and the other main surface of semiconductor substrate 5a.
Note that the boundary surface between the drain region 2 and the drift region 1 is parallel to the other main surface of the planar semiconductor substrate 5a. The drain electrode 6 is made of, for example, an aluminum deposition layer, and is connected to the drain region 2 on the other main surface of the semiconductor substrate 5a.
【００１２】ベース領域３は、ボデイ領域又はチャネル
形成領域とも呼ぶことができるものであって、ドリフト
領域１内にその上面から下面に向って柱状に形成されて
いる。ベース領域３の上面は半導体基体５ａの上面に露
出しており、ベース領域３の下面はドレイン領域２から
若干離間するように配置されている。このように若干離
間するように配置することによってベ−ス領域３の下側
での電界集中を緩和できると考えられる。図２に示すよ
うに、ベース領域３は平面的に見て半導体基体５ａ内に
島状に形成され且つ均一に分散配置されており、各々の
ベース領域３は四角形状の平面形状を有する。なお、ベ
ース領域３の平面形状は四角形に限られず、円形にして
もよい。このベース領域３は、周知のエピタキシャル成
長技術と拡散技術とを繰り返して形成する。即ち、ドレ
イン領域２の上に肉薄のＮ型半導体領域をエピタキシャ
ル成長によって形成し、このＮ型半導体領域に拡散技術
によってＰ型半導体領域を形成する。このＰ型半導体領
域はベース領域の一部を構成し、Ｐ型半導体領域の形成
されていない部分のＮ型半導体領域はドリフト領域１の
一部を構成する。Ｐ型半導体領域を形成したらこのＰ型
半導体領域とＮ型半導体領域の上面に再び肉薄のＮ型半
導体領域をエピタキシャル成長によって形成し、先に形
成したＰ型半導体領域と連続するようにＰ型半導体領域
を拡散によって形成する。この工程を複数回（例えば６
回）繰り返すことで、柱状のベース領域３とドリフト領
域１が形成される。The base region 3 can be called a body region or a channel forming region, and is formed in the drift region 1 in a columnar shape from the upper surface to the lower surface. The upper surface of the base region 3 is exposed on the upper surface of the semiconductor substrate 5a, and the lower surface of the base region 3 is arranged so as to be slightly separated from the drain region 2. It is considered that the electric field concentration on the lower side of the base region 3 can be reduced by arranging the base region 3 slightly apart in this way. As shown in FIG. 2, the base regions 3 are formed in the form of islands in the semiconductor substrate 5a and are uniformly dispersed in a plan view, and each base region 3 has a square planar shape. Note that the planar shape of the base region 3 is not limited to a square, but may be a circle. The base region 3 is formed by repeating a well-known epitaxial growth technique and diffusion technique. That is, a thin N-type semiconductor region is formed on the drain region 2 by epitaxial growth, and a P-type semiconductor region is formed in this N-type semiconductor region by a diffusion technique. The P-type semiconductor region forms a part of the base region, and the N-type semiconductor region where the P-type semiconductor region is not formed forms a part of the drift region 1. After the formation of the P-type semiconductor region, a thin N-type semiconductor region is again formed on the upper surfaces of the P-type semiconductor region and the N-type semiconductor region by epitaxial growth, and the P-type semiconductor region is connected to the previously formed P-type semiconductor region. Is formed by diffusion. This step is repeated several times (for example, 6
By repeating the above, a columnar base region 3 and a drift region 1 are formed.
【００１３】Ｎ型ソース領域４は各ベース領域３の中に
島状に形成され、半導体基体５ａの一方の主面に露出し
ている。多数のベース領域３の中で内側に配置された１
６個のベース領域３の中には四角形即ち環状のソース領
域４が形成され、外側の辺上の８個のベース領域３の中
にはコ字状のソース領域４が形成され、角の８個のベ−
ス領域３の中にはＬ字状のソ−ス領域４が形成されてい
る。ベース領域３におけるソース領域４とドリフト領域
１との間の表面側部分がチャネル形成部分となる。The N-type source region 4 is formed in an island shape in each base region 3, and is exposed on one main surface of the semiconductor substrate 5a. 1 arranged inside in a number of base regions 3
A square or annular source region 4 is formed in the six base regions 3, a U-shaped source region 4 is formed in the eight base regions 3 on the outer side, and a corner 8 is formed. Individual bases
An L-shaped source region 4 is formed in the source region 3. The surface side portion between the source region 4 and the drift region 1 in the base region 3 becomes a channel forming portion.
【００１４】ソース電極７は、例えばアルミニウムの蒸
着層であって、各ソース領域４と各ベース領域３との両
方に接続され、複数のソース領域４を共通接続するよう
に層間絶縁膜１１の上にも設けられている。The source electrode 7 is, for example, a vapor deposited layer of aluminum, is connected to both the source regions 4 and the base regions 3, and is formed on the interlayer insulating film 11 so as to connect the plurality of source regions 4 in common. Is also provided.
【００１５】ゲート絶縁膜９は少なくともベース領域３
における前述したチャネル形成部分を覆うように形成さ
れたシリコン酸化膜から成る。The gate insulating film 9 includes at least the base region 3
Of a silicon oxide film formed so as to cover the above-mentioned channel forming portion.
【００１６】ゲート電極８は、例えば周知の化学的気相
成長法で形成された多結晶シリコンから成り、ゲート絶
縁膜９の上に形成されている。このゲート電極８は平面
的に見て格子状に形成され、図示されていない金属製ゲ
ート端子に接続されている。The gate electrode 8 is made of, for example, polycrystalline silicon formed by a known chemical vapor deposition method, and is formed on the gate insulating film 9. The gate electrode 8 is formed in a lattice shape when viewed in plan, and is connected to a metal gate terminal (not shown).
【００１７】本発明に従って設けられた多数（この実施
例では６４個）の耐圧向上用領域１２は、図２から明ら
かなように平面的に見てベース領域３を囲むように分散
配置されている。この耐圧向上用領域１２はベース領域
３と同時に形成されたものであって、ベース領域３と同
一の不純物濃度を有するＰ型拡散領域から成り且つベー
ス領域３と同一平面形状及び同一断面形状を有し、且つ
ベース領域３と同様に均一に分散配置されている。即
ち、耐圧向上用領域１２はドリフト領域１の中に島状に
形成され、半導体基体５ａの一方の主面から他方の主面
に向って柱状に延びている。この耐圧向上用領域１２の
先端はＮ+ 型ドレイン領域２の近くに位置している。な
お、複数の耐圧向上用領域１２の相互間隔はベース領域
３の相互間隔と同一である。A large number (64 in this embodiment) of withstand voltage improving regions 12 provided according to the present invention are dispersedly arranged so as to surround the base region 3 in a plan view as is apparent from FIG. . This withstand voltage improving region 12 is formed simultaneously with the base region 3, is formed of a P-type diffusion region having the same impurity concentration as the base region 3, and has the same planar shape and the same sectional shape as the base region 3. And are uniformly distributed like the base region 3. That is, the breakdown voltage improving region 12 is formed in the drift region 1 in an island shape, and extends in a columnar shape from one main surface of the semiconductor base 5a toward the other main surface. The tip of the breakdown voltage improving region 12 is located near the N + type drain region 2. The mutual interval between the plurality of withstand voltage improving regions 12 is the same as the mutual interval between the base regions 3.
【００１８】図２において点々を付して示すＰ型補助領
域１３は耐圧向上用領域１２と同一導電型及び同一不純
物濃度を有し、図２から明らかなように耐圧向上用領域
１２及びベース領域３を囲むように環状に形成されてい
る。補助領域１３は複数回のエピタキシャル成長の最後
のエピタキシャル層にＰ型不純物を拡散したものであっ
て、耐圧向上用領域１２及びベース領域３の最上層と同
時に形成されている。このため、補助領域１３の深さは
耐圧向上用領域１２の深さの例えば１／６（好ましくは
１／１０〜１／２）のように大幅に浅く設定される。こ
の実施例では補助領域１３の１つは耐圧向上用領域１２
の外周側に接触し、別の１つは最外周側のベース領域２
の外周側に接触している。The P-type auxiliary region 13 indicated by dots in FIG. 2 has the same conductivity type and the same impurity concentration as the breakdown voltage improving region 12, and as apparent from FIG. 3 is formed in a ring shape. The auxiliary region 13 is formed by diffusing a P-type impurity into the last epitaxial layer of the plurality of epitaxial growths, and is formed simultaneously with the breakdown voltage improving region 12 and the uppermost layer of the base region 3. For this reason, the depth of the auxiliary region 13 is set to be significantly shallow, for example, 1/6 (preferably 1/10 to 1/2) of the depth of the breakdown voltage improving region 12. In this embodiment, one of the auxiliary regions 13 is a region 12 for improving the breakdown voltage.
And another one is the outermost base region 2
Is in contact with the outer peripheral side.
【００１９】フィールドプレート１４は例えばアルミニ
ウムの蒸着層であって、補助領域１３に絶縁膜１０を介
して対向するように環状に形成されている。即ち、フィ
ールドプレート１４の平面形状は図２に示す補助領域１
３とほぼ同一である。図３の実施例ではフィールドプレ
ート１４はＰ型の補助領域１３、耐圧向上用領域１２及
びベース領域３に対して電気的に接続されていない。ま
た、２つの環状フィールドプレート１４は互いに分離し
ている。The field plate 14 is, for example, a vapor-deposited layer of aluminum, and is formed in a ring shape so as to face the auxiliary region 13 with the insulating film 10 interposed therebetween. That is, the planar shape of the field plate 14 is the auxiliary area 1 shown in FIG.
It is almost the same as 3. In the embodiment of FIG. 3, the field plate 14 is not electrically connected to the P-type auxiliary region 13, the withstand voltage improving region 12, and the base region 3. Also, the two annular field plates 14 are separated from each other.
【００２０】ＥＱＲ１５は例えばアルミニウムの蒸着層
から成る導体層であって、補助領域１３よりも外周側に
環状に配置されている。このＥＱＲ１５は絶縁膜１０の
下層を介して半導体基体５ａの上面に対向しており、半
導体基体５ａには電気的に接続されていない。なお、Ｅ
ＱＲ１５は、絶縁膜１０の表面の電荷の安定化を図る機
能を有する他に空乏層の外周への広がりを防止するチャ
ンネルストッパの機能も有する。The EQR 15 is a conductor layer made of, for example, an aluminum vapor-deposited layer, and is arranged annularly on the outer peripheral side of the auxiliary region 13. This EQR 15 faces the upper surface of the semiconductor substrate 5a via the lower layer of the insulating film 10, and is not electrically connected to the semiconductor substrate 5a. Note that E
The QR 15 has a function of stabilizing charges on the surface of the insulating film 10 and also has a function of a channel stopper for preventing the depletion layer from spreading to the outer periphery.
【００２１】本実施例によれば、ＦＥＴ素子周辺側の耐
圧（周辺耐圧）の向上が図られ、高耐圧化が高水準に達
成される。また、高耐圧化したにも拘らず動作抵抗（オ
ン抵抗）を小さく保つことができる。即ち、ベース領域
３がドリフト領域１内に柱状に形成され、ドリフト領域
１の比抵抗が相対的に小さく設定されているため、ドリ
フト領域１の電流経路の抵抗を小さくでき動作抵抗の低
減化が高水準に達成される。また、素子形成領域（活性
領域）の耐圧については、ベース領域３の相互間が図３
において点線で模式的に示すように空乏層１６によって
埋められるため、十分高い耐圧を得ることができる。ま
た、素子周辺側の耐圧については、耐圧向上用領域１２
及び補助領域１３によって図示のように素子外周側に電
界集中を良好に緩和するように滑らかに空乏層１６を広
げることができるため、素子中央側と同様に十分に高い
耐圧を得ることができる。According to this embodiment, the withstand voltage (peripheral withstand voltage) on the peripheral side of the FET element is improved, and a high withstand voltage is achieved at a high level. In addition, the operating resistance (ON resistance) can be kept low despite the high withstand voltage. That is, since the base region 3 is formed in a columnar shape in the drift region 1 and the specific resistance of the drift region 1 is set relatively small, the resistance of the current path in the drift region 1 can be reduced, and the operating resistance can be reduced. Achieved to a high standard. As for the breakdown voltage of the element formation region (active region), the distance between the base regions 3 is shown in FIG.
Is filled with the depletion layer 16 as schematically shown by the dotted line, and a sufficiently high breakdown voltage can be obtained. As for the breakdown voltage on the element peripheral side, the breakdown voltage improving region 12 is used.
In addition, the depletion layer 16 can be smoothly expanded by the auxiliary region 13 so as to satisfactorily reduce the electric field concentration on the outer peripheral side of the element as shown in the figure, so that a sufficiently high withstand voltage can be obtained similarly to the central side of the element.
【００２２】空乏層１６の広がりについて更に詳しく説
明すると、ゲート電極８とソース電極７との間にチャネ
ルを形成する電圧が印加されていない状態において、ド
リフト領域１とベース領域３との間のＰＮ接合を逆バイ
アスする向きの高い電圧をドレイン電極６とソース電極
７との間に印加すると、ベース領域３よりも不純物濃度
の低いドリフト領域１に空乏層が広がる。ベース領域３
は柱状に多数個配置されているのでベース領域３の相互
間のドリフト領域１は空乏層１６で埋まる。空乏層１６
はベース領域３の相互間のみでなく、ベース領域３と同
様に形成された耐圧向上用領域１２の相互間及びこれと
ベース領域３との間にも広がる。ベース領域３の外周側
において耐圧向上用領域１２のみによって空乏層１６を
十分に広げることができないが、補助領域１３を設ける
と、この補助によって空乏層１６が耐圧向上用領域１２
の相互間及びベース領域３との間及び耐圧向上用領域１
２の外側に良好に広がる。また、補助領域１３は耐圧向
上用領域１２よりも浅く形成され且つ外周側に配置され
ているので、外周側での空乏層１６の変化が緩慢にな
り、耐圧向上が良好に達成される。The spread of the depletion layer 16 will be described in more detail. In a state where a voltage for forming a channel between the gate electrode 8 and the source electrode 7 is not applied, the PN between the drift region 1 and the base region 3 is not applied. When a high voltage that reverses the junction is applied between the drain electrode 6 and the source electrode 7, the depletion layer spreads in the drift region 1 having a lower impurity concentration than the base region 3. Base area 3
Are arranged in a columnar shape, the drift region 1 between the base regions 3 is filled with the depletion layer 16. Depletion layer 16
Extends not only between the base regions 3 but also between the breakdown voltage improving regions 12 formed similarly to the base region 3 and between the regions 12 and the base region 3. Although the depletion layer 16 cannot be sufficiently widened only by the breakdown voltage improving region 12 on the outer peripheral side of the base region 3, if the auxiliary region 13 is provided, the depletion layer 16 is reduced by the auxiliary region 13.
Between each other and between the base region 3 and the breakdown voltage improving region 1
2 spreads well outside. In addition, since the auxiliary region 13 is formed shallower than the breakdown voltage improving region 12 and is arranged on the outer peripheral side, the change of the depletion layer 16 on the outer peripheral side becomes slow, and the improvement of the withstand voltage is achieved satisfactorily.
【００２３】本実施例では、耐圧向上用領域１２及びこ
の補助領域１３の他にフィールドプレート１４及びＥＱ
Ｒ１５が設けられているので、空乏層１６が更に安定的
且つ良好に広がる。また、ＥＱＲ１５の働きによって空
乏層１６が半導体基体５ａの側面まで広がることが阻止
され、高耐圧化を安定的に達成することができる。ま
た、本実施例では耐圧向上用領域１２がベース領域３と
同時に形成されるので、生産性の点で有利である。In this embodiment, in addition to the breakdown voltage improving region 12 and the auxiliary region 13, the field plate 14 and the EQ
Since R15 is provided, the depletion layer 16 spreads more stably and favorably. Further, the function of the EQR 15 prevents the depletion layer 16 from spreading to the side surface of the semiconductor substrate 5a, so that a high breakdown voltage can be stably achieved. Further, in this embodiment, the withstand voltage improving region 12 is formed simultaneously with the base region 3, which is advantageous in terms of productivity.
【００２４】[0024]
【第２の実施例】次に、図４に示す第２の実施例の絶縁
ゲート型電界効果トランジスタを説明する。但し、図４
及び後述する図５〜図７において図２及び図３と実質的
に同一の部分には同一の符号を付してその説明を省略す
る。Second Embodiment Next, an insulated gate field effect transistor according to a second embodiment shown in FIG. 4 will be described. However, FIG.
In FIGS. 5 to 7 to be described later, substantially the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof will be omitted.
【００２５】図４のＦＥＴはＰ型補助領域１３ａの配置
を除いて第１の実施例と同一に構成されている。図４の
補助領域１３ａは図３の補助領域１３に対応するもので
あって、耐圧向上用領域１２及びベース領域３から外周
側に離間している。なお、図４の補助領域１３ａの平面
形状は図２と同様に環状であり、また深さは図３の補助
領域１３と同一である。この第２の実施例によっても第
１の実施例と同一の効果を得ることができる。The FET of FIG. 4 has the same configuration as that of the first embodiment except for the arrangement of the P-type auxiliary region 13a. The auxiliary region 13a in FIG. 4 corresponds to the auxiliary region 13 in FIG. 3, and is separated from the breakdown voltage improving region 12 and the base region 3 on the outer peripheral side. The planar shape of the auxiliary region 13a in FIG. 4 is annular as in FIG. 2, and the depth is the same as the auxiliary region 13 in FIG. According to the second embodiment, the same effect as that of the first embodiment can be obtained.
【００２６】[0026]
【第３の実施例】図５は第３の実施例のＦＥＴの半導体
基体５ａの表面の一部を示す。図５の第３の実施例のＦ
ＥＴは、点々を付して説明的に示すＰ型補助領域１３ｂ
を除いて第１の実施例と同一に構成されている。第１の
実施例の補助領域１３と同一の目的で設けられた図５の
Ｐ型補助領域１３ｂは多数の島状領域から成る。補助領
域１３ｂは第１の実施例の補助領域１３と同一の深さ、
同一の不純物濃度を有し、耐圧向上用領域１２及び最外
周側のベース領域３の相互間に分散配置されている。図
６は耐圧向上用領域１２と補助領域１３ｂとの位置関係
を示すものである。これから明らかなように４個の耐圧
向上用領域１２の中心を結ぶ点線の四角形の中心に補助
領域１３ｂの中心が一致するように補助領域１３ｂが配
置されている。また、四角形の補助領域１３ｂと４つの
耐圧向上用領域１２との最短距離Ｌがそれぞれほぼ同一
になるように補助領域１３ｂが配置されている。なお、
ベース領域３と補助領域１３ｂとの関係も図６と同様で
ある。Third Embodiment FIG. 5 shows a part of the surface of a semiconductor substrate 5a of an FET according to a third embodiment. F of the third embodiment in FIG.
ET is a P-type auxiliary region 13b which is illustrated with dots.
Except for this, the configuration is the same as that of the first embodiment. The P-type auxiliary region 13b of FIG. 5 provided for the same purpose as the auxiliary region 13 of the first embodiment is composed of a large number of island regions. The auxiliary region 13b has the same depth as the auxiliary region 13 of the first embodiment,
They have the same impurity concentration and are distributed between the breakdown voltage improving region 12 and the outermost base region 3. FIG. 6 shows the positional relationship between the breakdown voltage improving region 12 and the auxiliary region 13b. As is clear from this, the auxiliary region 13b is arranged so that the center of the auxiliary region 13b coincides with the center of the dotted rectangle connecting the centers of the four breakdown voltage improving regions 12. The auxiliary regions 13b are arranged such that the shortest distances L between the rectangular auxiliary regions 13b and the four withstand voltage improving regions 12 are substantially the same. In addition,
The relationship between the base region 3 and the auxiliary region 13b is the same as in FIG.
【００２７】図６に示すように補助領域１３ｂを配置す
ることによって、耐圧向上用領域１２の相互間及び最外
周側のベース領域３と耐圧向上用領域１２との間に空乏
層を良好に広げることができ、耐圧向上が第１の実施例
と同様に達成される。By arranging the auxiliary region 13b as shown in FIG. 6, the depletion layer is favorably spread between the breakdown voltage improving regions 12 and between the outermost base region 3 and the breakdown voltage improving region 12. Thus, an improvement in the breakdown voltage is achieved in the same manner as in the first embodiment.
【００２８】[0028]
【変形例】本発明は上述の実施例に限定されるものでは
なく、例えば次の変形が可能なものである。 （１） フィールドプレート１４を図７に示すように補
助領域１３又は耐圧向上用領域１２に電気的に接続する
ことができる。この様に接続すると、補助領域１３又は
耐圧向上用領域１２の等電位性が向上する。 （２） フィールドプレート１４部分の絶縁膜１０に図
７に示すように段差を設け、外周側を厚くすることがで
きる。これにより、外周側ほどフィールドプレートの効
果が低下し、空乏層の外周側での変化が滑らかになる。
また、図７に示すようにフィールドプレート１４を補助
領域１３又は耐圧向上用領域１２よりも外周側に延在さ
せることができる。 （３） 図７に示すように半導体基体５ａの外周縁にＮ
+ 型半導体領域１ａを形成し、ここにＥＱＲ１５を電気
的に接続することができる。これにより、空乏層の広が
りをＮ+ 型半導体領域１ａで確実に防ぐことができる。 （４） Ｎ+ 型ドレイン領域２の中にＰ型領域を配置し
てユニバーサルコンタクト構造にすることができる。 （５） 実施例では、ベ−ス領域３及び耐圧向上用領域
１２がこれらの中心を結ぶ仮想四角形の頂点にその中心
を位置させて配置された例を示したが、ベ−ス領域３及
び耐圧向上用領域１２がこれらの中心を結ぶ仮想三角形
やひし形の頂点にその中心を位置させて配置してもよ
い。 （６） ベ−ス領域３、耐圧向上用領域１２及び補助領
域１３の表面露出部分の不純物濃度を選択的に高く設定
してもよい。 （７） 補助領域１３の耐圧向上領域１２から外側に延
び出す長さは、要求される耐圧のレベルに応じて任意に
設定することができる。 （８） 実施例では、耐圧向上用領域１２をベ−ス領域
３と同一の配置としたが、電界緩和効果を高める為に耐
圧向上用領域１２をベ−ス領域２に比べて緻密に配置す
ることもできる。また、耐圧向上用領域１２の配置を全
てで同じにせず、例えばベ−ス領域２を包囲する最内周
の耐圧向上用領域１２のみ他の耐圧向上用領域１２に比
べて緻密に配置することもできる。 （９）最外周の耐圧向上用領域１２の外側には、補助領
域１３を設けない構造とすることもできる。又、耐圧向
上用領域１２の外側に複数本の補助領域１３を設けるこ
ともできる。 （１０） ベ−ス領域３及び耐圧向上用領域１２を、そ
の側面にこぶを有しない実質的なストレ−トな形状とす
ることもできる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The field plate 14 can be electrically connected to the auxiliary region 13 or the withstand voltage improving region 12 as shown in FIG. With such connection, the equipotential of the auxiliary region 13 or the withstand voltage improving region 12 is improved. (2) As shown in FIG. 7, steps may be provided in the insulating film 10 in the field plate 14 to increase the thickness on the outer peripheral side. As a result, the effect of the field plate decreases toward the outer peripheral side, and the change on the outer peripheral side of the depletion layer becomes smooth.
Further, as shown in FIG. 7, the field plate 14 can be extended to the outer peripheral side of the auxiliary region 13 or the withstand voltage improving region 12. (3) As shown in FIG. 7, N
The + type semiconductor region 1a is formed, and the EQR 15 can be electrically connected to the + type semiconductor region 1a. Thus, the expansion of the depletion layer can be reliably prevented in the N + type semiconductor region 1a. (4) A universal contact structure can be provided by disposing a P-type region in the N + -type drain region 2. (5) In the embodiment, an example is shown in which the base region 3 and the withstand voltage improving region 12 are arranged with their centers located at the vertices of a virtual rectangle connecting these centers. The withstand voltage improving region 12 may be arranged such that the center is located at the vertex of a virtual triangle or diamond connecting these centers. (6) The impurity concentration of the surface exposed portions of the base region 3, the breakdown voltage improving region 12, and the auxiliary region 13 may be selectively set high. (7) The length of the auxiliary region 13 extending outward from the breakdown voltage improving region 12 can be arbitrarily set according to the required breakdown voltage level. (8) In the embodiment, the breakdown voltage improving region 12 is arranged in the same manner as the base region 3. However, the breakdown voltage improving region 12 is more densely arranged than the base region 2 in order to enhance the electric field relaxation effect. You can also. In addition, the arrangement of the breakdown voltage improving regions 12 is not the same in all cases, and for example, only the innermost peripheral breakdown voltage improving region 12 surrounding the base region 2 is densely arranged as compared with the other breakdown voltage improving regions 12. Can also. (9) A structure in which the auxiliary region 13 is not provided outside the breakdown voltage improving region 12 on the outermost periphery may be adopted. Further, a plurality of auxiliary regions 13 can be provided outside the withstand voltage improving region 12. (10) The base region 3 and the breakdown voltage improving region 12 may be formed in a substantially straight shape having no bump on the side surface.
【図１】従来のＦＥＴを示す断面図である。FIG. 1 is a sectional view showing a conventional FET.
【図２】第１の実施例のＦＥＴの半導体基体の表面を示
す平面図である。FIG. 2 is a plan view showing a surface of a semiconductor substrate of the FET according to the first embodiment.
【図３】第１の実施例のＦＥＴの一部を図２のＡ−Ａ線
で示す断面図である。FIG. 3 is a cross-sectional view of a part of the FET according to the first embodiment, taken along line AA of FIG. 2;
【図４】第２の実施例のＦＥＴの一部を図３と同様に示
す断面図である。FIG. 4 is a cross-sectional view showing a part of the FET of the second embodiment, similarly to FIG.
【図５】第３の実施例のＦＥＴの半導体基体の表面の一
部を示す平面図である。FIG. 5 is a plan view showing a part of the surface of a semiconductor substrate of an FET according to a third embodiment.
【図６】図５の一部を拡大して示す平面図である。FIG. 6 is an enlarged plan view showing a part of FIG. 5;
【図７】変形例のＦＥＴの一部を示す断面図である。FIG. 7 is a cross-sectional view showing a part of a FET according to a modified example.
１ ドリフト領域 ２ ドレイン領域 ３ ベース領域 ４ ソース領域 ５ａ 半導体基体 １２ 耐圧向上用領域 １３ 補助領域 １４ フィールドプレート １５ ＥＱＲ Reference Signs List 1 drift region 2 drain region 3 base region 4 source region 5a semiconductor base 12 breakdown voltage improving region 13 auxiliary region 14 field plate 15 EQR
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 29/06 ３０１ Ｈ０１Ｌ 29/06 ３０１Ｇ (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 29/06 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI H01L 29/06 301 H01L 29/06 301G (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29/78 H01L 29 / 06
Claims (6)
ース領域と複数のソース領域と複数の耐圧向上用領域と
補助領域とを有する半導体基体と、ゲート絶縁膜と、ド
レイン電極と、ソース電極と、ゲート電極とを備え、 前記ドリフト領域は、前記ドレイン領域の不純物濃度よ
りも低い不純物濃度を有し且つ前記半導体基体の一方の
主面に露出する部分を有するように配置され且つ前記ド
レイン領域の上に前記ドレイン領域と同一の導電型の複
数のエピタキシャル成長層を設けたものから成り、 前記ドレイン領域は前記ドリフト領域と前記半導体基体
の他方の主面との間に配置され、 前記複数のベース領域のそれぞれは、前記ドリフト領域
と反対の導電型を有し且つ前記ドリフト領域の中に島状
に分散配置され且つ前記半導体基体の一方の主面から他
方の主面に向って柱状に延びており且つ前記ドリフト領
域を形成する前記複数のエピタキシャル成長層に拡散で
形成された領域から成り、 前記複数のソース領域のそれぞれは前記ベース領域と反
対の導電型を有し且つ前記複数のベース領域の中に島状
に配置され、 前記複数の耐圧向上用領域のそれぞれは、前記ベース領
域と同一の導電型を有して前記ドリフト領域の中に島状
に形成され且つ平面的に見て前記ベース領域の外側に分
散配置され且つ前記半導体基体の一方の主面から他方の
主面に向って柱状に延びており且つ前記ドリフト領域を
形成する前記複数のエピタキシャル成長層に拡散で形成
された領域から成り且つ前記ベース領域と同じ深さを有
し、 前記補助領域は前記ドリフト領域における空乏層の広が
りを補助するためのものであって、前記耐圧向上用領域
と同一の導電型を有し且つ前記半導体基体の表面に露出
するように前記ドリフト領域の中に形成され且つ前記耐
圧向上用領域よりも浅く形成され且つ平面的に見て前記
複数の耐圧向上用領域の外周側を囲むように環状に形成
され且つ前記複数の耐圧向上用領域に接触している領域
からなり、前記ドレイン電極と前記ソース電極との間に
電圧が印加された時に、前記複数のベース領域、前記複
数の耐圧向上用領域、及び前記補助領域に隣接している
前記ドリフト領域のそれぞれの部分に生じる空乏層が互
いに連続するように前記複数 のベース領域と前記複数の
耐圧向上用領域と前記補助領域とが配置されていること
を特徴とする絶縁ゲート型電界効果トランジスタ。A semiconductor substrate having a drain region, a drift region, a plurality of base regions, a plurality of source regions, a plurality of breakdown voltage improving regions, and an auxiliary region; a gate insulating film; a drain electrode; and a gate electrode, the drift region is arranged to have a portion exposed to one main surface of and the semiconductor body has an impurity concentration lower than the impurity concentration of the drain region and the de
The same conductivity type as the drain region is formed on the rain region.
A plurality of epitaxially grown layers, wherein the drain region is disposed between the drift region and the other main surface of the semiconductor substrate, and each of the plurality of base regions has a conductive property opposite to the drift region. The semiconductor substrate is arranged in an island-like manner in the drift region, and
And extends in a columnar manner toward the main surface of the
Diffusion into the plurality of epitaxially grown layers forming a region.
A plurality of source regions, each of the plurality of source regions being opposite to the base region.
It is arranged like islands in and said plurality of base regions have a conductivity type pair, each of the plurality of improvement in withstand voltage area, in said drift region having the same conductivity type as the base region Are formed in the shape of an island, are dispersedly arranged outside the base region when viewed in plan, and are separated from one main surface of the semiconductor substrate to the other.
Extending in a columnar shape toward the main surface and forming the drift region
Formed by diffusion in the plurality of epitaxial growth layers to be formed
The auxiliary region is for supporting the expansion of a depletion layer in the drift region , and has the same conductivity type as the breakdown voltage improving region. And formed in the drift region so as to be exposed on the surface of the semiconductor substrate, formed shallower than the breakdown voltage improving region , and viewed in plan.
Formed annularly so as to surround the outer peripheral side of multiple withstand voltage improvement areas
Region that is formed and is in contact with the plurality of withstand voltage improving regions.
Comprising between the drain electrode and the source electrode
When a voltage is applied, the plurality of base regions, the plurality of
Adjacent to a number of withstand voltage improving regions and the auxiliary region
The depletion layer generated in each part of the drift region is
The plurality of base regions and the plurality of
An insulated gate field effect transistor , wherein a withstand voltage improving region and the auxiliary region are arranged .
と同一の導電型を有し且つ前記半導体基体の表面に露出
するように前記ドリフト領域の中に形成され且つ前記ベ
ース領域よりも浅く形成され且つ平面的に見て前記複数
のベース領域の内の最外周側の複数のベース領域を囲む
ように環状に形成され且つ前記最外周側の複数のベース
領域に接触している領域を有していることを特徴とする
請求項１記載の絶縁ゲート型電界効果トランジスタ。2. The auxiliary area further includes a base area.
Has the same conductivity type as that of the semiconductor substrate and is exposed on the surface of the semiconductor substrate.
Formed in the drift region and
The plurality of regions are formed shallower than the source region and viewed in plan.
Surrounds the outermost base region of the base regions
A plurality of bases formed in an annular shape and on the outermost peripheral side
The insulated gate field effect transistor according to claim 1 , further comprising a region in contact with the region .
ース領域と複数のソース領域と複数の耐圧向上用領域と
補助領域とを有する半導体基体と、ゲート絶縁膜と、ド
レイン電極と、ソース電極と、ゲート電極とを備え、 前記ドリフト領域は、前記ドレイン領域の不純物濃度よ
りも低い不純物濃度を有し且つ前記半 導体基体の一方の
主面に露出する部分を有するように配置され且つ前記ド
レイン領域の上に前記ドレイン領域と同一の導電型の複
数のエピタキシャル成長層を設けたものから成り、前記ドレイン領域は前記ドリフト領域と前記半導体基体
の他方の主面との間に配置され、 前記複数のベース領域のそれぞれは、前記ドリフト領域
と反対の導電型を有し且つ前記ドリフト領域の中に島状
に分散配置され且つ前記半導体基体の一方の主面から他
方の主面に向って柱状に延びており且つ前記ドリフト領
域を形成する前記複数のエピタキシャル成長層に拡散で
形成された領域から成り、 前記複数のソース領域のそれぞれは前記ベース領域と反
対の導電型を有し且つ前記複数のベース領域の中に島状
に配置され、前記複数の耐圧向上用領域のそれぞれは、前記ベース領
域と同一の導電型を有して前記ドリフト領域の中に島状
に形成され且つ平面的に見て前記ベース領域の外側に分
散配置され且つ前記半導体基体の一方の主面から他方の
主面に向って柱状に延びており且つ前記ドリフト領域を
形成する前記複数のエピタキシャル成長層に拡散で形成
された領域から成り且つ前記ベース領域と同じ深さを有
し、 前記補助領域は前記ドリフト領域における空乏層の広が
りを補助するためのもの であって、前記耐圧向上用領域
と同一の導電型を有し且つ前記半導体基体の表面に露出
するように前記ドリフト領域の中に形成され且つ前記耐
圧向上用領域よりも浅く形成され且つ平面的に見て前記
複数の耐圧向上用領域の外周側を囲むように環状に形成
され且つ前記複数の耐圧向上用領域から離間している領
域から成り、 前記ドレイン電極と前記ソース電極との間に電圧が印加
された時に、前記複数のベース領域、前記複数の耐圧向
上用領域、及び前記補助領域に隣接している前記ドリフ
ト領域のそれぞれの部分に生じる空乏層が互いに連続す
るように前記複数のベース領域と前記複数の耐圧向上用
領域と前記補助領域とが配置されている ことを特徴とす
る絶縁ゲート型電界効果トランジスタ。3. A drain region, a drift region and a plurality of layers.
Source region, a plurality of source regions, and a plurality of withstand voltage improving regions.
A semiconductor substrate having an auxiliary region; a gate insulating film;
A drain electrode; a source electrode; and a gate electrode, wherein the drift region has an impurity concentration of the drain region.
Remote a plurality of epitaxially grown layers of the drain region same conductivity type as on the lower has an impurity concentration and the are arranged to have a portion exposed to one main surface of the semi-conductor substrate and the drain region Wherein the drain region comprises the drift region and the semiconductor substrate.
Each of the plurality of base regions is disposed between the drift region and the other main surface of the drift region.
Islands in the drift region
And distributed from one main surface of the semiconductor substrate to the other.
And extends in a columnar manner toward the main surface of the
Diffusion into the plurality of epitaxially grown layers forming a region.
A plurality of source regions, each of the plurality of source regions being opposite to the base region.
Each of the plurality of regions has a pair of conductivity types and is arranged in an island shape in the plurality of base regions.
Islands in the drift region with the same conductivity type as the region
Formed outside the base region in plan view.
Dispersed from one main surface of the semiconductor substrate to the other.
Extending in a columnar shape toward the main surface and forming the drift region
Formed by diffusion in the plurality of epitaxial growth layers to be formed
Region having the same depth as the base region.
The auxiliary region has a depletion layer in the drift region.
To improve the breakdown voltage.
Has the same conductivity type as that of the semiconductor substrate and is exposed on the surface of the semiconductor substrate.
Formed in the drift region and
It is formed shallower than the pressure improving region, and
Formed annularly so as to surround the outer peripheral side of multiple withstand voltage improvement areas
That are separated from the plurality of withstand voltage improving regions.
Consists range, a voltage applied between the drain electrode and the source electrode
The plurality of base regions and the plurality of withstand voltage directions.
An upper area and the drift adjacent to the auxiliary area
The depletion layers that occur in each part of the
So that the plurality of base regions and the plurality of
An insulated gate field effect transistor , wherein a region and the auxiliary region are arranged .
と同一の導電型を有し且つ前記半導体基体の表面に露出
するように前記ドリフト領域の中に形成され且つ前記ベ
ース領域よりも浅く形成され且つ平面的に見て前記複数
のベース領域の内の最外周側の複数のベース領域を囲む
ように環状に形成され且つ前記最外周側の複数のベース
領域から離間している領域を有していることを特徴とす
る請求項３記載の絶縁ゲート型電界効果トランジスタ。 4. The auxiliary area further includes a base area.
Has the same conductivity type as that of the semiconductor substrate and is exposed on the surface of the semiconductor substrate.
Formed in the drift region and
The plurality of regions are formed shallower than the source region and viewed in plan.
Surrounds the outermost base region of the base regions
A plurality of bases formed in an annular shape and on the outermost peripheral side
4. The insulated gate field effect transistor according to claim 3 , further comprising a region separated from the region .
ース領域と複数のソース領域と複数の耐圧向上用領域と
複数の補助領域とを有する半導体基体と、ゲート絶縁膜
と、ドレイン電極と、ソース電極と、ゲート電極とを備
え、前記ドリフト領域は、前記ドレイン領域の不純物濃度よ
りも低い不純物濃度を有し且つ前記半導体基体の一方の
主面に露出する部分を有するように配置され且つ前記ド
レイン領域の上に前記ドレイン領域と同一の導電型の複
数のエピタキシャル成長層を設けたものから成り、 前記ドレイン領域は前記ドリフト領域と前記半導体基体
の他方の主面との間に配置され、 前記複数のベース領域のそれぞれは、前記ドリフト領域
と反対の導電型を有し且つ前記ドリフト領域の中に島状
に分散配置され且つ前記半導体基体の一方の主面から他
方の主面に向って柱状に延びており且つ前記ドリフト領
域を形成する前記複数のエピタキシャル成長層に拡散で
形成された領域から成り、 前記複数のソース領域のそれぞれは前記ベース領域と反
対の導電型を有し且つ前記複数のベース領域の中に島状
に配置され、前記複数の耐圧向上用領域のそれぞれは、前記ベース領
域と同一の導電型を有して前記ドリフト領域の中に島状
に形成され且つ平面的に見て前記ベース領域の外側に分
散配置され且つ前記半導体基体の一方の主面から他方の
主面に向って柱状に延びており且つ前記ドリフト領域を
形成する前記複数のエピタキシャル成長層に拡散で形成
された領域から成り且つ前記ベース領域と同じ深さを有
し、 前記複数の補助領域のそれぞれは、前記耐圧向上用領域
の近傍の空乏層の広がりを補助するためのものであっ
て、前記耐圧向上用領域と同一の導電型を有し且つ前記
半導体基体の表面に露出するように前記ドリフト領域の
中に分散配置され且つ前記耐圧向上用領域よりも浅く形
成され且つ平面的に見て前記補助領域とこの補助領域の
近傍の４個の前記耐圧向上用領域との間の最短距離がそ
れぞれ同一になるよに前記４個の耐圧向上用領域の中心
に配置され、 前記ドレイン電極と前記ソース電極との間に電圧が印加
された時に、前記複数のベース領域、前記複数の耐圧向
上用領域、及び前記補助領域に隣接している前記ドリフ
ト領域のそれぞれの部分に生じる空乏層が互いに連続す
るように前記複数のベース領域と前記複数の耐圧向上用
領域と前記補助領域とが配置されている ことを特徴とす
る絶縁ゲート型電界効果トランジスタ。5. A drain region, a drift region and a plurality of layers.
Includes a semiconductor substrate having a over source region and a plurality of source regions and a plurality of breakdown voltage for enhancing region and a plurality of auxiliary areas, a gate insulating film, a drain electrode, a source electrode, a gate electrode, the drift region The impurity concentration of the drain region.
Having a lower impurity concentration and one of the semiconductor substrates.
The door is arranged so as to have a portion exposed to the main surface, and
The same conductivity type as the drain region is formed on the rain region.
The drain region and the semiconductor substrate.
Each of the plurality of base regions is disposed between the drift region and the other main surface of the drift region.
Islands in the drift region
And distributed from one main surface of the semiconductor substrate to the other.
And extends in a columnar manner toward the main surface of the
Diffusion into the plurality of epitaxially grown layers forming a region.
A plurality of source regions, each of the plurality of source regions being opposite to the base region.
Each of the plurality of regions has a pair of conductivity types and is arranged in an island shape in the plurality of base regions.
Islands in the drift region with the same conductivity type as the region
Formed outside the base region in plan view.
Dispersed from one main surface of the semiconductor substrate to the other.
Extending in a columnar shape toward the main surface and forming the drift region
Formed by diffusion in the plurality of epitaxial growth layers to be formed
Region having the same depth as the base region.
And, respectively, the breakdown voltage for enhancing region of the plurality of auxiliary areas
To help spread the depletion layer near the
Having the same conductivity type as the withstand voltage improving region and
The drift region is exposed so as to be exposed on the surface of the semiconductor substrate.
Dispersed inside and shallower than the withstand voltage improvement region
The auxiliary region and the auxiliary region
The shortest distance between the four adjacent withstand voltage improving regions is
The centers of the four withstand voltage improving regions so as to be the same.
Disposed, a voltage applied between the drain electrode and the source electrode
The plurality of base regions and the plurality of withstand voltage directions.
An upper area and the drift adjacent to the auxiliary area
The depletion layers that occur in each part of the
So that the plurality of base regions and the plurality of
An insulated gate field effect transistor , wherein a region and the auxiliary region are arranged .
域を囲むようにフィールドプレートと等電位リングとの
いずれか一方又は両方を有することを特徴とする請求項
１又は２又は３又は４又５は記載の絶縁ゲート型電界効
果トランジスタ。6. The semiconductor device according to claim 1, further comprising one or both of a field plate and an equipotential ring so as to surround the plurality of base regions in a plan view. 5 is the insulated gate field effect transistor described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08453799A JP3221489B2 (en) | 1999-03-26 | 1999-03-26 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08453799A JP3221489B2 (en) | 1999-03-26 | 1999-03-26 | Insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000277733A JP2000277733A (en) | 2000-10-06 |
| JP3221489B2 true JP3221489B2 (en) | 2001-10-22 |
Family
ID=13833407
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08453799A Expired - Fee Related JP3221489B2 (en) | 1999-03-26 | 1999-03-26 | Insulated gate field effect transistor |
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| Country | Link |
|---|---|
| JP (1) | JP3221489B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6878989B2 (en) | 2001-05-25 | 2005-04-12 | Kabushiki Kaisha Toshiba | Power MOSFET semiconductor device and method of manufacturing the same |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4839519B2 (en) * | 2001-03-15 | 2011-12-21 | 富士電機株式会社 | Semiconductor device |
| JP4813762B2 (en) * | 2003-12-25 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP4699692B2 (en) * | 2003-12-26 | 2011-06-15 | ローム株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2005197287A (en) * | 2003-12-26 | 2005-07-21 | Rohm Co Ltd | Semiconductor device and its fabrication process |
| JP4865194B2 (en) * | 2004-03-29 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | Super junction semiconductor device |
| US7598586B2 (en) | 2004-12-24 | 2009-10-06 | Rohm Co., Ltd. | Semiconductor device and production method therefor |
| JP5015488B2 (en) * | 2005-09-07 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2008177328A (en) * | 2007-01-18 | 2008-07-31 | Denso Corp | Semiconductor device and manufacturing method thereof |
| JP4621708B2 (en) * | 2007-05-24 | 2011-01-26 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP5718627B2 (en) * | 2010-03-15 | 2015-05-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5863574B2 (en) | 2012-06-20 | 2016-02-16 | 株式会社東芝 | Semiconductor device |
| JP6237064B2 (en) | 2013-09-30 | 2017-11-29 | サンケン電気株式会社 | Semiconductor device |
-
1999
- 1999-03-26 JP JP08453799A patent/JP3221489B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6878989B2 (en) | 2001-05-25 | 2005-04-12 | Kabushiki Kaisha Toshiba | Power MOSFET semiconductor device and method of manufacturing the same |
| US7226841B2 (en) | 2001-05-25 | 2007-06-05 | Kabushiki Kaisha Toshiba | Power MOSFET semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000277733A (en) | 2000-10-06 |
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