JP3869581B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a protective diode is connected between a gate and a source of a MOSFET or an insulated gate bipolar transistor (IGBT), and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device that can improve switching characteristics and increase reliability by increasing the impurity concentration of a gate electrode pad sufficiently without increasing a special manufacturing process, and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, for example, a vertical MOSFET has a high switching speed and is used as a high-output switching device. However, the gate threshold voltage is lowered by reducing the thickness of the gate insulating film. When this insulating film becomes thin, dielectric breakdown easily occurs even with small energy such as static electricity. Therefore, a structure in which a protective diode is inserted between the gate and the source and static electricity is discharged by the protective diode is used. This protection diode is formed as a Zener diode by forming a pn junction at the outer periphery of a gate electrode pad made of, for example, a polysilicon film, and is connected between the gate and the source. A structure in which such a protection diode is provided An example of the vertical MOSFET is shown in a sectional view in FIG.
[0003]
That is, for example, an n-type semiconductor layer (epitaxial growth layer) 21 serving as a drain region is epitaxially grown on a semiconductor substrate 21a, and a p-type body region (base region) 22 is formed by diffusing p-type impurities on the surface side. An n ^{+ -type} source region 23 is formed on the surface side of the body region 22. A gate electrode 25 is provided on the end of the body region 22 and on the surface side of the semiconductor layer 21 outside the body region 22 via a gate oxide film 24. Then, a source electrode 27 is formed of Al or the like through an interlayer insulating film 26 so as to be connected to the source region 23, and a drain electrode (not shown) is formed on the back surface of the semiconductor substrate 21a, whereby the FET portion 20 is formed. ing. As shown in the plan view of FIG. 4B, the body region 22 is formed in a matrix and a large number of transistor cells are formed, so that a power MOSFET corresponding to a large current is formed.
[0004]
Further, in the protection diode portion 30, a gate electrode pad 33 is formed of a polysilicon film through an insulating film 32 on the surface of a p-type region 31 formed by diffusion in the n-type semiconductor layer 21 in the same manner as the body region 22. As shown in the plan view of the gate electrode pad 33 in FIG. 5A, n-type layers 33a and p-type layers 33b are alternately formed on the outer periphery of the gate electrode pad 33, whereby npnpn As the connection structure, the outermost n-type layer 33b is connected to the source electrode 25 described above. As a result, as shown in an equivalent circuit diagram in FIG. 5B, a protective diode including a bidirectional Zener diode ZD is formed between the gate G and the source S of the FET. In FIG. 4, reference numeral 35 denotes a gate wiring formed by being connected to the gate electrode pad 33 by Al or the like through the interlayer insulating film 34.
[0005]
The protection diode portion is formed of the polysilicon film as described above. For example, as described in the prior art of Japanese Patent Laid-Open No. 1-220267, the protection diode portion is directly formed in the p-type region 31 described above. Things are also done.
[0006]
[Problems to be solved by the invention]
As described above, when a protective diode is formed by forming a pn junction in polysilicon such as a gate electrode pad, the Zener breakdown voltage is determined by the impurity concentration. The gate electrode pad and the like must be formed with a high resistance value. As a result, gettering of mobile ions such as Na ^{+ in} the case of an n-channel MOSFET cannot be sufficiently performed, and switching characteristics are deteriorated, and a gate threshold voltage in a reliability test varies.
[0007]
Further, in the method of forming a protection diode in the p-type region as described in JP-A-1-202867, the gate electrode pad cannot be formed, and there are similar problems, and the protection diode is formed. Therefore, it is necessary to form a mask for introducing impurities and to increase the number of manufacturing steps.
[0008]
The present invention has been made in order to solve such problems. The gettering effect can be sufficiently obtained without specially increasing the number of manufacturing steps and by forming the gate electrode pad with a high impurity concentration. It is an object of the present invention to provide a semiconductor device having a protection diode capable of improving switching characteristics and reliability, and a manufacturing method thereof.
[0009]
[Means for Solving the Problems]
In the semiconductor device of the present invention, a first conductivity type semiconductor layer and a plurality of second conductivity type base regions (body regions) are provided on the surface of the semiconductor layer, and the first conductivity type base region is provided within the first conductivity type base region. A plurality of transistor cells formed by forming a conductivity type diffusion region; a second conductivity type diffusion region formed separately from the base region on a surface of the first conductivity type semiconductor layer; A gate electrode pad formed of the same material as the gate electrode of the cell via an insulating film on the two-conductivity diffusion region, and a plurality of removal portions formed by removing the gate electrode pad in a ring shape; And a plurality of first conductivity type regions formed in the second conductivity type diffusion region below the plurality of removal portions, and the first conductivity type region and the second conductivity type diffusion region. A protection diode and a protection diode; A gate wiring provided to connect to the first conductivity type region of the ends, consists the source wiring provided to connect to the first conductivity type region of the other end of the protective diode.
[0010]
In the method of manufacturing a semiconductor device according to the present invention, (a) a mask is formed on the surface of the first conductivity type semiconductor layer, a second conductivity type impurity is introduced, and a well below the base region and gate electrode pad constituting the transistor cell (B) forming a gate oxide film on the surface of the semiconductor layer, forming a polysilicon film and introducing a first conductivity type impurity; (c) Etching the polysilicon film forms a gate electrode and a gate electrode pad portion of the transistor cell, and forms a ring-shaped groove for forming a protective diode in the gate electrode pad portion, and (d) the gate Using the electrode as a mask, a second conductivity type impurity is introduced to form a channel region forming region on the surface of the semiconductor layer, and (e) a mask is formed on the base region. By introducing electric impurities, a source cell is provided in the base region to form a transistor cell, a protective diode is formed in the second conductivity type diffusion region, and (f) an insulating film is formed on the entire surface. A back contact hole is provided, and connected to one end of the protection diode and connected to the gate electrode of the transistor cell. A gate electrode wiring is connected to the other end of the protection diode and the transistor cell. Each of the source wirings is formed so as to be connected to the source.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Next, the semiconductor device of the present invention and the manufacturing method thereof will be described with reference to the drawings.
[0012]
The semiconductor device according to the present invention has a first conductivity type (for example, n ^{− type} ), as shown in FIG. 1 which is a cross-sectional explanatory view showing a part of a protection diode portion and a transistor cell of a vertical MOSFET of one embodiment. A plurality of second conductivity type (p-type) base regions (body regions) 2 are provided on the surface of the semiconductor layer 1, and a first conductivity type (n-type) diffusion region 3 is formed in the base region. An end portion of the base region 2 sandwiched between the shaped diffusion region 3 and the semiconductor layer 1 becomes a channel region 4, and a gate electrode 6 is provided on the surface of the base region 2 with a gate oxide film 5. A transistor cell T is formed.
[0013]
A second conductivity type (p-type) diffusion region 7 is formed on the surface of the n-type semiconductor layer 1 separately from the base region 2 in a portion where the gate electrode pad 9 is formed. The p-type diffusion region 7 is provided with a gate electrode pad 9 made of polysilicon, which is the same material as the gate electrode 6 of the transistor cell T, with an insulating film 5 interposed therebetween, and a plurality of gate electrode pads 9 are removed in a ring shape. The removal part 9a is formed. Then, a plurality of first conductivity type (n-type) regions 8 are formed by diffusion or the like in the p-type diffusion region 7 below the plurality of removal portions 9a, and the n-type region 8 and the p-type diffusion region 7 A pn junction is formed and a protection diode D is provided. For example, as shown in the plan view of the p-type diffusion region 7 in FIG. 1B, the protection diode D has a ring-like shape by diffusing an n-type region 8 in the ring shape in the p-type diffusion region 7. A p-type layer and an n-type layer are alternately joined. A gate wiring 11 is provided via an interlayer insulating film 10 with Al or the like connected to the n-type region 8 at one end of the protection diode D, and connected to the n-type region 8 at the other end of the protection diode D to form a source wiring. 12 is similarly provided. The source line 12 is provided so as to be connected to the source region 3 of the transistor cell T.
[0014]
Conventionally, a p-type diffusion region 7 is provided as a well for extending the depletion layer to the outer peripheral side on the surface side of the semiconductor layer where the gate electrode pad is formed. In the present invention, this p-type diffusion region 7 is provided. The protection diode D is formed using In addition, the gate electrode pad 9 is patterned to form a ring-shaped removal portion 9a without forming a special mask, and an n-type impurity is introduced from the removal portion and diffused to form a pn junction. For example, the gate wiring 11 is provided so as to be electrically connected to the innermost n-type region 8. For example, the source wiring 12 is similarly Al connected so as to be connected to the outermost n-type region 8. Etc. are provided. As a result, a bidirectional protection diode D is connected between the gate and the source. The protection diode D can adjust its impurity concentration to some extent independently, can set a necessary Zener breakdown voltage, has a desired withstand voltage, and withstands surges such as static electricity of higher voltage. Can be discharged through the protective diode D, and the thin gate oxide film can be protected.
[0015]
The gate electrode pad 9 is provided with a ring-shaped removal portion 9a. However, since the gate electrode pad 9 is not related to the protective diode, the impurity concentration can be sufficiently increased and the gettering action can be sufficiently performed. . Further, in FIG. 1A, the gate wiring on the gate electrode pad 9 is narrowed, but this region can be widened so that wire bonding can be performed, and the gate electrode pad 9 has a ring shape. However, since it is electrically insulated, there is no problem. Note that even if the gate wiring 11 and the gate electrode pad 9 cannot be directly connected, they may be connected to the gate electrode somewhere in the gate wiring, and the gate finger portion extending from the gate wiring is connected to the gate electrode. You may do it.
[0016]
As shown in FIG. 1A, the cell portion T of the transistor is formed by introducing a p-type dopant into the surface side of an n ⁻ -type semiconductor layer 1 epitaxially grown on an n ^{+ -type} semiconductor substrate 1a to form a base region ( Body region) 2 is provided in a matrix, and an n-type impurity is introduced into the outer periphery of base region 2 to form source region 3, and base region 2 sandwiched between source region 3 and n ⁻ -type semiconductor layer 1. The gate electrode 6 is formed on the peripheral channel region 4 with the gate oxide film 5 interposed therebetween. The base region 5 is provided in a matrix form as described above, and a large number of transistor cells T are formed in parallel to form a vertical MOSFET from which a large current can be obtained. The source wiring 12 and the gate wiring 11 are formed by providing the interlayer insulating film 10 made of phosphor glass or the like on the gate electrode 6, opening a contact hole, and providing Al or the like by vacuum deposition or the like. Similarly, a drain electrode (not shown) is formed on the back surface of the semiconductor substrate 1a by an electrode metal by vapor deposition. Note that the gate wiring 11 is provided to partially connect the gate electrode of the transistor cell T far from the gate electrode pad G to lower the resistance.
[0017]
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2A, for example, epitaxial growth is performed on the surface of an n ^{+ type} semiconductor substrate 1a with a specific resistance of about 0.1 to several tens of Ω · cm and a thickness of about several μm to several tens of μm. A mask is formed on the surface of the n-type semiconductor layer 1 formed by the step of introducing p-type impurities, and the base region 2 constituting the transistor cell and the p-type diffusion region 7 constituting the well under the gate electrode pad are simultaneously formed. Form. The base region 2 and the p-type diffusion region 7 are formed by, for example, forming an oxide film 15 of about several thousand Å, providing a resist film (not shown), patterning, and etching as shown in FIG. The mask 15 is further formed by forming a through oxide film 16 of about several hundreds of liters, doping a p-type dopant such as boron (B) by ion implantation, and performing a heat treatment.
[0018]
Next, as shown in FIG. 2B, a gate oxide film 4 is formed on the surface of the semiconductor layer 1, and a polysilicon film 6a is formed by, for example, a CVD method. Then, a phosphorus deposition process (introduction of the first conductivity type impurity) is performed.
[0019]
Next, as shown in FIG. 2C, the polysilicon film 6a is etched to form the gate electrode 6 and the gate electrode pad 9 of the transistor cell, and the gate electrode pad 9 is formed with a protection diode. A ring-shaped groove 9a is formed. The polysilicon film 6a can be patterned, for example, by providing a resist film (not shown) on the entire surface of the polysilicon film 6a, performing patterning by a photolithography process, and etching using the resist film as a mask.
[0020]
Next, as shown in FIG. 2 (d), a p-type impurity is introduced using the gate electrode 6 as a mask to form a channel region forming region 2 a on the surface of the semiconductor layer 1. The channel region forming region 2a can be formed by introducing a p-type impurity such as boron (B) by ion implantation or the like and then performing diffusion as shown in FIG. 2D. .
[0021]
Thereafter, as shown in FIG. 3E, a mask 17 is formed on the base region 2 by a photolithography process similar to that described above using a photoresist or the like, and an n-type impurity is introduced, whereby a source in the base region 2 is obtained. The region 3 is provided to form the transistor cell T, and the n-type region 8 is formed in the p-type region 7 to form the protective diode D. This n-type region (source region) can also be formed by ion implantation of phosphorus (P) or the like and heat treatment.
[0022]
Thereafter, as shown in FIG. 3F, a PSG film is formed on the entire surface by, for example, atmospheric pressure CVD, and then an interlayer insulating film 10 provided with contact holes 10a is formed. The contact hole 10a can also be formed by providing a resist film (not shown), patterning, and etching. Thereafter, the gate electrode wiring 11 is connected so as to be connected to one end (for example, the center) of the protection diode D and to the gate electrode 6 of the transistor cell T, and the other end (for example, the outer peripheral side) of the protection diode D. And a source wiring 12 formed so as to be connected to the source region 3 of the transistor cell T, thereby obtaining a vertical MOSFET with a protective diode having a structure shown in FIG. . The gate wiring 11 and the source wiring 12 can be formed, for example, by depositing Al or the like on the entire surface by a vacuum deposition method and providing a resist film and patterning as described above.
[0023]
According to the present invention, since the protection diode D is formed in the second conductivity type region formed below the electrode pad while using the polysilicon film of the gate electrode pad, the impurity of the gate electrode pad is formed. The concentration can be freely controlled, and the gate electrode can have a sufficiently low resistance. As a result, the switching speed can be improved and the variation of the gate threshold voltage in the reliability test can be suppressed (for example, in an n-channel MOSFET, a low concentration of n-type polysilicon results in gettering against Na ⁺ mobile ions. There is a problem that the ring effect is weakened and the threshold voltage is lowered).
[0024]
The above example is an example of a vertical MOSFET, but the same applies to an insulated gate bipolar transistor (IGBT) in which a bipolar transistor is further formed in the vertical MOSFET.
[0025]
【The invention's effect】
According to the present invention, the impurity concentration of the polysilicon film serving as the gate electrode can be sufficiently reduced without being limited, so that the switching characteristics are improved and the characteristics such as the gate threshold value in the reliability test are stabilized. Reliability can be ensured, and reliability is improved.
[0026]
Further, when forming the protection diode, it is not necessary to add a special process and can be formed at the same time as the manufacturing process of the transistor cell, so that the number of steps is not increased and a semiconductor device with the protection diode can be obtained at a low cost. It is done.
[Brief description of the drawings]
FIG. 1 is a cross-sectional explanatory view of a vertical MOSFET as an embodiment of a semiconductor device of the present invention and a plan explanatory view of a protective diode portion.
2 is a cross-sectional explanatory view showing a manufacturing process of the vertical MOSFET of FIG. 1. FIG.
3 is a cross-sectional explanatory view showing the manufacturing process of the vertical MOSFET of FIG. 1; FIG.
FIG. 4 is an explanatory diagram of a cross section and a plan view of a vertical MOSFET provided with a conventional protection diode.
FIG. 5 is an explanatory diagram of an electrode pad provided with the protection diode of FIG. 4;
[Explanation of symbols]
1 n-type semiconductor layer 2 base region 3 source region 6 gate electrode 7 p-type diffusion region 8 n-type region 9 gate electrode pad D protection diode T transistor cell

Claims (2)

Formed by forming a first conductivity type semiconductor layer and a plurality of second conductivity type base regions on the surface of the semiconductor layer, and forming a first conductivity type diffusion region in the second conductivity type base region. A plurality of transistor cells, a second conductivity type diffusion region formed separately from the base region on the surface of the first conductivity type semiconductor layer, and an insulating film on the second conductivity type diffusion region A gate electrode pad made of the same material as the gate electrode of the cell, a plurality of removal portions formed by removing the gate electrode pad in a ring shape, and the bottom of the plurality of removal portions A plurality of first conductivity type regions formed in the second conductivity type diffusion region, a protection diode formed by the first conductivity type region and the second conductivity type diffusion region, and one end portion of the protection diode; Connected to the first conductivity type region A gate wiring kicked, the semiconductor device comprising a source wiring provided to connect to the first conductivity type region of the other end of the protective diode. (A) A second conductivity type diffusion region which forms a mask on the surface of the first conductivity type semiconductor layer and introduces a second conductivity type impurity to form a base region constituting a transistor cell and a well under a gate electrode pad Forming at the same time,
(B) forming a gate oxide film on the surface of the semiconductor layer, forming a polysilicon film, and introducing a first conductivity type impurity;
(C) etching the polysilicon film to form a gate electrode and a gate electrode pad portion of the transistor cell, and forming a ring-shaped groove for forming a protective diode in the gate electrode pad portion;
(D) introducing a second conductivity type impurity using the gate electrode as a mask to form a channel region forming region on the surface of the semiconductor layer;
(E) A mask is formed on the base region and a first conductivity type impurity is introduced, thereby providing a source region in the base region to form a transistor cell and protecting the second conductivity type diffusion region. Forming a diode,
(F) An insulating film is formed on the entire surface, a contact hole is provided, a gate electrode wiring is connected to one end of the protection diode and to the gate electrode of the transistor cell, and the other end of the protection diode And forming a source wiring so as to be connected to the source of the transistor cell and to the source of the transistor cell.

Images