JPH0282580A - Vertical mos fet - Google Patents
Vertical mos fetInfo
- Publication number
- JPH0282580A JPH0282580A JP63234109A JP23410988A JPH0282580A JP H0282580 A JPH0282580 A JP H0282580A JP 63234109 A JP63234109 A JP 63234109A JP 23410988 A JP23410988 A JP 23410988A JP H0282580 A JPH0282580 A JP H0282580A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- gate
- diffusion region
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 229910018125 Al-Si Inorganic materials 0.000 claims 2
- 229910018520 Al—Si Inorganic materials 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は縦型ＭＯＳ Ｆ ＥＴの耐圧向−ヒとオン抵抗
低減に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improving voltage resistance and reducing on-resistance of a vertical MOSFET.
（ロ）従来の技術
縦型Ｄ Ｓ Ａ （Ｄｉｆｆｕｓｉｏｎ ５ｅｌｆ Ａ
ｌｉｇｎｍｅｎｔ ）構造の縦型ＭＯＳ Ｆ ＥＴは一
平面上に多数の素子（セル）を等間隔に並べることによ
り高耐圧化と大電流化が図られ、高電圧高速スイッチン
グ用として使用されている（特開昭６１−８０８５９、
ＨＯＩＩ、 ２９／７８）。(b) Conventional technology Vertical DSA (Diffusion 5elf A)
Vertical MOSFETs with a lignment) structure have a large number of elements (cells) arranged at regular intervals on one plane to achieve high withstand voltage and large current, and are used for high-voltage, high-speed switching (especially Kaisho 61-80859,
HOII, 29/78).
断る構造の縦型ＭＯ５ＦＥＴは、第３図及び第４図に示
す如く、底部に高濃度Ｎ３型層（１）を有するＮ−型シ
リコン基体（２）をドレインとして、その表面上に所定
の間隔でゲート電極（ポリＳｉゲート）（３）が配置さ
れ、このゲート電極（３〉の下にチャンネル部を作るよ
うに基体（２）表面にＰ型拡散領域（４）とＮ＋型ソー
ス領域〈５）を形成したもので、ゲートへの電圧印加に
よってゲート下のＰ型拡散領域（４）（チャンネル部）
を通るドレイン電流ＩＤｓを制御するようにＭＯＳＦＥ
Ｔを動作させるものである。As shown in FIGS. 3 and 4, a vertical MO5FET with a vertical structure has an N-type silicon substrate (2) having a high concentration N3 type layer (1) at the bottom as a drain, and a drain at a predetermined interval on its surface. A gate electrode (poly-Si gate) (3) is arranged, and a P-type diffusion region (4) and an N+ type source region (5) are formed on the surface of the substrate (2) to form a channel section under this gate electrode (3). ), and by applying voltage to the gate, the P-type diffusion region (4) (channel part) under the gate is formed.
MOSFE to control the drain current IDs through
This is what makes T operate.
従来の縦型ＭＯＳ Ｆ ＥＴの各セル（６）の形状は、
第３図に示すように四角形となって等間隔で縦横方向に
配列され、四角形の中心からソース電極を取出し、ゲー
ト電極（３）からはその上の絶縁膜のスルーホールを通
して共通のゲート電極を取出すようになっている。The shape of each cell (6) of a conventional vertical MOS FET is as follows:
As shown in Figure 3, they are arranged in a rectangular shape at equal intervals in the vertical and horizontal directions, the source electrode is taken out from the center of the rectangle, and the common gate electrode is connected from the gate electrode (3) through a through hole in the insulating film above it. It is designed to be taken out.
そして、各セル（６）のチャンネル部形成にあたっては
、ゲート電極（３）を利用したセルファライン技術によ
りＰ型拡散領域（４）とソース領域（５）を形成するが
、ゲート電極（３）によるセル（６）形状が四角形を成
すことにより、セル（６）のコーナー部（７）への不純
物拡散が他の部分（辺部）への不純物拡散に比べて少な
く、従ってコーナー部（７）のチャンネル部は凸型の球
面形状のＰＮ接合を形成し、逆バイアス時の電界強度が
他よりも大きくなる。その為、セル（６）のコーナー部
（７）で電界集中を発生し、この部分における耐圧が縦
型ＭＯ８ＦＥＴの耐圧を決定していた。尚、（８）はチ
ャンネル部の輪郭を示す。そのうえ、不純物濃度が薄く
なるので、コーナー部（７）が他の辺部より早くオンし
、リークが発生したり、動作上電流分布が不均一となる
為低Ｖａｓ＜：ｏｆｆ）化の妨げになっていた。Then, in forming the channel part of each cell (6), a P-type diffusion region (4) and a source region (5) are formed by self-line technology using the gate electrode (3). Since the cell (6) has a rectangular shape, impurity diffusion into the corner portion (7) of the cell (6) is smaller than impurity diffusion into other portions (side portions). The channel portion forms a convex spherical PN junction, and the electric field strength at the time of reverse bias is larger than that of other parts. Therefore, electric field concentration occurs at the corner portion (7) of the cell (6), and the breakdown voltage at this portion determines the breakdown voltage of the vertical MO8FET. Note that (8) shows the outline of the channel portion. In addition, since the impurity concentration becomes thinner, the corner portion (7) turns on earlier than the other side portions, causing leakage and non-uniform current distribution during operation, which hinders lowering Vas<:off). It had become.
（ハ）発明が解決しようとする課題
このように、従来の縦型ＭＯＳＦＥＴはセル（６）のコ
ーナー部（７）で耐圧が決定されてしまう欠点があった
。また、コーナー部（７）のＰＮ接合の曲率を緩和する
為チャンネル部を浅くすることができず、従ってセル（
６）の微細化が難しい欠点があった。更には微細化が困
難である為、ＭＯＳＦＥＴのチャンネル幅ＧＷ（セルの
周囲長の総和）を増大してオン抵抗Ｒ□（ｏｎ ）を減
少することも困難である欠点があった。(c) Problems to be Solved by the Invention As described above, the conventional vertical MOSFET has the drawback that the breakdown voltage is determined by the corner portion (7) of the cell (6). Furthermore, in order to reduce the curvature of the PN junction at the corner section (7), the channel section cannot be made shallow; therefore, the cell (
6) had the drawback that it was difficult to miniaturize it. Furthermore, since miniaturization is difficult, it is also difficult to reduce the on-resistance R□ (on) by increasing the MOSFET channel width GW (total circumferential length of the cell).
（ニ）課題を解決するための手段
本発明は斯上した欠点に鑑み、チャンネル部の】−ナ一
部（２３）が形成するＰＮ接合が凹型の曲面を形成する
ようにＰ型拡散領域（１３）を格子状に形成し、ゲート
電極（１５）は夫々が独立するようアイランド状に形成
することにより、コーナー部（２３）での耐圧劣化を防
止した縦型ＭＯＳＦＥＴを提供するものである。(d) Means for Solving the Problems In view of the above-mentioned drawbacks, the present invention provides a P-type diffusion region ( 13) is formed in a lattice shape, and the gate electrodes (15) are formed in an island shape so that each gate electrode is independent, thereby providing a vertical MOSFET in which breakdown voltage deterioration at the corner portions (23) is prevented.
更に、夫々が独立したゲート電極（１５）を接続電極（
１７）で電気的に接続することにより、多層配線構造を
用いることの無い、簡略化した構造の縦型ＭＯ８ＦＥＴ
を提供するものである。Furthermore, each independent gate electrode (15) is connected to a connecting electrode (
17) Vertical MO8FET with a simplified structure that does not require a multilayer wiring structure by electrically connecting
It provides:
（＊）作用
本発明によれば、コーナー部（２３）のＰＮ接合が凹型
の曲面形状を成すので、電界が分散され、集中は起らな
い。また、チャンネルのコーナー８Ｉζ（７）は他の部
分より不純物濃度が高くなる為、ノーク電流源にはなら
ず、低Ｖ ６ｓ （ｏｆｆ ）化が容易である。(*) Effect According to the present invention, the PN junction at the corner portion (23) has a concave curved shape, so the electric field is dispersed and no concentration occurs. In addition, since the impurity concentration at the corner 8Iζ(7) of the channel is higher than other parts, it does not become a nok current source, and it is easy to lower V 6s (off).
また、夫々のゲート電極＜１５）が接続電極（１７）で
接続きれているので、夫々のゲート電極（１５）を電気
的に共通にできる。Furthermore, since the respective gate electrodes (<15) are connected by the connection electrode (17), the respective gate electrodes (15) can be electrically shared.
（へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図及び第２図は本発明の縦型ＭＯＳＦＥＴを示す゛
Ｆ面図及びＡＡ線断面図を示す。（１１）は裏面にドレ
イン電極が設けられる比較的低比抵抗のＮ＋型シリコン
半導体基板、（１２）は基板（１１）表面に設けられ共
通のドレイン領域となる比較的高比抵抗のＮ型エピタキ
シャル層、＜１３）はＮ型エピタキシャル層（１２）の
表面に格子状に形成したＰ型の拡散領域、（１４）はＰ
型拡散領域（１３）表面の一部に形成したＮ”型拡散領
域（ソース領域）、（１５）はソース領域（１４）と露
出したＮ型エピタキシャル層（１２）とに挾まれたＰ型
拡散領域（１３）が形成するチャンネル領域の上にゲー
ト酸化膜（１６）を介して形成したゲート電極、（１７
）は夫々独立したゲート電極を橋絡する接続電極、（１
８）はＰ型拡散領域（１３）とＮ″″型ソース領域（１
４）の双方にコンタクトするソース電極、（１９）はそ
のコンタクトホールを夫々示す。FIGS. 1 and 2 show a cross-sectional view taken along the line AA and F, respectively, showing the vertical MOSFET of the present invention. (11) is a relatively low specific resistance N+ type silicon semiconductor substrate with a drain electrode provided on the back surface, and (12) is a relatively high specific resistance N type epitaxial substrate provided on the surface of the substrate (11) and serves as a common drain region. layer, <13) is a P-type diffusion region formed in a lattice shape on the surface of the N-type epitaxial layer (12), and (14) is a P-type diffusion region formed in a lattice pattern on the surface of the N-type epitaxial layer (12).
N” type diffusion region (source region) formed on a part of the surface of the type diffusion region (13), (15) is a P type diffusion region sandwiched between the source region (14) and the exposed N type epitaxial layer (12). A gate electrode (17) is formed on the channel region formed by the region (13) via a gate oxide film (16).
) are connection electrodes that bridge independent gate electrodes, (1
8) is a P type diffusion region (13) and an N'' type source region (1
4), and (19) indicate the contact holes thereof.
Ｐ型拡散領域（１３）はエピタキシャル層（１２）表面
に格子状に形成するので、その結果Ｎ型エピタキシャル
層（１２）はＰ型拡散領域（１３）に囲まれて表面に露
出し、露出部分がタイル状に点在する。Since the P-type diffusion region (13) is formed in a lattice pattern on the surface of the epitaxial layer (12), as a result, the N-type epitaxial layer (12) is surrounded by the P-type diffusion region (13) and exposed at the surface, and the exposed portion are scattered like tiles.
ゲート電極（１５）は、−例として四角形状を成し前記
格子状パターンの網目に相当する部分、つまり前記エピ
タキシャル層（１２）の露出部分を覆う様にして縦横に
配設される。そして、ゲート電極（Ｎ５）の４個のコー
ナー部には夫々斜め方向に延在する接続電極（１７）が
設けられ、これが近接するゲート電極（１５）を夫々接
続することにより、全てのゲート電極（１５）を同電位
とする。The gate electrodes (15) have, for example, a rectangular shape and are arranged vertically and horizontally so as to cover portions corresponding to the meshes of the lattice pattern, that is, exposed portions of the epitaxial layer (12). Connection electrodes (17) extending diagonally are provided at each of the four corners of the gate electrode (N5), and by connecting the adjacent gate electrodes (15), all the gate electrodes are connected to each other. (15) are at the same potential.
ソース電極（１８）は、酸化膜（２０）を介してゲート
電極（１５）を覆う様に形成され、接続電極（１７）を
避ける為ゲート電極（１５）の側辺部でＰ型拡散領域（
１３）とＮ３型ソース領域（１４）の双方にコンタクト
する。The source electrode (18) is formed to cover the gate electrode (15) via the oxide film (20), and the P-type diffusion region (
13) and the N3 type source region (14).
ゲート電極（１５）下のチャンネル部形成にあたっては
、先ずエピタキシャルＢ（１２）表面にＰ型拡散領域（
１３）のうちの深い領域を形成する為のＰ型不純物（ボ
ロン等）を選択的にデボジ・７トした後、エピタキシャ
ル層（１２〉表面に膜厚１０００人程度０ゲート酸化膜
（１６）と膜厚５０００乃至８０００人のポリシリコン
層を生成し、このポリシリコンＪａをアイランド状にパ
ターニングすることでゲート電極〈１５〉を形成し、ゲ
ート電極（１５）をマスクとしたセルファライン技術に
より全面にＰ型不純物（ポロン等）をイオン注入し、先
に導入したＰ型不純物と共にこのＰ型不純物を熱拡散し
てＰ型拡散領域（１３）を形成し、今度はゲート電極（
１５）とパターニングしたホトレジスト膜をマスクとし
たセルファライン技術によりＮ型不純物（リン等）をイ
オン注入してＮ＋型ソース領域（１４）を形成し、その
結果Ｐ型拡散領域（１３〉とＮ１型ソース領域（１４）
が規定するゲート電極（１５）下のＰ型拡散領域（１３
〉がチャンネル部となる。そして、ゲート電極（１５〉
を覆う様にＣＶＤｌ９化膜（２０）を生成し、Ｐ型拡散
領域（１３）上に夫々コンタクトホール（１９）を形成
した後全面に電極配ｍ層を形成し、この電極配線層をパ
ターニングしてソース電極（１８）を形成することによ
り本願のＭＯＳ Ｆ ＥＴを得る。尚、電極配！！層材
料としてはアルミニウム（Ａ１）、アルミニウム・シリ
コン（Ａｌ−Ｓｉ）、タングステン（Ｗ）等が選択され
る。In forming the channel section under the gate electrode (15), first a P-type diffusion region (
After selectively depositing P-type impurities (boron, etc.) to form the deep region of 13), a gate oxide film (16) with a thickness of about 1000 is deposited on the surface of the epitaxial layer (12). A polysilicon layer with a thickness of 5,000 to 8,000 layers is generated, and this polysilicon Ja is patterned into an island shape to form a gate electrode (15). A P-type impurity (such as poron) is ion-implanted, and this P-type impurity is thermally diffused together with the previously introduced P-type impurity to form a P-type diffusion region (13), and then a gate electrode (13) is formed.
15) and using the patterned photoresist film as a mask, an N-type impurity (such as phosphorus) is ion-implanted to form an N+-type source region (14), and as a result, a P-type diffusion region (13) and an N1-type Source area (14)
P-type diffusion region (13) under the gate electrode (15) defined by
> is the channel part. Then, the gate electrode (15)
A CVD l9 film (20) is formed to cover the P-type diffusion region (13), contact holes (19) are formed respectively on the P-type diffusion region (13), an electrode wiring layer is formed on the entire surface, and this electrode wiring layer is patterned. By forming a source electrode (18), the MOSFET of the present invention is obtained. In addition, the electrode arrangement! ! Aluminum (A1), aluminum-silicon (Al-Si), tungsten (W), etc. are selected as the layer material.
従って、ソース領域（１４）を形成するＮ型不純物は接
続電極（１７）の下にはイオン注入されないので、ソー
ス領域（１４）はリング形状にならず、ゲート電極（１
５）の周囲に分割して形成される。ゲート電極（１５）
のコーナー部分は本来あまりドレイン電流Ｉｏに関与し
ないので、ソース領域（１４）がチャンネル部分の周囲
長より短くならない限り電流容量が減少することは無い
。Therefore, the N-type impurity forming the source region (14) is not ion-implanted under the connection electrode (17), so the source region (14) does not have a ring shape and the gate electrode (14) does not have a ring shape.
5) is divided and formed around the area. Gate electrode (15)
Since the corner portions of the source region (14) do not originally contribute much to the drain current Io, the current capacity will not decrease unless the source region (14) becomes shorter than the circumference of the channel portion.
斯る構成によれば、チャンネル部がアイランド状に形成
されたゲート電極り１５）の内側へ形成される為、四角
形状のコーナー部のＰＮ接合は内側へ折れ曲った形状を
成し、従って第１図に、示す如く、前記ＰＮ接合からエ
ピタキシャル層（１２ＭＩｌ！Ｉへ形成される空乏層（
２１）も前記ＰＮ接合の形状に沿ったものとなる。この
様な形状では、エピタキシャル層（１２）からＰ型拡散
領域（１３）への電界は集中せず、前記空乏層（２１）
の凹曲面状に沿って分散することになる。その為、本願
のＭＯＳＦＥＴの耐圧は純粋にゲート電極（１５）側辺
のチャンネル部でのパンチスルー又はツェナー降伏電圧
で決マリ、コーナー部での耐圧劣化は無い。Ｐ型拡散領
域（１３）の深い部分もまた、格子状に形成した結果コ
ーナー部分が凹曲面を成すので、前記耐圧を劣化させな
い。According to such a configuration, since the channel portion is formed inside the gate electrode layer 15) formed in an island shape, the PN junction at the square corner portion has a shape bent inward, and therefore the As shown in Figure 1, a depletion layer (
21) also follows the shape of the PN junction. With such a shape, the electric field from the epitaxial layer (12) to the P-type diffusion region (13) is not concentrated, and the depletion layer (21)
It will be dispersed along the concave surface shape. Therefore, the breakdown voltage of the MOSFET of the present application is determined purely by the punch-through or Zener breakdown voltage at the channel portion on the side of the gate electrode (15), and there is no breakdown voltage deterioration at the corner portions. The deep portion of the P-type diffusion region (13) is also formed in a lattice shape, and as a result, the corner portion forms a concave curved surface, so that the withstand voltage does not deteriorate.
また、マルチゲート構造としながら接続電極（１７）に
よって全てのゲート電極（１５）を電気的に接続できる
ので、配線がポリシリコン層とソース１ヒ極（１Ｂ）層
だけで済む他、ソース電極（１８）を全面に形成しゲー
ト電極（１５）を囲むようにコンタクトできるので、ゲ
ート電極（１５）の周囲から効率的にドレイン電流ＩＯ
を供給できる。In addition, all the gate electrodes (15) can be electrically connected by the connection electrode (17) while having a multi-gate structure, so the wiring only requires the polysilicon layer and the source 1 hypode (1B) layer, and the source electrode ( 18) can be formed on the entire surface and can be contacted so as to surround the gate electrode (15), so that the drain current IO can be efficiently transferred from the periphery of the gate electrode (15).
can be supplied.
（ト）発明の詳細
な説明した如く、本発明によればマルチゲート構造とし
ゲート電極（１５）のコーナー部分における電界集中を
防止したので、耐圧が向上し且つ微細化することでＭＯ
ＳＦＥＴのチャンネル幅を増大し、オン抵抗Ｒｏｓ（ｏ
ｎ）を低減できる利点を有する。(G) As described in detail, the present invention has a multi-gate structure and prevents electric field concentration at the corner portions of the gate electrode (15).
By increasing the channel width of SFET, the on-resistance Ros(o
It has the advantage of being able to reduce n).
また、マルチゲート構造としながら接続電極（１７）を
設けることにより、構成が簡単でソース電極（１８）が
ゲート電極（１５）を囲む様にコンタクトできる構造を
実現できる利点をも有する。Further, by providing a connection electrode (17) while forming a multi-gate structure, there is an advantage that the structure is simple and a structure in which the source electrode (18) can contact the gate electrode (15) so as to surround it can be realized.
第１図及び第２図は夫々本発明の一実施例を説明する為
の平面図及び断面図、第３図及び第４図は従来例を説明
する為の平面図及び断面図である。1 and 2 are a plan view and a sectional view, respectively, for explaining an embodiment of the present invention, and FIGS. 3 and 4 are a plan view and a sectional view, respectively, for explaining a conventional example.
Claims (4)
主表面の一部に第２導電型の拡散領域が形成され、 前記拡散領域表面の一部に第１導電型のソース領域が形
成され、 前記ソース領域と前記基体とに挾まれたチャンネル領域
となるべき第２導電型拡散領域上にゲート絶縁膜を介し
てゲート電極が形成され、 前記ソース領域と第２導電型拡散領域の双方にコンタク
トするソース電極が形成された縦型ＭＯＳＦＥＴにおい
て、 前記第２導電型拡散領域を格子状に形成しその網目部分
に夫々が独立するようにアイランド状の前記ゲート電極
を配設すると共に、 前記ゲート電極の一部に前記ゲート電極と連続する接続
電極を設け、前記独立したゲート電極を前記接続電極で
橋絡したことを特徴とする縦型ＭＯＳＦＥＴ。(1) A semiconductor substrate of a first conductivity type is used as a drain, a diffusion region of a second conductivity type is formed in a part of one main surface thereof, and a source region of a first conductivity type is formed in a part of the surface of the diffusion region. , a gate electrode is formed via a gate insulating film on a second conductivity type diffusion region sandwiched between the source region and the base body and to become a channel region, and a gate electrode is formed on both the source region and the second conductivity type diffusion region. In a vertical MOSFET in which a contacting source electrode is formed, the second conductivity type diffusion region is formed in a lattice shape, and the island-shaped gate electrodes are arranged in the mesh portion so that each one is independent, and the gate electrode A vertical MOSFET characterized in that a connection electrode continuous with the gate electrode is provided in a part of the electrode, and the independent gate electrode is bridged with the connection electrode.
層で、前記ソース電極は次層のＡｌ又はＡｌ−Ｓｉ層で
構成されていることを特徴とする請求項第１項に記載の
縦型ＭＯＳＦＥＴ。(2) The vertical structure according to claim 1, wherein the gate electrode and the connection electrode are made of the same polysilicon layer, and the source electrode is made of the next layer of Al or Al-Si. Type MOSFET.
れると共に、前記接続電極が前記ゲート電極のコーナー
部から斜め方向に延在し、且つ４個のゲート電極が共通
の接続電極で橋絡されていることを特徴とする請求項第
１項に記載の縦型ＭＯＳＦＥＴ。(3) The gate electrodes have a rectangular shape and are arranged vertically and horizontally, and the connection electrode extends diagonally from a corner of the gate electrode, and the four gate electrodes are a common connection electrode. 2. The vertical MOSFET according to claim 1, wherein the vertical MOSFET is bridged.
層で、前記ソース電極は次層のＡｌ又はＡｌ−Ｓｉ層で
構成され、且つ前記ソース電極は前記ゲート電極のコー
ナー部分を除く４辺４箇所でコンタクトし前記ゲート電
極を覆う様に形成したことを特徴とする請求項第３項に
記載の縦型ＭＯＳＦＥＴ。(4) The gate electrode and the connection electrode are made of the same polysilicon layer, the source electrode is made of the next layer of Al or Al-Si, and the source electrode is made of the four sides of the gate electrode excluding the corner portions. 4. The vertical MOSFET according to claim 3, wherein the vertical MOSFET is formed so as to make contact at four locations and cover the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234109A JPH07118542B2 (en) | 1988-09-19 | 1988-09-19 | Vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234109A JPH07118542B2 (en) | 1988-09-19 | 1988-09-19 | Vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282580A true JPH0282580A (en) | 1990-03-23 |
| JPH07118542B2 JPH07118542B2 (en) | 1995-12-18 |
Family
ID=16965772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63234109A Expired - Fee Related JPH07118542B2 (en) | 1988-09-19 | 1988-09-19 | Vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118542B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1143526A2 (en) * | 2000-04-06 | 2001-10-10 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor and method of manufacturing the same |
| WO2011122670A1 (en) * | 2010-03-30 | 2011-10-06 | ローム株式会社 | Semiconductor device |
| WO2012105609A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9214572B2 (en) | 2013-09-20 | 2015-12-15 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US9991376B2 (en) | 2013-09-20 | 2018-06-05 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56116669A (en) * | 1980-02-19 | 1981-09-12 | Nec Corp | Field effect transistor |
-
1988
- 1988-09-19 JP JP63234109A patent/JPH07118542B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56116669A (en) * | 1980-02-19 | 1981-09-12 | Nec Corp | Field effect transistor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1143526A2 (en) * | 2000-04-06 | 2001-10-10 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor and method of manufacturing the same |
| EP1143526A3 (en) * | 2000-04-06 | 2005-09-28 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor and method of manufacturing the same |
| WO2011122670A1 (en) * | 2010-03-30 | 2011-10-06 | ローム株式会社 | Semiconductor device |
| JP2011211020A (en) * | 2010-03-30 | 2011-10-20 | Rohm Co Ltd | Semiconductor device |
| US10727318B2 (en) | 2010-03-30 | 2020-07-28 | Rohm Co., Ltd. | Semiconductor device VDMOS having a gate insulating film having a high dielectric constant portion contacting the drift region for relaxing an electric field generated in the gate insulating film |
| WO2012105609A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor device |
| US9184286B2 (en) | 2011-02-02 | 2015-11-10 | Rohm Co., Ltd. | Semiconductor device having a breakdown voltage holding region |
| US9406744B2 (en) | 2011-02-02 | 2016-08-02 | Rohm Co., Ltd. | Semiconductor device having a breakdown voltage holding region |
| US9698216B2 (en) | 2011-02-02 | 2017-07-04 | Rohm Co., Ltd. | Semiconductor device having a breakdown voltage holding region |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07118542B2 (en) | 1995-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5008725A (en) | Plural polygon source pattern for MOSFET | |
| CA1175953A (en) | Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions | |
| US5130767A (en) | Plural polygon source pattern for mosfet | |
| US7732869B2 (en) | Insulated-gate semiconductor device | |
| JPH03270273A (en) | Semiconductor device and its manufacture | |
| JP2002141507A (en) | Semiconductor device and its manufacturing method | |
| JPH03219678A (en) | Semiconductor device | |
| JP2003142698A (en) | Power semiconductor device | |
| JP3221489B2 (en) | Insulated gate field effect transistor | |
| JPH0354868A (en) | Mos type semiconductor device | |
| JP2877408B2 (en) | Conduction modulation type MOSFET | |
| US6703665B1 (en) | Transistor | |
| JP4122113B2 (en) | High breakdown strength field effect transistor | |
| JPH01238173A (en) | Power mosfet | |
| US6563169B1 (en) | Semiconductor device with high withstand voltage and a drain layer having a highly conductive region connectable to a diffused source layer by an inverted layer | |
| JPH0282580A (en) | Vertical mos fet | |
| JPH01238174A (en) | Vertical mosfet | |
| JP3482959B2 (en) | Semiconductor element | |
| JP3221673B2 (en) | High voltage semiconductor device | |
| JP3738127B2 (en) | High voltage semiconductor device | |
| JPH02237162A (en) | Insulated gate bipolar transistor | |
| JP3768656B2 (en) | Semiconductor device | |
| JP2003332588A (en) | Semiconductor element | |
| JP2002141505A (en) | Field-effect transistor | |
| JPH0821714B2 (en) | Insulated gate field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |