WO2006082618A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2006082618A1
WO2006082618A1 PCT/JP2005/001331 JP2005001331W WO2006082618A1 WO 2006082618 A1 WO2006082618 A1 WO 2006082618A1 JP 2005001331 W JP2005001331 W JP 2005001331W WO 2006082618 A1 WO2006082618 A1 WO 2006082618A1
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WIPO (PCT)
Prior art keywords
region
carrier extraction
extraction region
semiconductor layer
conductivity type
Prior art date
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PCT/JP2005/001331
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French (fr)
Japanese (ja)
Inventor
Toshiyuki Takemori
Yuji Watanabe
Fuminori Sasaoka
Kazushige Matsuyama
Kunihito Ohshima
Masato Itoi
Original Assignee
Shindengen Electric Manufacturing Co., Ltd.
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Application filed by Shindengen Electric Manufacturing Co., Ltd. filed Critical Shindengen Electric Manufacturing Co., Ltd.
Priority to PCT/JP2005/001331 priority Critical patent/WO2006082618A1/en
Priority to JP2007501456A priority patent/JP4794546B2/en
Publication of WO2006082618A1 publication Critical patent/WO2006082618A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • the present invention relates to a semiconductor device having a trench gate type MOS (Metal-Oxide-Semiconductor) structure and a method for manufacturing the same.
  • MOS Metal-Oxide-Semiconductor
  • a trench gate structure formed has been widely applied to various power sources such as a DC-DC converter in recent years.
  • the breakdown voltage is improved by improving the structure related to the gate electrode.
  • a parasitic diode is formed by a PN junction between a drain layer and a base diffusion layer.
  • FIG. 13 shows a cross-sectional structure of a conventional semiconductor device 2 having a power MOSFET.
  • a semiconductor device having such a structure is described in Patent Document 1, for example.
  • the drain layer 201 containing an N-type impurity at a high concentration constitutes an N + type silicon substrate.
  • a drift layer 202 containing a low concentration N-type impurity is formed on the drain layer 201.
  • a P-type body region 203 containing P-type impurities is formed on the drift layer 202.
  • a P + type diffusion region 204 containing a P-type impurity at a higher concentration than the P-type body region 203 is formed.
  • An N + type source region 205 containing a high concentration of N type impurities is also formed on the surface of the P type body region 203 so as to sandwich the P + type diffusion region 204.
  • a plurality of trenches 206 having a rectangular cross section are formed.
  • a gate insulating film 207 and an interlayer insulating film 224 are formed on the inner surface (including the side wall surface 206a and the bottom surface 206b) of the trench 206.
  • a gate electrode 208 having a polysilicon force surrounded by a gate insulating film 207 and an interlayer insulating film 224 is formed.
  • a P + type diffusion region 209 containing a high concentration P type impurity is formed on the surface of the drift layer 202.
  • This P + type diffusion region 209 is formed from the surface of the drift layer 202 to the deep inside.
  • P-type body region 203 and P + -type diffusion region 209 are adjacent to each other through trench 206.
  • parasitic diodes are formed between the P-type body region 203 and the drift layer 202 and between the P + -type diffusion region 209 and the drift layer 202.
  • a source electrode film 210 having a metal force is formed on the top of the above structure.
  • the source electrode film 210 is electrically connected to the N + type source region 205 and the P + type diffusion region 209 and insulated from the gate electrode 208.
  • a drain electrode film 211 having a metal force is formed on the back surface of the drain layer 201.
  • the illustrated active region includes a drain layer 201, a drift layer 202, a P-type body region 203, an N + type source region 205, a gate electrode 208, a source electrode film 210, a drain electrode film 211, and an interlayer insulating film 224.
  • Multiple MOSFET structures are formed! / Figure 13 shows the structure around the outer edge of the active area.
  • the gate electrode 208 and the drain electrode film 211 are grounded and a positive voltage is applied to the source electrode film 210, the PN junction between the P-type body region 203 and the drift layer 202 and the P + type diffusion region 209 and the drift layer 202 The PN junction between the source electrode film 210 and the drain electrode film 211 becomes a forward bias, and a current flows from the source electrode film 210 toward the drain electrode film 211.
  • Patent Document 2 discloses a technique for improving the breakdown voltage of a trench gate IGBT by forming the outermost P-well deeper than the inner P-well.
  • Patent Document 3 discloses a technique for maintaining a high breakdown voltage of a device by connecting a P-type base layer to a P-type base layer in a trench gate type IGBT and enclosing the P-type base layer. It is disclosed.
  • Patent Document 4 discloses a technique for preventing element destruction due to carrier concentration by providing a fixed potential diffusion layer through which carriers flow in a planar MOSFET.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-154748
  • Patent Document 2 JP-A-6-45612
  • Patent Document 3 Japanese Patent Laid-Open No. 9-270512
  • Patent Document 4 Japanese Patent Laid-Open No. 2001-7322
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve breakdown voltage and reduce the occurrence of element breakdown. To do.
  • the present invention includes a first semiconductor layer having first and second main surfaces facing each other, made of a first conductivity type semiconductor, and in contact with the first main surface, and the first semiconductor
  • a second semiconductor layer made of a first-conductivity-type semiconductor having a lower impurity concentration than the layer, a plurality of grooves formed in the surface of the second semiconductor layer, a gate electrode formed in the groove,
  • On the surface of the second semiconductor layer a first region of the second conductivity type formed between the two grooves, and on the surface of the second semiconductor layer, the first region A first carrier extraction region of a second conductivity type formed so as to be in contact with the groove and in contact with the first region; and on the surface of the second semiconductor layer, the first carrier extraction region A second conductivity type second electrode formed in contact with the groove and in contact with the first carrier extraction region;
  • a semiconductor device comprising a second electrode in contact with and having a metal force.
  • the depth of the first carrier extraction region of the surface force of the second semiconductor layer may be greater than the depth of the second carrier extraction region from the surface of the second semiconductor layer. .
  • the depth of the second carrier extraction region of the surface force of the second semiconductor layer is determined by the second of the groove in contact with both the first carrier extraction region and the second carrier extraction region. It may be smaller than the depth of the surface force of the semiconductor layer.
  • the width of the groove contacting both the first carrier extraction region and the second carrier extraction region may be larger than the widths of the other grooves.
  • the depth of the surface force of the second semiconductor layer in the groove that contacts both the first carrier extraction region and the second carrier extraction region depends on the second semiconductor of the other groove. It may be larger than the depth of the surface force of the body layer.
  • the present invention provides the first main surface of the first semiconductor layer having the first and second main surfaces facing each other and formed of a first conductivity type semiconductor.
  • Forming a pattern of an oxide film made of a semiconductor oxide on a second semiconductor layer having a semiconductor power of the first conductivity type having a lower impurity concentration than that of the semiconductor layer, and a pattern of the oxide film As a mask, a second conductivity type impurity is implanted, and the impurity is diffused into the second semiconductor layer to form a second conductivity type first carrier extraction region and the second conductivity type.
  • Forming a second carrier extraction region of the second conductivity type separated from the carrier extraction region of 1, the second semiconductor layer, the first carrier extraction region, and the second carrier extraction region The pattern of the acid coating covering the surface of Forming a groove in contact with the first carrier extraction region and the second carrier extraction region by etching using the oxide film pattern as a mask, and a plurality of other grooves, Forming a gate electrode so as to fill the groove, forming a second conductivity type first region between the plurality of grooves, and forming a first electrode on the surface of the first carrier extraction region; Forming a second region of the second conductivity type having an impurity concentration higher than that of the first carrier extraction region, and having an impurity concentration higher than that of the second carrier extraction region on the surface of the second carrier extraction region Forming a third region of the second conductivity type, and forming a fourth region of the first conductivity type having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
  • the second The first electrode made of metal is formed in contact
  • FIG. 1 is a sectional view showing a sectional structure of a semiconductor device la according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view for explaining a manufacturing process for the semiconductor device la.
  • FIG. 3 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 4 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 5 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 6 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
  • FIG. 7 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 8 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
  • FIG. 9 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 10 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lb according to a second embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lc according to a modification of the second embodiment.
  • FIG. 13 is a cross-sectional view showing a cross-sectional structure of a conventional semiconductor device 2.
  • Drain electrode film 115, 116 , 120, 121, 122, 123... Acid film, 117, 118 ⁇ ⁇ ⁇ Implanted layer, 119 ⁇ ⁇ ⁇ Resist film, 124, 224 ⁇ ⁇ Interlayer insulating film, 301, 302 ⁇ ⁇ ⁇ Main surface.
  • FIG. 1 shows a cross-sectional structure of a semiconductor device la according to the first embodiment of the present invention.
  • the drain layer 101 containing a high-concentration N-type impurity has two main surfaces 301 and 302 facing each other, and constitutes an N + type silicon substrate.
  • a drift layer 102 containing a low concentration N-type impurity is formed on the main surface 301 of the drain layer 101.
  • a P-type body region 103 containing P-type impurities is formed in the surface region of the drift layer 102.
  • a P + type diffusion region 104 containing P-type impurities at a higher concentration than the P-type body region 103 is formed.
  • an N + type source region 105 containing a high concentration N-type impurity is also formed so as to sandwich the P + type diffusion region 104.
  • a plurality of trenches 106 having a rectangular cross-sectional shape are formed.
  • a gate insulating film 107 is formed on the inner surface (including the side wall surface 106a and the bottom surface 106b) of the trench 106.
  • a gate electrode 108 having a polysilicon force surrounded by a gate insulating film 107 is formed inside the trench 106.
  • Two carrier extraction regions 109 and 110 containing a P-type impurity are formed in the surface region of the drift layer 102.
  • the carrier extraction region 109 is in contact with the trench 106 in contact with the P-type body region 103 and is also in contact with the P-type body region 103.
  • the carrier extraction region 109 is in contact with the outermost trench 106.
  • the carrier extraction region 110 is in contact with the trench 106 in contact with the carrier extraction region 109 and is separated from the carrier extraction region 109.
  • the depth of the carrier extraction region 109 having the surface force of the drift layer 102 (distance X in the figure) is larger than the depth of the carrier extraction region 110 having the surface force of the drift layer 102 (distance X in the drawing).
  • Minority carriers injected into the drift layer 102 during the operation of the semiconductor device la flow into the extraction regions 109 and 110. This alleviates minority carrier concentration and destroys the device. Can be prevented.
  • a P + type diffusion region 111 containing a high concentration of P type impurities is formed on the surfaces of the carrier extraction regions 109 and 110.
  • a source electrode film 112 that is in contact with the P + type diffusion region 104 and the N + type source region 105 and also has a metal force is formed on the surface of the drift layer 102.
  • the source electrode film 112 is also in contact with the carrier extraction regions 109 and 110 and the P + type diffusion region 111.
  • the source electrode film 112 is isolated from the gate electrode 108 by the interlayer insulating film 124.
  • the carrier extraction regions 109 and 110 are electrically connected to the source electrode film 112 through the P + type diffusion region 111.
  • a part of the surface of the carrier extraction region 110 is covered with an insulating film 113 made of SiO.
  • a drain electrode film 114 made of metal is formed on the main surface 302 of the drain layer 101.
  • the drain electrode film 114 forms an ohmic junction with the drain layer 101.
  • the drain layer 101, the drift layer 102, the P-type body region 103, the N + type source region 105, the gate electrode 108, the source electrode film 112, the drain electrode film 114, and the interlayer insulating film 124 constitute a MOSFET.
  • a plurality of MOSFET structures are formed in the active region.
  • Figure 1 shows the structure around the outer edge of the active area.
  • Carrier extraction regions 109 and 110 are formed outside the active region.
  • the trench 106 is formed so that all the trenches 106 have the same width (distance X in the figure).
  • the trenches 106 are formed so that all the trenches 106 have the same depth from the drift layer 102 (distance X in the figure). Around the outer edge of the active area shown in Figure 1
  • the mask shape In order to prevent this, it is desirable to design the mask shape so that the width of the outermost trench 106 is wider than the width of the other trenches 106.
  • the width of the outer trench 106 becomes wider than the width of the other trench 106, the depth of the outer trench 106 becomes smaller than that of the other trench 106 due to the microloading effect that the etching rate changes according to the pattern dimension. Greater than depth.
  • the drift layer 102 is formed by epitaxially growing silicon containing N-type impurities on the surface of the drain layer 101.
  • the P-type body region 103 is formed by injecting P-type impurities as well as the surface force of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range.
  • the P + type diffusion region 104 is formed by selectively injecting a surface force P-type impurity of the P-type body region 103 and diffusing the impurity at a high temperature within a range of a predetermined surface force depth.
  • the N + type source region 105 is formed by selectively injecting an N type impurity from the surface of the P type body region 103 and diffusing the impurity at a high temperature within a predetermined depth from the surface.
  • the carrier extraction regions 109 and 110 are formed by injecting P-type impurities from the surface of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range.
  • the P + type diffusion region 111 is formed by selectively injecting the surface force P-type impurities of the carrier extraction regions 109 and 110 and diffusing the impurities at a high temperature within a predetermined depth range. ing.
  • a mesa structure is formed including the surfaces of the P-type body region 103, the P + type diffusion region 104, and the N + type source region 105 that are in contact with the source electrode film 112. .
  • the trench 106 is formed by etching the drift layer 102.
  • the gate insulating film 107 is formed by oxidizing the surface of the trench 106 in a high-temperature oxygen atmosphere.
  • the gate electrode 108 is formed by depositing polysilicon containing an N-type impurity on the surface of the gate insulating film 107.
  • the source electrode film 112 and the drain electrode film 114 are formed, for example, by sputtering an electrode material.
  • the impurity concentration of the drain layer 101 is, for example, 10 19 — 10 2 G cm ⁇ 3 .
  • the impurity concentration on the surface of the P-type body region 10 3 is, for example, 10 17 ⁇ 10 18 cm ⁇ 3 .
  • the impurity concentration at the surface of the P + type diffusion region 104 and the P + type diffusion region 111 is, for example, 10 18 ⁇ 10 19 cm ⁇ 3 .
  • the impurity concentration on the surface of the N + type source region 105 is, for example, 10 19 ⁇ 10 2 G cm ⁇ 3 .
  • the impurity concentration at the surface of the carrier extraction regions 109 and 110 is, for example, 10 1 7 ⁇ 10 18 cm ⁇ 3 .
  • Source electrode film 112 is grounded and drained.
  • a positive voltage is applied to the gate electrode film 114 and a positive voltage is applied to the gate electrode 108, an inversion layer is formed at the interface between the P-type body region 103 and the trench 106, and the drain electrode film 114 moves toward the source electrode film 112.
  • Current flows by force.
  • the ground force is also applied to the gate electrode 108 as its state force, the inversion layer formed at the interface between the P-type body region 103 and the trench 106 is extinguished, and the current is cut off.
  • the parasitic diode formed by the drift layer 102, the P-type body region 103, and the P + type diffusion region 104 is in order. Biased and current flows through the parasitic diode. Minority carriers are injected into the drift layer 102 by the current. In this state, when the voltage between the source electrode film 112 and the drain electrode film 114 is inverted, the minority carriers injected into the drift layer 102 flow into the P-type body region 103 connected to the source electrode film 112.
  • the drift layer 102 is formed by epitaxial growth on the main surface 301 of the drain layer 101, and an oxide such as SiO is deposited on the drift layer 102 to form an oxide film 115 (FIG. 2).
  • a resist is applied on the oxide film 115, and a resist pattern is formed by a photographic process.
  • the oxide film 115 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed (FIG. 3).
  • P-type impurities such as B (boron) are added to the surface of the drift layer 102 so as to pass through the oxide film 116.
  • Implantation forms implant layers 117 and 118 (FIG. 4).
  • a resist is applied on the oxide film 115, and a pattern of the resist film 119 is formed by a photographic process.
  • a P-type impurity is again implanted into the implantation layer 117 (FIG. 5).
  • the process shown in FIGS. 3 to 5 may be constituted by a process of forming only the injection layer 117 and a process of forming only the injection layer 118.
  • the resist film 119 is removed and annealing is performed in a high-temperature oxygen atmosphere, the P-type impurities in the implantation layers 117 and 118 diffuse into the drift layer 102, and the carrier extraction regions 109 and 110 become Formed ( Figure 6).
  • the surface of the drift layer 102 is oxidized to form an oxide film 120 (FIG. 7).
  • a resist is applied on the oxide film 120, and a resist pattern is formed by a photographic process.
  • the oxide film 120 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed. At this time, an insulating film 113 is formed.
  • Thermal oxidation is performed in a high-temperature oxygen atmosphere to form a thin oxide film 121 on the surface of the drift layer 102 other than the portion covered with the oxide film 120.
  • An oxide film 122 (NS G: Non-doped Silicate Glass) is deposited on the oxide film 121 by CVD (Chemical Vapor Deposition) (FIG. 8).
  • a film composed of the oxide films 121 and 122 is referred to as an oxide film 123.
  • a resist is applied on the oxide film 123, and a resist pattern is formed by a photographic process.
  • alignment of the photomask is performed so that an opening of the resist is formed between the carrier extraction region 109 and the carrier extraction region 110.
  • the oxide film 123 is etched to expose the surface of the drift layer 102, and then the resist is removed.
  • the drift layer 102 is etched to form a trench 106 (FIG. 9).
  • the depth of the trench 106 A in which the width of the outermost trench 106 A is larger than the width of the other trench 106 is larger than the depth of the other trench 106.
  • the oxide film 123 is removed, and the gate insulating film 107 is formed by thermal oxidation in a high-temperature oxygen atmosphere.
  • Polysilicon is deposited so as to fill trench 106 and cover the surface of drift layer 102. This polysilicon is etched to a height near the surface of the drift layer 102 to form a gate electrode 108.
  • Thermal oxidation is performed in a high-temperature oxygen atmosphere, and the gate electrode The surface of 108 is covered with a gate insulating film 107.
  • a resist is applied on the surface of the drift layer 102, and a resist pattern is formed through a photographic process, in which the region where the P-type body region 103 is formed is exposed.
  • P-type impurities such as B are implanted into the surface of the drift layer 102. After removing the resist and annealing at a high temperature, the implanted P-type impurities diffuse into the drift layer 102. A P-type body region 103 is formed.
  • the P + type diffusion regions 104 and 111 are formed. It is formed.
  • an N type impurity such as As (arsenic) is selectively implanted into the surface of the P type body region 103 and annealing is performed at a high temperature, an N + type diffusion region 105 is formed.
  • the gate insulating film 107 above the upper surface of the gate electrode 108 is etched.
  • An interlayer insulating film 124 is formed by CVD, and a portion of the interlayer insulating film 124 that is exposed outside the trench 106 is etched.
  • An electrode material is deposited on the surface of the drift layer 102 to form the source electrode film 112, and an electrode material is deposited on the main surface 302 of the drain layer 101 to form the drain electrode film 114 (FIG. 10).
  • FIG. 11 shows a cross-sectional structure of the semiconductor device lb according to the present embodiment. Structures having the same functions as those shown in FIG. 1 are given the same reference numerals.
  • the depth of the surface force of the drift layer 102 in the carrier extraction region 110 is the outermost tray.
  • the depth from the surface of the drift layer 102 of the 106A is smaller (distance X in the figure)! /.
  • FIG. 12 shows a cross-sectional structure of a semiconductor device lc according to a modification of the present embodiment. Structures having the same functions as those shown in Fig. 1 are given the same reference numerals.
  • the width of the outermost trench 106A (distance X in the figure) is larger than the width of other trenches 106 (distance X in the figure). This is the outermost
  • the shape of the mask is designed so that the width of one trench 106 is wider than the width of the other trench 106.
  • the depth (distance X in the figure) of the outermost trench 106A from the surface of the drift layer 102 is different from the surface of the drift layer 102 of the other trench 106. Greater than the depth (distance X in the figure).
  • the breakdown voltage can be improved and the occurrence of device breakdown can be reduced.

Abstract

On the surface region of a drift layer (102), two carrier extracting regions (109, 110) containing a P-type impurity are formed. The carrier extracting region (109) is brought into contact with a trench (106) having contact with a P-type body region (103), and is also brought into contact with the P-type body region (103). The carrier extracting region (109) is also brought into contact with the outermost trench (106). The carrier extracting region (110) is brought into contact with the trench (106) having contact with the carrier extracting region (109), and is separated from the carrier extracting region (109). A small number of carriers, which have been injected into the drift layer (102) while a semiconductor device (1a) is operated, flow into the carrier extracting regions (109, 110).

Description

明 細 書  Specification
半導体装置およびその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、トレンチゲート型の MOS (Metal-Oxide-Semiconductor)構造を有する 半導体装置およびその製造方法に関する。  The present invention relates to a semiconductor device having a trench gate type MOS (Metal-Oxide-Semiconductor) structure and a method for manufacturing the same.
背景技術  Background art
[0002] パワー MOSFET(MOS Field Effect Transistor)の構成を有する半導体装置にお いて、トレンチゲート構造が形成されたものは、近年、 DC— DCコンバータ等、各種電 源に幅広く応用されている。トレンチゲート型 MOSFETを備えた半導体装置におい ては、ゲート電極に関わる構造を改良することによって、耐圧の向上が図られている 。一般に、 MOSFETにおいては、ドレイン層とベース拡散層との間の PN接合によつ て寄生ダイオードが形成されて 、る。  In a semiconductor device having a power MOSFET (MOS field effect transistor) configuration, a trench gate structure formed has been widely applied to various power sources such as a DC-DC converter in recent years. In a semiconductor device including a trench gate type MOSFET, the breakdown voltage is improved by improving the structure related to the gate electrode. In general, in a MOSFET, a parasitic diode is formed by a PN junction between a drain layer and a base diffusion layer.
[0003] 図 13は、パワー MOSFETを備えた従来の半導体装置 2の断面構造を示している 。このような構造の半導体装置は、例えば特許文献 1に記載されている。高濃度の N 型不純物を含むドレイン層 201は N+型シリコン基板を構成している。ドレイン層 201 上には、低濃度の N型不純物を含むドリフト層 202が形成されている。ドリフト層 202 上には、 P型不純物を含む P型ボディ領域 203が形成されている。 P型ボディ領域 20 3の表面近傍には、 P型ボディ領域 203よりも高濃度の P型不純物を含む P+型拡散 領域 204が形成されている。 P型ボディ領域 203の表面には、 P+型拡散領域 204を 挟むように、高濃度の N型不純物を含む N+型ソース領域 205も形成されて ヽる。  FIG. 13 shows a cross-sectional structure of a conventional semiconductor device 2 having a power MOSFET. A semiconductor device having such a structure is described in Patent Document 1, for example. The drain layer 201 containing an N-type impurity at a high concentration constitutes an N + type silicon substrate. On the drain layer 201, a drift layer 202 containing a low concentration N-type impurity is formed. A P-type body region 203 containing P-type impurities is formed on the drift layer 202. Near the surface of the P-type body region 203, a P + type diffusion region 204 containing a P-type impurity at a higher concentration than the P-type body region 203 is formed. An N + type source region 205 containing a high concentration of N type impurities is also formed on the surface of the P type body region 203 so as to sandwich the P + type diffusion region 204.
[0004] P型ボディ領域 203の表面からドリフト層 202に至るまでの領域には、断面の形状 が矩形である複数のトレンチ 206が形成されている。このトレンチ 206の内面（側壁面 206aおよび底面 206bを含む）には、ゲート絶縁膜 207および層間絶縁膜 224が形 成されている。トレンチ 206の内部には、ゲート絶縁膜 207および層間絶縁膜 224に よって囲まれた、ポリシリコン力もなるゲート電極 208が形成されている。ドリフト層 20 2の表面には、高濃度の P型不純物を含む P+型拡散領域 209が形成されている。こ の P+型拡散領域 209は、ドリフト層 202の表面から内部の深くまで形成されている。 P型ボディ領域 203と P+型拡散領域 209は、トレンチ 206を介して隣り合つている。こ の半導体装置 2においては、 P型ボディ領域 203とドリフト層 202との間および P+型 拡散領域 209とドリフト層 202との間に寄生ダイオードが形成されている。 [0004] In a region from the surface of the P-type body region 203 to the drift layer 202, a plurality of trenches 206 having a rectangular cross section are formed. A gate insulating film 207 and an interlayer insulating film 224 are formed on the inner surface (including the side wall surface 206a and the bottom surface 206b) of the trench 206. Inside the trench 206, a gate electrode 208 having a polysilicon force surrounded by a gate insulating film 207 and an interlayer insulating film 224 is formed. On the surface of the drift layer 202, a P + type diffusion region 209 containing a high concentration P type impurity is formed. This P + type diffusion region 209 is formed from the surface of the drift layer 202 to the deep inside. P-type body region 203 and P + -type diffusion region 209 are adjacent to each other through trench 206. In this semiconductor device 2, parasitic diodes are formed between the P-type body region 203 and the drift layer 202 and between the P + -type diffusion region 209 and the drift layer 202.
[0005] 上記の構造の最上部には、金属力もなるソース電極膜 210が形成されている。ソー ス電極膜 210は N+型ソース領域 205および P+型拡散領域 209と電気的に接続され 、ゲート電極 208とは絶縁されている。ドレイン層 201の裏面には、金属力もなるドレ イン電極膜 211が形成されている。図示される能動領域には、ドレイン層 201、ドリフ ト層 202、 P型ボディ領域 203、 N+型ソース領域 205、ゲート電極 208、ソース電極 膜 210、ドレイン電極膜 211、および層間絶縁膜 224によって構成される MOSFET の構造が複数形成されて!/、る。図 13は能動領域の外縁周辺の構造を示して ヽる。  A source electrode film 210 having a metal force is formed on the top of the above structure. The source electrode film 210 is electrically connected to the N + type source region 205 and the P + type diffusion region 209 and insulated from the gate electrode 208. On the back surface of the drain layer 201, a drain electrode film 211 having a metal force is formed. The illustrated active region includes a drain layer 201, a drift layer 202, a P-type body region 203, an N + type source region 205, a gate electrode 208, a source electrode film 210, a drain electrode film 211, and an interlayer insulating film 224. Multiple MOSFET structures are formed! / Figure 13 shows the structure around the outer edge of the active area.
[0006] ソース電極膜 210を接地し、ドレイン電極膜 211に正電圧を印加し、ゲート電極 20 8に正電圧を印加すると、 P型ボディ領域 203とトレンチ 206との界面に反転層が形 成され、ドレイン電極膜 211からソース電極膜 210へ向力つて電流が流れるようにな る。一方、ゲート電極 208およびドレイン電極膜 211を接地し、ソース電極膜 210に 正電圧を印加すると、 P型ボディ領域 203とドリフト層 202との間の PN接合および P+ 型拡散領域 209とドリフト層 202との間の PN接合が共に順バイアスとなり、ソース電 極膜 210からドレイン電極膜 211へ向かって電流が流れるようになる。  [0006] When the source electrode film 210 is grounded, a positive voltage is applied to the drain electrode film 211, and a positive voltage is applied to the gate electrode 208, an inversion layer is formed at the interface between the P-type body region 203 and the trench 206. As a result, a current flows from the drain electrode film 211 toward the source electrode film 210. On the other hand, when the gate electrode 208 and the drain electrode film 211 are grounded and a positive voltage is applied to the source electrode film 210, the PN junction between the P-type body region 203 and the drift layer 202 and the P + type diffusion region 209 and the drift layer 202 The PN junction between the source electrode film 210 and the drain electrode film 211 becomes a forward bias, and a current flows from the source electrode film 210 toward the drain electrode film 211.
[0007] このように、トレンチゲート型 MOSFETにおいては、寄生ダイオードを回路の一部 として利用することがある力 能動領域の外縁に位置する寄生ダイオードにキャリア が集中し、素子破壊を起こしやすいという問題があった。なお、特許文献 2には、トレ ンチゲート型 IGBTにおいて、最外の Pゥエルをそれよりも内側の Pゥエルよりも深く形 成することにより、素子耐圧の向上を図る技術が開示されている。特許文献 3には、ト レンチゲート型 IGBTにおいて、 P型ベース層に連結すると共に、 P型ベース層を包 囲するように形成された P型半導体層によって、装置の耐圧を高く維持する技術が開 示されている。特許文献 4には、プレーナ型 MOSFETにおいて、キャリアが流れ込 む固定電位拡散層を設けることにより、キャリアの集中による素子破壊を防止する技 術が開示されている。  As described above, in the trench gate type MOSFET, there is a problem that the parasitic diode may be used as a part of the circuit. The problem is that the carrier is concentrated on the parasitic diode located at the outer edge of the active region, and the element is easily destroyed. was there. Patent Document 2 discloses a technique for improving the breakdown voltage of a trench gate IGBT by forming the outermost P-well deeper than the inner P-well. Patent Document 3 discloses a technique for maintaining a high breakdown voltage of a device by connecting a P-type base layer to a P-type base layer in a trench gate type IGBT and enclosing the P-type base layer. It is disclosed. Patent Document 4 discloses a technique for preventing element destruction due to carrier concentration by providing a fixed potential diffusion layer through which carriers flow in a planar MOSFET.
特許文献 1：特開平 11-154748号公報 特許文献 2：特開平 6 - 45612号公報 Patent Document 1: Japanese Patent Laid-Open No. 11-154748 Patent Document 2: JP-A-6-45612
特許文献 3：特開平 9— 270512号公報  Patent Document 3: Japanese Patent Laid-Open No. 9-270512
特許文献 4:特開 2001-7322号公報  Patent Document 4: Japanese Patent Laid-Open No. 2001-7322
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0008] 本発明は、上述した問題点に鑑みてなされたものであって、耐圧を向上し、素子破 壊の発生を低減することができる半導体装置およびその製造方法を提供することを 目的とする。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve breakdown voltage and reduce the occurrence of element breakdown. To do.
課題を解決するための手段  Means for solving the problem
[0009] 本発明は、対向する第 1および第 2の主面を有し、第 1導電型の半導体からなる第 1 の半導体層と、前記第 1の主面に接し、前記第 1の半導体層よりも不純物濃度の低い 第 1導電型の半導体からなる第 2の半導体層と、前記第 2の半導体層の表面に形成 された複数の溝と、前記溝に形成されたゲート電極と、前記第 2の半導体層の表面に おいて、 2つの前記溝の間に形成された第 2導電型の第 1の領域と、前記第 2の半導 体層の表面において、前記第 1の領域と接する前記溝に接すると共に、前記第 1の 領域と接するように形成された第 2導電型の第 1のキャリア引き抜き領域と、前記第 2 の半導体層の表面において、前記第 1のキャリア引き抜き領域と接する前記溝に接し 、前記第 1のキャリア引き抜き領域と離れて形成された第 2導電型の第 2のキャリア引 き抜き領域と、前記第 1のキャリア引き抜き領域の表面において、前記第 1のキャリア 引き抜き領域よりも不純物濃度の高い第 2導電型の第 2の領域と、前記第 2のキャリア 引き抜き領域の表面において、前記第 2のキャリア引き抜き領域よりも不純物濃度の 高い第 2導電型の第 3の領域と、前記第 1の領域の表面において、前記第 2の半導 体層よりも不純物濃度の高い第 1導電型の第 4の領域と、前記第 2の領域、前記第 3 の領域、および前記 4の領域の表面に接し、金属力 なる第 1の電極と、前記第 2の 主面に接し、金属力 なる第 2の電極とを備えたことを特徴とする半導体装置である。  [0009] The present invention includes a first semiconductor layer having first and second main surfaces facing each other, made of a first conductivity type semiconductor, and in contact with the first main surface, and the first semiconductor A second semiconductor layer made of a first-conductivity-type semiconductor having a lower impurity concentration than the layer, a plurality of grooves formed in the surface of the second semiconductor layer, a gate electrode formed in the groove, On the surface of the second semiconductor layer, a first region of the second conductivity type formed between the two grooves, and on the surface of the second semiconductor layer, the first region A first carrier extraction region of a second conductivity type formed so as to be in contact with the groove and in contact with the first region; and on the surface of the second semiconductor layer, the first carrier extraction region A second conductivity type second electrode formed in contact with the groove and in contact with the first carrier extraction region; A carrier extraction region, a second conductivity type second region having an impurity concentration higher than that of the first carrier extraction region on the surface of the first carrier extraction region, and the second carrier extraction region. A second conductivity type third region having a higher impurity concentration than the second carrier extraction region, and a surface of the first region having an impurity concentration higher than that of the second semiconductor layer. A first region of high first conductivity type, the second region, the third region, and the surface of the fourth region, the first electrode made of metal force, and the second main surface; A semiconductor device comprising a second electrode in contact with and having a metal force.
[0010] 前記第 2の半導体層の表面力 の前記第 1のキャリア引き抜き領域の深さは、前記 第 2の半導体層の表面からの前記第 2のキャリア引き抜き領域の深さよりも大きくても よい。 [0011] 前記第 2の半導体層の表面力 の前記第 2のキャリア引き抜き領域の深さは、前記 第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する前記 溝の前記第 2の半導体層の表面力もの深さよりも小さくてもよい。 [0010] The depth of the first carrier extraction region of the surface force of the second semiconductor layer may be greater than the depth of the second carrier extraction region from the surface of the second semiconductor layer. . [0011] The depth of the second carrier extraction region of the surface force of the second semiconductor layer is determined by the second of the groove in contact with both the first carrier extraction region and the second carrier extraction region. It may be smaller than the depth of the surface force of the semiconductor layer.
[0012] 前記第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する 前記溝の幅は、他の前記溝の幅よりも大きくてもよい。  [0012] The width of the groove contacting both the first carrier extraction region and the second carrier extraction region may be larger than the widths of the other grooves.
[0013] 前記第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する 前記溝の前記第 2の半導体層の表面力 の深さは、他の前記溝の前記第 2の半導 体層の表面力もの深さよりも大きくてもよい。  [0013] The depth of the surface force of the second semiconductor layer in the groove that contacts both the first carrier extraction region and the second carrier extraction region depends on the second semiconductor of the other groove. It may be larger than the depth of the surface force of the body layer.
[0014] 本発明は、対向する第 1および第 2の主面を有し、第 1導電型の半導体からなる第 1 の半導体層の前記第 1の主面上に形成された、前記第 1の半導体層よりも不純物濃 度の低い第 1導電型の半導体力 なる第 2の半導体層上に、半導体の酸化物からな る酸化膜のパターンを形成する工程と、前記酸ィ匕膜のパターンをマスクとして、第 2 導電型の不純物を注入すると共に、前記不純物を前記第 2の半導体層内に拡散す ることにより、第 2導電型の第 1のキャリア引き抜き領域を形成すると共に、前記第 1の キャリア引き抜き領域とは分離した第 2導電型の第 2のキャリア引き抜き領域を形成す る工程と、前記第 2の半導体層、前記第 1のキャリア引き抜き領域、および前記第 2の キャリア引き抜き領域の表面を被覆する前記酸ィ匕膜のパターンを形成し、前記酸ィ匕 膜のパターンをマスクとしてエッチングを行うことにより、前記第 1のキャリア引き抜き 領域および前記第 2のキャリア引き抜き領域に接する溝と、他の複数の溝を形成する 工程と、前記溝を埋めるようにゲート電極を形成し、前記複数の溝どうしの間に第 2導 電型の第 1の領域を形成する工程と、前記第 1のキャリア引き抜き領域の表面におい て、前記第 1のキャリア引き抜き領域よりも不純物濃度の高い第 2導電型の第 2の領 域を形成すると共に、前記第 2のキャリア引き抜き領域の表面において、前記第 2の キャリア引き抜き領域よりも不純物濃度の高い第 2導電型の第 3の領域を形成し、前 記第 1の領域の表面において、前記第 2の半導体層よりも不純物濃度の高い第 1導 電型の第 4の領域を形成する工程と、前記第 2の領域、前記第 3の領域、および前記 第 4の領域の表面に接し、金属からなる第 1の電極を形成し、前記第 2の主面上に、 金属からなる第 2の電極を形成する工程とを備えたことを特徴とする半導体装置の製 造方法である。 [0014] The present invention provides the first main surface of the first semiconductor layer having the first and second main surfaces facing each other and formed of a first conductivity type semiconductor. Forming a pattern of an oxide film made of a semiconductor oxide on a second semiconductor layer having a semiconductor power of the first conductivity type having a lower impurity concentration than that of the semiconductor layer, and a pattern of the oxide film As a mask, a second conductivity type impurity is implanted, and the impurity is diffused into the second semiconductor layer to form a second conductivity type first carrier extraction region and the second conductivity type. Forming a second carrier extraction region of the second conductivity type separated from the carrier extraction region of 1, the second semiconductor layer, the first carrier extraction region, and the second carrier extraction region The pattern of the acid coating covering the surface of Forming a groove in contact with the first carrier extraction region and the second carrier extraction region by etching using the oxide film pattern as a mask, and a plurality of other grooves, Forming a gate electrode so as to fill the groove, forming a second conductivity type first region between the plurality of grooves, and forming a first electrode on the surface of the first carrier extraction region; Forming a second region of the second conductivity type having an impurity concentration higher than that of the first carrier extraction region, and having an impurity concentration higher than that of the second carrier extraction region on the surface of the second carrier extraction region Forming a third region of the second conductivity type, and forming a fourth region of the first conductivity type having a higher impurity concentration than the second semiconductor layer on the surface of the first region; The second The first electrode made of metal is formed in contact with the surfaces of the first region, the third region, and the fourth region, and the second electrode made of metal is formed on the second main surface. A semiconductor device characterized by comprising a process. It is a manufacturing method.
発明の効果  The invention's effect
[0015] 本発明によれば、耐圧を向上し、素子破壊の発生を低減することができるという効 果が得られる。  [0015] According to the present invention, it is possible to improve the breakdown voltage and reduce the occurrence of element breakdown.
図面の簡単な説明  Brief Description of Drawings
[0016] [図 1]図 1は、本発明の第 1の実施形態による半導体装置 laの断面構造を示す断面 図である。  FIG. 1 is a sectional view showing a sectional structure of a semiconductor device la according to a first embodiment of the present invention.
[図 2]図 2は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 2 is a cross-sectional view for explaining a manufacturing process for the semiconductor device la.
[図 3]図 3は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 3 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 4]図 4は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 4 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 5]図 5は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 5 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 6]図 6は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 6 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
[図 7]図 7は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 7 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 8]図 8は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 8 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
[図 9]図 9は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 9 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 10]図 10は、半導体装置 laの製造工程を説明するための断面図である。  FIG. 10 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
[図 11]図 11は、本発明の第 2の実施形態による半導体装置 lbの断面構造を示す断 面図である。  FIG. 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lb according to a second embodiment of the present invention.
[図 12]図 12は、第 2の実施形態の変形例による半導体装置 lcの断面構造を示す断 面図である。  FIG. 12 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lc according to a modification of the second embodiment.
[図 13]図 13は、従来の半導体装置 2の断面構造を示す断面図である。  FIG. 13 is a cross-sectional view showing a cross-sectional structure of a conventional semiconductor device 2.
符号の説明  Explanation of symbols
[0017] la, lb, lc, 2···半導体装置、 101, 201…ドレイン層、 102, 202···ドリフト層 、 103, 203···Ρ型ボディ領域、 104, 111, 204, 209···Ρ+型拡散領域、 105, 2 05···Ν+型ソース領域、 106, 106A, 206…卜レンチ、 106a, 206a…側壁面、 1 06b, 206b…底面、 107, 207…ゲー卜絶縁膜、 108, 208…ゲー卜電極、 109, 110···キャリア引き抜き領域、 112, 210···ソース電極膜、 113···絶縁膜、 114, 211…ドレイン電極膜、 115, 116, 120, 121, 122, 123…酸ィ匕膜、 117, 118· · ·注入層、 119 · · ·レジスト膜、 124, 224· · ·層間絶縁膜、 301, 302 · · ·主面。 発明を実施するための最良の形態 [0017] la, lb, lc, 2... Semiconductor device, 101, 201... Drain layer, 102, 202... Drift layer, 103, 203 .. saddle type body region, 104, 111, 204, 209 Ρ + diffusion region, 105, 2 05 · + source region, 106, 106A, 206… 206wrench, 106a, 206a… side wall surface, 10 06b, 206b… bottom surface, 107, 207… gate卜 Insulating film, 108, 208… Gate electrode, 109, 110 ··· carrier extraction region, 112, 210 ··· Source electrode film, 113 ··· Insulating film, 114, 211 ... Drain electrode film, 115, 116 , 120, 121, 122, 123… Acid film, 117, 118 · · · Implanted layer, 119 · · · Resist film, 124, 224 · · Interlayer insulating film, 301, 302 · · · Main surface. BEST MODE FOR CARRYING OUT THE INVENTION
[0018] 以下、図面を参照し、本発明を実施するための最良の形態について説明する。図 1 は、本発明の第 1の実施形態による半導体装置 laの断面構造を示している。高濃度 の N型不純物を含むドレイン層 101は、対向する 2つの主面 301および 302を有し、 N+型シリコン基板を構成している。ドレイン層 101の主面 301上には、低濃度の N型 不純物を含むドリフト層 102が形成されている。ドリフト層 102の表面領域には、 P型 不純物を含む P型ボディ領域 103が形成されて 、る。 P型ボディ領域 103の表面近 傍には、 P型ボディ領域 103よりも高濃度の P型不純物を含む P+型拡散領域 104が 形成されている。 P型ボディ領域 103の表面には、 P+型拡散領域 104を挟むように、 高濃度の N型不純物を含む N+型ソース領域 105も形成されている。  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional structure of a semiconductor device la according to the first embodiment of the present invention. The drain layer 101 containing a high-concentration N-type impurity has two main surfaces 301 and 302 facing each other, and constitutes an N + type silicon substrate. On the main surface 301 of the drain layer 101, a drift layer 102 containing a low concentration N-type impurity is formed. A P-type body region 103 containing P-type impurities is formed in the surface region of the drift layer 102. Near the surface of the P-type body region 103, a P + type diffusion region 104 containing P-type impurities at a higher concentration than the P-type body region 103 is formed. On the surface of the P-type body region 103, an N + type source region 105 containing a high concentration N-type impurity is also formed so as to sandwich the P + type diffusion region 104.
[0019] P型ボディ領域 103の表面からドリフト層 102に至るまでの領域には、断面の形状 が矩形である複数のトレンチ 106が形成されている。このトレンチ 106の内面（側壁面 106aおよび底面 106bを含む）には、ゲート絶縁膜 107が形成されている。トレンチ 1 06の内部には、ゲート絶縁膜 107によって囲まれた、ポリシリコン力もなるゲート電極 108が形成されている。  In a region from the surface of P-type body region 103 to drift layer 102, a plurality of trenches 106 having a rectangular cross-sectional shape are formed. A gate insulating film 107 is formed on the inner surface (including the side wall surface 106a and the bottom surface 106b) of the trench 106. Inside the trench 106, a gate electrode 108 having a polysilicon force surrounded by a gate insulating film 107 is formed.
[0020] ドリフト層 102の表面領域には、 P型不純物を含む 2つのキャリア引き抜き領域 109 および 110が形成されている。キャリア引き抜き領域 109は、 P型ボディ領域 103と接 しているトレンチ 106と接していると共に、 P型ボディ領域 103とも接している。また、キ ャリア引き抜き領域 109は最も外側のトレンチ 106に接して ヽる。キャリア引き抜き領 域 110は、キャリア引き抜き領域 109と接するトレンチ 106に接しており、キャリア引き 抜き領域 109とは分離されて 、る。  [0020] Two carrier extraction regions 109 and 110 containing a P-type impurity are formed in the surface region of the drift layer 102. The carrier extraction region 109 is in contact with the trench 106 in contact with the P-type body region 103 and is also in contact with the P-type body region 103. The carrier extraction region 109 is in contact with the outermost trench 106. The carrier extraction region 110 is in contact with the trench 106 in contact with the carrier extraction region 109 and is separated from the carrier extraction region 109.
[0021] ドリフト層 102の表面力ものキャリア引き抜き領域 109の深さ（図中の距離 X )は、ド リフト層 102の表面力ものキャリア引き抜き領域 110の深さ（図中の距離 X )よりも大き  [0021] The depth of the carrier extraction region 109 having the surface force of the drift layer 102 (distance X in the figure) is larger than the depth of the carrier extraction region 110 having the surface force of the drift layer 102 (distance X in the drawing). big
2 い。キャリア引き抜き領域 109および 110のドリフト層 102の表面からの深さは共に、 トレンチ 106のドリフト層 102の表面からの深さ（図中の距離 X )よりも大きい。キャリア  2 The depths of carrier extraction regions 109 and 110 from the surface of drift layer 102 are both greater than the depth of trench 106 from the surface of drift layer 102 (distance X in the figure). Career
4  Four
引き抜き領域 109および 110には、半導体装置 laの動作時にドリフト層 102に注入 された少数キャリアが流れ込む。これにより、少数キャリアの集中を緩和し、素子破壊 を防ぐことができる。 Minority carriers injected into the drift layer 102 during the operation of the semiconductor device la flow into the extraction regions 109 and 110. This alleviates minority carrier concentration and destroys the device. Can be prevented.
[0022] キャリア引き抜き領域 109および 110の表面には、高濃度の P型不純物を含む P+ 型拡散領域 111が形成されている。ドリフト層 102の表面上には、 P+型拡散領域 10 4および N+型ソース領域 105に接し、金属力もなるソース電極膜 112が形成されて いる。ソース電極膜 112はキャリア引き抜き領域 109および 110、 P+型拡散領域 111 にも接している。ソース電極膜 112は、層間絶縁膜 124によってゲート電極 108と絶 縁されている。キャリア引き抜き領域 109および 110は、 P+型拡散領域 111を介して ソース電極膜 112と電気的に接続されている。キャリア引き抜き領域 110の表面の一 部は、 SiO力 なる絶縁膜 113によって被覆されている。  [0022] On the surfaces of the carrier extraction regions 109 and 110, a P + type diffusion region 111 containing a high concentration of P type impurities is formed. On the surface of the drift layer 102, a source electrode film 112 that is in contact with the P + type diffusion region 104 and the N + type source region 105 and also has a metal force is formed. The source electrode film 112 is also in contact with the carrier extraction regions 109 and 110 and the P + type diffusion region 111. The source electrode film 112 is isolated from the gate electrode 108 by the interlayer insulating film 124. The carrier extraction regions 109 and 110 are electrically connected to the source electrode film 112 through the P + type diffusion region 111. A part of the surface of the carrier extraction region 110 is covered with an insulating film 113 made of SiO.
2  2
[0023] ドレイン層 101の主面 302上には、金属からなるドレイン電極膜 114が形成されて いる。ドレイン電極膜 114はドレイン層 101とォーミック接合を形成している。ドレイン 層 101、ドリフト層 102、 P型ボディ領域 103、 N+型ソース領域 105、ゲート電極 108 、ソース電極膜 112、ドレイン電極膜 114、および層間絶縁膜 124によって MOSFE Tが構成されている。能動領域には、 MOSFET構造が複数形成されている。図 1は 能動領域の外縁周辺の構造を示している。キャリア引き抜き領域 109および 110は 能動領域の外側に形成されて 、る。  A drain electrode film 114 made of metal is formed on the main surface 302 of the drain layer 101. The drain electrode film 114 forms an ohmic junction with the drain layer 101. The drain layer 101, the drift layer 102, the P-type body region 103, the N + type source region 105, the gate electrode 108, the source electrode film 112, the drain electrode film 114, and the interlayer insulating film 124 constitute a MOSFET. A plurality of MOSFET structures are formed in the active region. Figure 1 shows the structure around the outer edge of the active area. Carrier extraction regions 109 and 110 are formed outside the active region.
[0024] トレンチ 106は、全てのトレンチ 106の幅（図中の距離 X )が同一となるように形成さ  [0024] The trench 106 is formed so that all the trenches 106 have the same width (distance X in the figure).
3  Three
れている。また、トレンチ 106は、全てのトレンチ 106のドリフト層 102からの深さ（図中 の距離 X )が同一となるように形成されている。図 1に示される能動領域の外縁周辺  It is. The trenches 106 are formed so that all the trenches 106 have the same depth from the drift layer 102 (distance X in the figure). Around the outer edge of the active area shown in Figure 1
4  Four
においては、トレンチ 106を形成するためのドリフト層 102のエッチング用のマスクを 形成するときに、以下のような問題が発生することがある。レジストが塗布された後の 写真工程 (露光および現像)のときに、最も外側のトレンチ 106 (キャリア引き抜き領域 109とキャリア引き抜き領域 110とに挟まれたトレンチ 106)において、露光が十分で なぐトレンチ 106が安定的に形成されない。  However, when forming a mask for etching the drift layer 102 for forming the trench 106, the following problems may occur. Trench 106 with sufficient exposure in the outermost trench 106 (trench 106 sandwiched between carrier extraction region 109 and carrier extraction region 110) during the photographic process (exposure and development) after the resist is applied. Is not formed stably.
[0025] これを防ぐため、最も外側のトレンチ 106の幅が他のトレンチ 106の幅よりも広くなる ように、マスクの形状を設計することが望ましい。外側のトレンチ 106の幅が他のトレン チ 106の幅よりも広くなると、パターン寸法に応じてエッチング速度が変化するという マイクロローデイング効果によって、外側のトレンチ 106の深さが他のトレンチ 106の 深さよりも大きくなる。 In order to prevent this, it is desirable to design the mask shape so that the width of the outermost trench 106 is wider than the width of the other trenches 106. When the width of the outer trench 106 becomes wider than the width of the other trench 106, the depth of the outer trench 106 becomes smaller than that of the other trench 106 due to the microloading effect that the etching rate changes according to the pattern dimension. Greater than depth.
[0026] 上述した構造にぉ ヽてドリフト層 102は、 N型不純物を含むシリコンをドレイン層 10 1の表面上にェピタキシャル成長させることにより形成されている。 P型ボディ領域 10 3は、ドリフト層 102の表面力も P型不純物を注入し、表面力も所定の深さの範囲内に その不純物を高温で拡散することにより形成されている。 P+型拡散領域 104は、 P型 ボディ領域 103の表面力 P型不純物を選択的に注入し、表面力 所定の深さの範 囲内にその不純物を高温で拡散することにより形成されている。 N+型ソース領域 10 5は、 P型ボディ領域 103の表面から N型不純物を選択的に注入し、表面から所定の 深さの範囲内にその不純物を高温で拡散することにより形成されている。  [0026] Over the above-described structure, the drift layer 102 is formed by epitaxially growing silicon containing N-type impurities on the surface of the drain layer 101. The P-type body region 103 is formed by injecting P-type impurities as well as the surface force of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range. The P + type diffusion region 104 is formed by selectively injecting a surface force P-type impurity of the P-type body region 103 and diffusing the impurity at a high temperature within a range of a predetermined surface force depth. The N + type source region 105 is formed by selectively injecting an N type impurity from the surface of the P type body region 103 and diffusing the impurity at a high temperature within a predetermined depth from the surface.
[0027] キャリア引き抜き領域 109および 110は、ドリフト層 102の表面から P型不純物を注 入し、表面力 所定の深さの範囲内にその不純物を高温で拡散することにより形成さ れている。 P+型拡散領域 111も同様に、キャリア引き抜き領域 109および 110の表 面力 P型不純物を選択的に注入し、表面力 所定の深さの範囲内にその不純物を 高温で拡散することにより形成されている。図 1においては、ソース電極膜 112と接触 している P型ボディ領域 103、 P+型拡散領域 104、および N+型ソース領域 105の各 表面を含んで 、るメサ状の構造が形成されて 、る。  The carrier extraction regions 109 and 110 are formed by injecting P-type impurities from the surface of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range. Similarly, the P + type diffusion region 111 is formed by selectively injecting the surface force P-type impurities of the carrier extraction regions 109 and 110 and diffusing the impurities at a high temperature within a predetermined depth range. ing. In FIG. 1, a mesa structure is formed including the surfaces of the P-type body region 103, the P + type diffusion region 104, and the N + type source region 105 that are in contact with the source electrode film 112. .
[0028] トレンチ 106は、ドリフト層 102をエッチングすることによって形成されている。ゲート 絶縁膜 107は、高温の酸素雰囲気中でトレンチ 106の表面を酸ィ匕することによって 形成されている。ゲート電極 108は、 N型不純物を含むポリシリコンをゲート絶縁膜 1 07の表面に堆積することにより形成されている。ソース電極膜 112およびドレイン電 極膜 114は、例えば電極材料のスパッタリングによって形成されている。  The trench 106 is formed by etching the drift layer 102. The gate insulating film 107 is formed by oxidizing the surface of the trench 106 in a high-temperature oxygen atmosphere. The gate electrode 108 is formed by depositing polysilicon containing an N-type impurity on the surface of the gate insulating film 107. The source electrode film 112 and the drain electrode film 114 are formed, for example, by sputtering an electrode material.
[0029] ドレイン層 101の不純物濃度は例えば 1019— 102Gcm— 3である。 P型ボディ領域 10 3の表面における不純物濃度は例えば 1017— 1018cm— 3である。 P+型拡散領域 104 および P+型拡散領域 111の表面における不純物濃度は例えば 1018— 1019cm— 3で ある。 N+型ソース領域 105の表面における不純物濃度は例えば 1019— 102Gcm— 3で ある。キャリア引き抜き領域 109および 110の表面における不純物濃度は例えば 101 7— 1018cm— 3である。 [0029] The impurity concentration of the drain layer 101 is, for example, 10 19 — 10 2 G cm −3 . The impurity concentration on the surface of the P-type body region 10 3 is, for example, 10 17 −10 18 cm− 3 . The impurity concentration at the surface of the P + type diffusion region 104 and the P + type diffusion region 111 is, for example, 10 18 −10 19 cm− 3 . The impurity concentration on the surface of the N + type source region 105 is, for example, 10 19 − 10 2 G cm− 3 . The impurity concentration at the surface of the carrier extraction regions 109 and 110 is, for example, 10 1 7 − 10 18 cm− 3 .
[0030] 次に、半導体装置 laの動作について説明する。ソース電極膜 112を接地し、ドレイ ン電極膜 114に正電圧を印加し、ゲート電極 108に正電圧を印加すると、 P型ボディ 領域 103とトレンチ 106との界面に反転層が形成され、ドレイン電極膜 114からソース 電極膜 112へ向力つて電流が流れる。その状態力もゲート電極 108に接地電圧を印 加すると、 P型ボディ領域 103とトレンチ 106との界面に形成されていた反転層が消 滅し、電流は遮断される。 Next, the operation of the semiconductor device la will be described. Source electrode film 112 is grounded and drained. When a positive voltage is applied to the gate electrode film 114 and a positive voltage is applied to the gate electrode 108, an inversion layer is formed at the interface between the P-type body region 103 and the trench 106, and the drain electrode film 114 moves toward the source electrode film 112. Current flows by force. When the ground force is also applied to the gate electrode 108 as its state force, the inversion layer formed at the interface between the P-type body region 103 and the trench 106 is extinguished, and the current is cut off.
[0031] また、ソース電極膜 112にドレイン電極膜 114よりも高い電圧が印加された場合に は、ドリフト層 102、 P型ボディ領域 103、および P+型拡散領域 104によって形成され る寄生ダイオードが順バイアスされ、その寄生ダイオードを通って電流が流れる。そ の電流により、ドリフト層 102内に少数キャリアが注入される。その状態でソース電極 膜 112とドレイン電極膜 114との間の電圧が反転すると、ドリフト層 102〖こ注入された 少数キャリアは、ソース電極膜 112に接続された P型ボディ領域 103に流れ込む。  In addition, when a higher voltage than the drain electrode film 114 is applied to the source electrode film 112, the parasitic diode formed by the drift layer 102, the P-type body region 103, and the P + type diffusion region 104 is in order. Biased and current flows through the parasitic diode. Minority carriers are injected into the drift layer 102 by the current. In this state, when the voltage between the source electrode film 112 and the drain electrode film 114 is inverted, the minority carriers injected into the drift layer 102 flow into the P-type body region 103 connected to the source electrode film 112.
[0032] MOSFET構造が形成された能動領域の端部では、最外周に位置する P型ボディ 領域 103に少数キャリアが集中しやすいが、ソース電極膜 112に電気的に接続され たキャリア引き抜き領域 109および 110が形成されていることにより、少数キャリアがこ のキャリア引き抜き領域 109および 110に流れ込むため、少数キャリアの集中は起こ らない。したがって、耐圧を向上し、素子破壊を低減することができる。また、分離さ れた 2つのキャリア引き抜き領域 109および 110が形成されていることにより、少数キ ャリア力 つのキャリア引き抜き領域に集中することを防止し、より効率的に少数キヤリ ァをソース電極膜 112へ送ることができる。  [0032] At the edge of the active region where the MOSFET structure is formed, minority carriers tend to concentrate in the P-type body region 103 located on the outermost periphery, but the carrier extraction region 109 electrically connected to the source electrode film 112 As a result of the formation of and 110, minority carriers flow into the carrier extraction regions 109 and 110, so that minority carrier concentration does not occur. Therefore, the breakdown voltage can be improved and the element breakdown can be reduced. Further, since the two separated carrier extraction regions 109 and 110 are formed, it is possible to prevent the minority carrier from being concentrated in the carrier extraction region having a minority carrier force, and to more efficiently distribute the minority carrier to the source electrode film 112. Can be sent to.
[0033] 次に、半導体装置 laの製造方法について、図 2—図 10を用いて説明する。まず、 ドレイン層 101の主面 301上に、ェピタキシャル成長によってドリフト層 102を形成し 、ドリフト層 102上に SiO等の酸化物を堆積し、酸化膜 115を形成する（図 2)。続い  Next, a method for manufacturing the semiconductor device la will be described with reference to FIGS. First, the drift layer 102 is formed by epitaxial growth on the main surface 301 of the drain layer 101, and an oxide such as SiO is deposited on the drift layer 102 to form an oxide film 115 (FIG. 2). Continued
2  2
て、酸ィ匕膜 115上にレジストを塗布し、写真工程によってレジストのパターンを形成す る。このレジストのパターンをマスクとして酸化膜 115をエッチングして、ドリフト層 102 の表面を露出させた後、レジストを除去する（図 3)。  Then, a resist is applied on the oxide film 115, and a resist pattern is formed by a photographic process. The oxide film 115 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed (FIG. 3).
[0034] 続いて、高温の酸素雰囲気中で熱酸化を行い、ドリフト層 102の表面のうち、酸ィ匕 膜 115によって被覆された部分以外の部分の表面に薄い酸ィ匕膜 116を形成する。こ の酸ィ匕膜 116を通過するように、ドリフト層 102の表面に B (ボロン)等の P型不純物を 注入し、注入層 117および 118を形成する（図 4)。再度、酸ィ匕膜 115上にレジストを 塗布し、写真工程によってレジスト膜 119のパターンを形成する。このレジスト膜 119 のパターンおよび酸ィ匕膜 115をマスクとして、注入層 117に P型不純物を再度注入 する（図 5)。図 3—図 5で示される工程は、注入層 117のみを形成する工程と、注入 層 118のみを形成する工程とによって構成される場合もある。 Subsequently, thermal oxidation is performed in a high-temperature oxygen atmosphere to form a thin oxide film 116 on the surface of the drift layer 102 other than the portion covered with the oxide film 115. . P-type impurities such as B (boron) are added to the surface of the drift layer 102 so as to pass through the oxide film 116. Implantation forms implant layers 117 and 118 (FIG. 4). Again, a resist is applied on the oxide film 115, and a pattern of the resist film 119 is formed by a photographic process. Using the pattern of the resist film 119 and the oxide film 115 as a mask, a P-type impurity is again implanted into the implantation layer 117 (FIG. 5). The process shown in FIGS. 3 to 5 may be constituted by a process of forming only the injection layer 117 and a process of forming only the injection layer 118.
[0035] 続いて、レジスト膜 119を除去し、高温の酸素雰囲気中でァニールを行うと、注入 層 117および 118内の P型不純物がドリフト層 102内に拡散し、キャリア引き抜き領域 109および 110が形成される（図 6)。ドリフト層 102の表面を酸ィ匕し、酸ィ匕膜 120を形 成する（図 7)。この酸ィ匕膜 120上にレジストを塗布し、写真工程によってレジストのパ ターンを形成する。このレジストのパターンをマスクとして酸化膜 120をエッチングして 、ドリフト層 102の表面を露出させた後、レジストを除去する。このとき、絶縁膜 113が 形成される。高温の酸素雰囲気中で熱酸化を行い、ドリフト層 102の表面のうち、酸 化膜 120によって被覆された部分以外の部分の表面に薄い酸ィ匕膜 121を形成する 。 CVD (Chemical Vapor Deposition)によって、この酸化膜 121上に酸化膜 122 (NS G : Non-doped Silicate Glass)を堆積する（図 8)。酸化膜 121および 122からなる膜を 酸化膜 123とする。 Subsequently, when the resist film 119 is removed and annealing is performed in a high-temperature oxygen atmosphere, the P-type impurities in the implantation layers 117 and 118 diffuse into the drift layer 102, and the carrier extraction regions 109 and 110 become Formed (Figure 6). The surface of the drift layer 102 is oxidized to form an oxide film 120 (FIG. 7). A resist is applied on the oxide film 120, and a resist pattern is formed by a photographic process. The oxide film 120 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed. At this time, an insulating film 113 is formed. Thermal oxidation is performed in a high-temperature oxygen atmosphere to form a thin oxide film 121 on the surface of the drift layer 102 other than the portion covered with the oxide film 120. An oxide film 122 (NS G: Non-doped Silicate Glass) is deposited on the oxide film 121 by CVD (Chemical Vapor Deposition) (FIG. 8). A film composed of the oxide films 121 and 122 is referred to as an oxide film 123.
[0036] 続いて、酸ィ匕膜 123上にレジストを塗布し、写真工程によってレジストのパターンを 形成する。このとき、キャリア引き抜き領域 109とキャリア引き抜き領域 110との間にレ ジストの開口部が形成されるように、フォトマスクの位置合わせを行う。レジストのパタ ーンをマスクとして、酸ィ匕膜 123をエッチングし、ドリフト層 102の表面を露出させた後 、レジストを除去する。酸化膜 123のパターンをマスクとして、ドリフト層 102をエツチン グし、トレンチ 106を形成する（図 9)。図 9においては、最も外側のトレンチ 106Aの 幅が他のトレンチ 106の幅よりも大きぐトレンチ 106Aの深さが他のトレンチ 106の深 さよりも大きくなつている。  Subsequently, a resist is applied on the oxide film 123, and a resist pattern is formed by a photographic process. At this time, alignment of the photomask is performed so that an opening of the resist is formed between the carrier extraction region 109 and the carrier extraction region 110. Using the resist pattern as a mask, the oxide film 123 is etched to expose the surface of the drift layer 102, and then the resist is removed. Using the pattern of the oxide film 123 as a mask, the drift layer 102 is etched to form a trench 106 (FIG. 9). In FIG. 9, the depth of the trench 106 A in which the width of the outermost trench 106 A is larger than the width of the other trench 106 is larger than the depth of the other trench 106.
[0037] 続いて、酸ィ匕膜 123を除去し、高温の酸素雰囲気中での熱酸化によってゲート絶 縁膜 107を形成する。トレンチ 106を埋めて、ドリフト層 102の表面を覆うように、ポリ シリコンを堆積する。ドリフト層 102の表面近傍の高さまでこのポリシリコンをエツチン グし、ゲート電極 108を形成する。高温の酸素雰囲気中で熱酸化を行い、ゲート電極 108の表面をゲート絶縁膜 107によって被覆する。ドリフト層 102の表面上にレジスト を塗布し、写真工程を経て、 P型ボディ領域 103の形成される領域が露出したレジス トのパターンを形成する。このレジストをマスクとしてドリフト層 102の表面に B等の P型 不純物を注入し、レジストを除去した後、高温でァニールを行うと、注入された P型不 純物がドリフト層 102内に拡散し、 P型ボディ領域 103が形成される。 Subsequently, the oxide film 123 is removed, and the gate insulating film 107 is formed by thermal oxidation in a high-temperature oxygen atmosphere. Polysilicon is deposited so as to fill trench 106 and cover the surface of drift layer 102. This polysilicon is etched to a height near the surface of the drift layer 102 to form a gate electrode 108. Thermal oxidation is performed in a high-temperature oxygen atmosphere, and the gate electrode The surface of 108 is covered with a gate insulating film 107. A resist is applied on the surface of the drift layer 102, and a resist pattern is formed through a photographic process, in which the region where the P-type body region 103 is formed is exposed. Using this resist as a mask, P-type impurities such as B are implanted into the surface of the drift layer 102. After removing the resist and annealing at a high temperature, the implanted P-type impurities diffuse into the drift layer 102. A P-type body region 103 is formed.
[0038] 続いて、同様にして、 P型ボディ領域 103、キャリア引き抜き領域 109および 110の 表面に選択的に P型不純物を注入し、高温でァニールを行うと、 P+型拡散領域 104 および 111が形成される。また、 P型ボディ領域 103の表面に選択的に As (ヒ素）等 の N型不純物を注入し、高温でァニールを行うと、 N+型拡散領域 105が形成される 。ゲート電極 108の上面よりも上方のゲート絶縁膜 107をエッチングする。 CVDによ つて層間絶縁膜 124を形成し、層間絶縁膜 124において、トレンチ 106の外部に出 ている部分をエッチングする。電極材料をドリフト層 102の表面に堆積してソース電極 膜 112を形成し、電極材料をドレイン層 101の主面 302に堆積してドレイン電極膜 11 4を形成する（図 10)。 Subsequently, in the same manner, when P-type impurities are selectively implanted into the surfaces of the P-type body region 103 and the carrier extraction regions 109 and 110 and annealing is performed at a high temperature, the P + type diffusion regions 104 and 111 are formed. It is formed. Further, when an N type impurity such as As (arsenic) is selectively implanted into the surface of the P type body region 103 and annealing is performed at a high temperature, an N + type diffusion region 105 is formed. The gate insulating film 107 above the upper surface of the gate electrode 108 is etched. An interlayer insulating film 124 is formed by CVD, and a portion of the interlayer insulating film 124 that is exposed outside the trench 106 is etched. An electrode material is deposited on the surface of the drift layer 102 to form the source electrode film 112, and an electrode material is deposited on the main surface 302 of the drain layer 101 to form the drain electrode film 114 (FIG. 10).
[0039] 次に、本発明の第 2の実施形態について説明する。図 11は、本実施形態による半 導体装置 lbの断面構造を示している。図 1に示された構造と同一の機能を有する構 造には同一の符号が付与されている。この半導体装置 lbにおいては、キャリア引き 抜き領域 110のドリフト層 102の表面力もの深さ（図中の距離 X )は、最も外側のトレ  [0039] Next, a second embodiment of the present invention will be described. FIG. 11 shows a cross-sectional structure of the semiconductor device lb according to the present embodiment. Structures having the same functions as those shown in FIG. 1 are given the same reference numerals. In this semiconductor device lb, the depth of the surface force of the drift layer 102 in the carrier extraction region 110 (distance X in the figure) is the outermost tray.
5  Five
ンチ 106Aのドリフト層 102の表面からの深さ（図中の距離 X )よりも小さ！/、。  The depth from the surface of the drift layer 102 of the 106A is smaller (distance X in the figure)! /.
6  6
[0040] 図 12は、本実施形態の変形例による半導体装置 lcの断面構造を示している。図 1 に示された構造と同一の機能を有する構造には同一の符号が付与されて 、る。この 半導体装置 lcにおいては、最も外側のトレンチ 106Aの幅（図中の距離 X )は、他の トレンチ 106の幅（図中の距離 X )よりも大きい。このようになっているのは、最も外側  FIG. 12 shows a cross-sectional structure of a semiconductor device lc according to a modification of the present embodiment. Structures having the same functions as those shown in Fig. 1 are given the same reference numerals. In this semiconductor device lc, the width of the outermost trench 106A (distance X in the figure) is larger than the width of other trenches 106 (distance X in the figure). This is the outermost
8  8
のトレンチ 106の幅が他のトレンチ 106の幅よりも広くなるように、マスクの形状を設計 してある力もである。これにより、ドリフト層 102のエッチング用のマスクを形成するた めにレジストを塗布した後の写真工程のときに、露光が不十分となることを防ぐことが できる。マイクロローデイング効果によって、最も外側のトレンチ 106Aのドリフト層 102 の表面からの深さ（図中の距離 X )は、他のトレンチ 106のドリフト層 102の表面から の深さ（図中の距離 X )よりも大きい。 It is also the force that the shape of the mask is designed so that the width of one trench 106 is wider than the width of the other trench 106. Thus, it is possible to prevent insufficient exposure during the photographic process after applying a resist to form a mask for etching the drift layer 102. Due to the microloading effect, the depth (distance X in the figure) of the outermost trench 106A from the surface of the drift layer 102 is different from the surface of the drift layer 102 of the other trench 106. Greater than the depth (distance X in the figure).
10  Ten
[0041] 以上、図面を参照して本発明の実施形態について詳述してきたが、具体的な構成 はこれらの実施の形態に限られるものではなぐこの発明の要旨を逸脱しない範囲の 設計変更等も含まれる。  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and design changes and the like within the scope not departing from the gist of the present invention. Is also included.
産業上の利用可能性  Industrial applicability
[0042] 耐圧を向上し、素子破壊の発生を低減することができる。 [0042] The breakdown voltage can be improved and the occurrence of device breakdown can be reduced.

Claims

請求の範囲 The scope of the claims
[1] 対向する第 1および第 2の主面を有し、第 1導電型の半導体からなる第 1の半導体 層と、  [1] a first semiconductor layer having first and second main surfaces facing each other and made of a semiconductor of the first conductivity type;
前記第 1の主面に接し、前記第 1の半導体層よりも不純物濃度の低い第 1導電型の 半導体からなる第 2の半導体層と、  A second semiconductor layer made of a semiconductor of a first conductivity type in contact with the first main surface and having an impurity concentration lower than that of the first semiconductor layer;
前記第 2の半導体層の表面に形成された複数の溝と、  A plurality of grooves formed on the surface of the second semiconductor layer;
前記溝に形成されたゲート電極と、  A gate electrode formed in the trench;
前記第 2の半導体層の表面において、 2つの前記溝の間に形成された第 2導電型 の第 1の領域と、  A first conductivity type first region formed between the two grooves on the surface of the second semiconductor layer;
前記第 2の半導体層の表面において、前記第 1の領域と接する前記溝に接すると 共に、前記第 1の領域と接するように形成された第 2導電型の第 1のキャリア引き抜き 領域と、  A first carrier extraction region of a second conductivity type formed on the surface of the second semiconductor layer so as to be in contact with the groove in contact with the first region and in contact with the first region;
前記第 2の半導体層の表面において、前記第 1のキャリア引き抜き領域と接する前 記溝に接し、前記第 1のキャリア引き抜き領域と離れて形成された第 2導電型の第 2 のキャリア引き抜き領域と、  A second carrier extraction region of a second conductivity type formed on the surface of the second semiconductor layer, in contact with the groove contacting the first carrier extraction region and spaced apart from the first carrier extraction region; ,
前記第 1のキャリア引き抜き領域の表面において、前記第 1のキャリア引き抜き領域 よりも不純物濃度の高い第 2導電型の第 2の領域と、  A second conductivity type second region having an impurity concentration higher than that of the first carrier extraction region on the surface of the first carrier extraction region;
前記第 2のキャリア引き抜き領域の表面において、前記第 2のキャリア引き抜き領域 よりも不純物濃度の高い第 2導電型の第 3の領域と、  A second conductivity type third region having a higher impurity concentration than the second carrier extraction region on the surface of the second carrier extraction region;
前記第 1の領域の表面において、前記第 2の半導体層よりも不純物濃度の高い第 1 導電型の第 4の領域と、  A first conductivity type fourth region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
前記第 2の領域、前記第 3の領域、および前記 4の領域の表面に接し、金属からな る第 1の電極と、  A first electrode made of metal in contact with the surfaces of the second region, the third region, and the fourth region;
前記第 2の主面に接し、金属からなる第 2の電極と、  A second electrode made of metal in contact with the second main surface;
を備えたことを特徴とする半導体装置。  A semiconductor device comprising:
[2] 前記第 2の半導体層の表面力 の前記第 1のキャリア引き抜き領域の深さは、前記 第 2の半導体層の表面からの前記第 2のキャリア引き抜き領域の深さよりも大きいこと を特徴とする請求項 1に記載の半導体装置。 [2] The depth of the first carrier extraction region in the surface force of the second semiconductor layer is greater than the depth of the second carrier extraction region from the surface of the second semiconductor layer. The semiconductor device according to claim 1.
[3] 前記第 2の半導体層の表面力 の前記第 2のキャリア引き抜き領域の深さは、前記 第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する前記 溝の前記第 2の半導体層の表面力もの深さよりも小さいことを特徴とする請求項 1に 記載の半導体装置。 [3] The depth of the second carrier extraction region of the surface force of the second semiconductor layer is determined by the second of the groove contacting both the first carrier extraction region and the second carrier extraction region. 2. The semiconductor device according to claim 1, wherein the depth of the semiconductor layer is smaller than the depth of the surface force.
[4] 前記第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する 前記溝の幅は、他の前記溝の幅よりも大きいことを特徴とする請求項 1に記載の半導 体装置。  4. The semiconductor according to claim 1, wherein a width of the groove contacting both the first carrier extraction region and the second carrier extraction region is larger than a width of the other groove. Body equipment.
[5] 前記第 1のキャリア引き抜き領域と前記第 2のキャリア引き抜き領域の両方に接する 前記溝の前記第 2の半導体層の表面力 の深さは、他の前記溝の前記第 2の半導 体層の表面力もの深さよりも大きいことを特徴とする請求項 1に記載の半導体装置。  [5] The depth of the surface force of the second semiconductor layer in the groove that contacts both the first carrier extraction region and the second carrier extraction region depends on the second semiconductor of the other groove. 2. The semiconductor device according to claim 1, wherein the depth is greater than the depth of the surface force of the body layer.
[6] 対向する第 1および第 2の主面を有し、第 1導電型の半導体からなる第 1の半導体 層の前記第 1の主面上に形成された、前記第 1の半導体層よりも不純物濃度の低い 第 1導電型の半導体からなる第 2の半導体層上に、半導体の酸化物からなる酸化膜 のパターンを形成する工程と、  [6] From the first semiconductor layer formed on the first main surface of the first semiconductor layer having the first and second main surfaces facing each other and made of a first conductivity type semiconductor Forming a pattern of an oxide film made of a semiconductor oxide on a second semiconductor layer made of a first conductivity type semiconductor having a low impurity concentration;
前記酸ィ匕膜のパターンをマスクとして、第 2導電型の不純物を注入すると共に、前 記不純物を前記第 2の半導体層内に拡散することにより、第 2導電型の第 1のキヤリ ァ引き抜き領域を形成すると共に、前記第 1のキャリア引き抜き領域とは分離した第 2 導電型の第 2のキャリア引き抜き領域を形成する工程と、  Using the oxide film pattern as a mask, a second conductivity type impurity is implanted, and the impurity is diffused into the second semiconductor layer to thereby extract the second conductivity type first carrier. Forming a region and forming a second carrier extraction region of a second conductivity type separated from the first carrier extraction region;
前記第 2の半導体層、前記第 1のキャリア引き抜き領域、および前記第 2のキャリア 引き抜き領域の表面を被覆する前記酸化膜のパターンを形成し、前記酸ィ匕膜のバタ ーンをマスクとしてエッチングを行うことにより、前記第 1のキャリア引き抜き領域およ び前記第 2のキャリア引き抜き領域に接する溝と、他の複数の溝を形成する工程と、 前記溝を埋めるようにゲート電極を形成し、前記複数の溝どうしの間に第 2導電型 の第 1の領域を形成する工程と、  Forming a pattern of the oxide film covering a surface of the second semiconductor layer, the first carrier extraction region, and the second carrier extraction region, and etching using the pattern of the oxide film as a mask Forming a groove in contact with the first carrier extraction region and the second carrier extraction region, and a plurality of other grooves, and forming a gate electrode so as to fill the groove, Forming a second region of the second conductivity type between the plurality of grooves;
前記第 1のキャリア引き抜き領域の表面において、前記第 1のキャリア引き抜き領域 よりも不純物濃度の高い第 2導電型の第 2の領域を形成すると共に、前記第 2のキヤ リア引き抜き領域の表面において、前記第 2のキャリア引き抜き領域よりも不純物濃 度の高い第 2導電型の第 3の領域を形成し、前記第 1の領域の表面において、前記 第 2の半導体層よりも不純物濃度の高い第 1導電型の第 4の領域を形成する工程と、 前記第 2の領域、前記第 3の領域、および前記第 4の領域の表面に接し、金属から なる第 1の電極を形成し、前記第 2の主面上に、金属からなる第 2の電極を形成する 工程と、 On the surface of the first carrier extraction region, a second region of a second conductivity type having a higher impurity concentration than the first carrier extraction region is formed, and on the surface of the second carrier extraction region, Forming a third region of the second conductivity type having a higher impurity concentration than the second carrier extraction region, and on the surface of the first region, Forming a fourth region of the first conductivity type having a higher impurity concentration than the second semiconductor layer; and contacting a surface of the second region, the third region, and the fourth region, a metal Forming a first electrode made of metal and forming a second electrode made of metal on the second main surface;
を備えたことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
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