WO2006082618A1 - Dispositif semi-conducteur et procédé de fabrication de celui-ci - Google Patents

Dispositif semi-conducteur et procédé de fabrication de celui-ci Download PDF

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Publication number
WO2006082618A1
WO2006082618A1 PCT/JP2005/001331 JP2005001331W WO2006082618A1 WO 2006082618 A1 WO2006082618 A1 WO 2006082618A1 JP 2005001331 W JP2005001331 W JP 2005001331W WO 2006082618 A1 WO2006082618 A1 WO 2006082618A1
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WO
WIPO (PCT)
Prior art keywords
region
carrier extraction
extraction region
semiconductor layer
conductivity type
Prior art date
Application number
PCT/JP2005/001331
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English (en)
Japanese (ja)
Inventor
Toshiyuki Takemori
Yuji Watanabe
Fuminori Sasaoka
Kazushige Matsuyama
Kunihito Ohshima
Masato Itoi
Original Assignee
Shindengen Electric Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co., Ltd. filed Critical Shindengen Electric Manufacturing Co., Ltd.
Priority to JP2007501456A priority Critical patent/JP4794546B2/ja
Priority to PCT/JP2005/001331 priority patent/WO2006082618A1/fr
Publication of WO2006082618A1 publication Critical patent/WO2006082618A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • the present invention relates to a semiconductor device having a trench gate type MOS (Metal-Oxide-Semiconductor) structure and a method for manufacturing the same.
  • MOS Metal-Oxide-Semiconductor
  • a trench gate structure formed has been widely applied to various power sources such as a DC-DC converter in recent years.
  • the breakdown voltage is improved by improving the structure related to the gate electrode.
  • a parasitic diode is formed by a PN junction between a drain layer and a base diffusion layer.
  • FIG. 13 shows a cross-sectional structure of a conventional semiconductor device 2 having a power MOSFET.
  • a semiconductor device having such a structure is described in Patent Document 1, for example.
  • the drain layer 201 containing an N-type impurity at a high concentration constitutes an N + type silicon substrate.
  • a drift layer 202 containing a low concentration N-type impurity is formed on the drain layer 201.
  • a P-type body region 203 containing P-type impurities is formed on the drift layer 202.
  • a P + type diffusion region 204 containing a P-type impurity at a higher concentration than the P-type body region 203 is formed.
  • An N + type source region 205 containing a high concentration of N type impurities is also formed on the surface of the P type body region 203 so as to sandwich the P + type diffusion region 204.
  • a plurality of trenches 206 having a rectangular cross section are formed.
  • a gate insulating film 207 and an interlayer insulating film 224 are formed on the inner surface (including the side wall surface 206a and the bottom surface 206b) of the trench 206.
  • a gate electrode 208 having a polysilicon force surrounded by a gate insulating film 207 and an interlayer insulating film 224 is formed.
  • a P + type diffusion region 209 containing a high concentration P type impurity is formed on the surface of the drift layer 202.
  • This P + type diffusion region 209 is formed from the surface of the drift layer 202 to the deep inside.
  • P-type body region 203 and P + -type diffusion region 209 are adjacent to each other through trench 206.
  • parasitic diodes are formed between the P-type body region 203 and the drift layer 202 and between the P + -type diffusion region 209 and the drift layer 202.
  • a source electrode film 210 having a metal force is formed on the top of the above structure.
  • the source electrode film 210 is electrically connected to the N + type source region 205 and the P + type diffusion region 209 and insulated from the gate electrode 208.
  • a drain electrode film 211 having a metal force is formed on the back surface of the drain layer 201.
  • the illustrated active region includes a drain layer 201, a drift layer 202, a P-type body region 203, an N + type source region 205, a gate electrode 208, a source electrode film 210, a drain electrode film 211, and an interlayer insulating film 224.
  • Multiple MOSFET structures are formed! / Figure 13 shows the structure around the outer edge of the active area.
  • the gate electrode 208 and the drain electrode film 211 are grounded and a positive voltage is applied to the source electrode film 210, the PN junction between the P-type body region 203 and the drift layer 202 and the P + type diffusion region 209 and the drift layer 202 The PN junction between the source electrode film 210 and the drain electrode film 211 becomes a forward bias, and a current flows from the source electrode film 210 toward the drain electrode film 211.
  • Patent Document 2 discloses a technique for improving the breakdown voltage of a trench gate IGBT by forming the outermost P-well deeper than the inner P-well.
  • Patent Document 3 discloses a technique for maintaining a high breakdown voltage of a device by connecting a P-type base layer to a P-type base layer in a trench gate type IGBT and enclosing the P-type base layer. It is disclosed.
  • Patent Document 4 discloses a technique for preventing element destruction due to carrier concentration by providing a fixed potential diffusion layer through which carriers flow in a planar MOSFET.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-154748
  • Patent Document 2 JP-A-6-45612
  • Patent Document 3 Japanese Patent Laid-Open No. 9-270512
  • Patent Document 4 Japanese Patent Laid-Open No. 2001-7322
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve breakdown voltage and reduce the occurrence of element breakdown. To do.
  • the present invention includes a first semiconductor layer having first and second main surfaces facing each other, made of a first conductivity type semiconductor, and in contact with the first main surface, and the first semiconductor
  • a second semiconductor layer made of a first-conductivity-type semiconductor having a lower impurity concentration than the layer, a plurality of grooves formed in the surface of the second semiconductor layer, a gate electrode formed in the groove,
  • On the surface of the second semiconductor layer a first region of the second conductivity type formed between the two grooves, and on the surface of the second semiconductor layer, the first region A first carrier extraction region of a second conductivity type formed so as to be in contact with the groove and in contact with the first region; and on the surface of the second semiconductor layer, the first carrier extraction region A second conductivity type second electrode formed in contact with the groove and in contact with the first carrier extraction region;
  • a semiconductor device comprising a second electrode in contact with and having a metal force.
  • the depth of the first carrier extraction region of the surface force of the second semiconductor layer may be greater than the depth of the second carrier extraction region from the surface of the second semiconductor layer. .
  • the depth of the second carrier extraction region of the surface force of the second semiconductor layer is determined by the second of the groove in contact with both the first carrier extraction region and the second carrier extraction region. It may be smaller than the depth of the surface force of the semiconductor layer.
  • the width of the groove contacting both the first carrier extraction region and the second carrier extraction region may be larger than the widths of the other grooves.
  • the depth of the surface force of the second semiconductor layer in the groove that contacts both the first carrier extraction region and the second carrier extraction region depends on the second semiconductor of the other groove. It may be larger than the depth of the surface force of the body layer.
  • the present invention provides the first main surface of the first semiconductor layer having the first and second main surfaces facing each other and formed of a first conductivity type semiconductor.
  • Forming a pattern of an oxide film made of a semiconductor oxide on a second semiconductor layer having a semiconductor power of the first conductivity type having a lower impurity concentration than that of the semiconductor layer, and a pattern of the oxide film As a mask, a second conductivity type impurity is implanted, and the impurity is diffused into the second semiconductor layer to form a second conductivity type first carrier extraction region and the second conductivity type.
  • Forming a second carrier extraction region of the second conductivity type separated from the carrier extraction region of 1, the second semiconductor layer, the first carrier extraction region, and the second carrier extraction region The pattern of the acid coating covering the surface of Forming a groove in contact with the first carrier extraction region and the second carrier extraction region by etching using the oxide film pattern as a mask, and a plurality of other grooves, Forming a gate electrode so as to fill the groove, forming a second conductivity type first region between the plurality of grooves, and forming a first electrode on the surface of the first carrier extraction region; Forming a second region of the second conductivity type having an impurity concentration higher than that of the first carrier extraction region, and having an impurity concentration higher than that of the second carrier extraction region on the surface of the second carrier extraction region Forming a third region of the second conductivity type, and forming a fourth region of the first conductivity type having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
  • the second The first electrode made of metal is formed in contact
  • FIG. 1 is a sectional view showing a sectional structure of a semiconductor device la according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view for explaining a manufacturing process for the semiconductor device la.
  • FIG. 3 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 4 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 5 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 6 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
  • FIG. 7 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 8 is a cross-sectional view for explaining a manufacturing step for the semiconductor device la.
  • FIG. 9 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 10 is a cross-sectional view for illustrating a manufacturing step for the semiconductor device la.
  • FIG. 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lb according to a second embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing a cross-sectional structure of a semiconductor device lc according to a modification of the second embodiment.
  • FIG. 13 is a cross-sectional view showing a cross-sectional structure of a conventional semiconductor device 2.
  • Drain electrode film 115, 116 , 120, 121, 122, 123... Acid film, 117, 118 ⁇ ⁇ ⁇ Implanted layer, 119 ⁇ ⁇ ⁇ Resist film, 124, 224 ⁇ ⁇ Interlayer insulating film, 301, 302 ⁇ ⁇ ⁇ Main surface.
  • FIG. 1 shows a cross-sectional structure of a semiconductor device la according to the first embodiment of the present invention.
  • the drain layer 101 containing a high-concentration N-type impurity has two main surfaces 301 and 302 facing each other, and constitutes an N + type silicon substrate.
  • a drift layer 102 containing a low concentration N-type impurity is formed on the main surface 301 of the drain layer 101.
  • a P-type body region 103 containing P-type impurities is formed in the surface region of the drift layer 102.
  • a P + type diffusion region 104 containing P-type impurities at a higher concentration than the P-type body region 103 is formed.
  • an N + type source region 105 containing a high concentration N-type impurity is also formed so as to sandwich the P + type diffusion region 104.
  • a plurality of trenches 106 having a rectangular cross-sectional shape are formed.
  • a gate insulating film 107 is formed on the inner surface (including the side wall surface 106a and the bottom surface 106b) of the trench 106.
  • a gate electrode 108 having a polysilicon force surrounded by a gate insulating film 107 is formed inside the trench 106.
  • Two carrier extraction regions 109 and 110 containing a P-type impurity are formed in the surface region of the drift layer 102.
  • the carrier extraction region 109 is in contact with the trench 106 in contact with the P-type body region 103 and is also in contact with the P-type body region 103.
  • the carrier extraction region 109 is in contact with the outermost trench 106.
  • the carrier extraction region 110 is in contact with the trench 106 in contact with the carrier extraction region 109 and is separated from the carrier extraction region 109.
  • the depth of the carrier extraction region 109 having the surface force of the drift layer 102 (distance X in the figure) is larger than the depth of the carrier extraction region 110 having the surface force of the drift layer 102 (distance X in the drawing).
  • Minority carriers injected into the drift layer 102 during the operation of the semiconductor device la flow into the extraction regions 109 and 110. This alleviates minority carrier concentration and destroys the device. Can be prevented.
  • a P + type diffusion region 111 containing a high concentration of P type impurities is formed on the surfaces of the carrier extraction regions 109 and 110.
  • a source electrode film 112 that is in contact with the P + type diffusion region 104 and the N + type source region 105 and also has a metal force is formed on the surface of the drift layer 102.
  • the source electrode film 112 is also in contact with the carrier extraction regions 109 and 110 and the P + type diffusion region 111.
  • the source electrode film 112 is isolated from the gate electrode 108 by the interlayer insulating film 124.
  • the carrier extraction regions 109 and 110 are electrically connected to the source electrode film 112 through the P + type diffusion region 111.
  • a part of the surface of the carrier extraction region 110 is covered with an insulating film 113 made of SiO.
  • a drain electrode film 114 made of metal is formed on the main surface 302 of the drain layer 101.
  • the drain electrode film 114 forms an ohmic junction with the drain layer 101.
  • the drain layer 101, the drift layer 102, the P-type body region 103, the N + type source region 105, the gate electrode 108, the source electrode film 112, the drain electrode film 114, and the interlayer insulating film 124 constitute a MOSFET.
  • a plurality of MOSFET structures are formed in the active region.
  • Figure 1 shows the structure around the outer edge of the active area.
  • Carrier extraction regions 109 and 110 are formed outside the active region.
  • the trench 106 is formed so that all the trenches 106 have the same width (distance X in the figure).
  • the trenches 106 are formed so that all the trenches 106 have the same depth from the drift layer 102 (distance X in the figure). Around the outer edge of the active area shown in Figure 1
  • the mask shape In order to prevent this, it is desirable to design the mask shape so that the width of the outermost trench 106 is wider than the width of the other trenches 106.
  • the width of the outer trench 106 becomes wider than the width of the other trench 106, the depth of the outer trench 106 becomes smaller than that of the other trench 106 due to the microloading effect that the etching rate changes according to the pattern dimension. Greater than depth.
  • the drift layer 102 is formed by epitaxially growing silicon containing N-type impurities on the surface of the drain layer 101.
  • the P-type body region 103 is formed by injecting P-type impurities as well as the surface force of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range.
  • the P + type diffusion region 104 is formed by selectively injecting a surface force P-type impurity of the P-type body region 103 and diffusing the impurity at a high temperature within a range of a predetermined surface force depth.
  • the N + type source region 105 is formed by selectively injecting an N type impurity from the surface of the P type body region 103 and diffusing the impurity at a high temperature within a predetermined depth from the surface.
  • the carrier extraction regions 109 and 110 are formed by injecting P-type impurities from the surface of the drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth range.
  • the P + type diffusion region 111 is formed by selectively injecting the surface force P-type impurities of the carrier extraction regions 109 and 110 and diffusing the impurities at a high temperature within a predetermined depth range. ing.
  • a mesa structure is formed including the surfaces of the P-type body region 103, the P + type diffusion region 104, and the N + type source region 105 that are in contact with the source electrode film 112. .
  • the trench 106 is formed by etching the drift layer 102.
  • the gate insulating film 107 is formed by oxidizing the surface of the trench 106 in a high-temperature oxygen atmosphere.
  • the gate electrode 108 is formed by depositing polysilicon containing an N-type impurity on the surface of the gate insulating film 107.
  • the source electrode film 112 and the drain electrode film 114 are formed, for example, by sputtering an electrode material.
  • the impurity concentration of the drain layer 101 is, for example, 10 19 — 10 2 G cm ⁇ 3 .
  • the impurity concentration on the surface of the P-type body region 10 3 is, for example, 10 17 ⁇ 10 18 cm ⁇ 3 .
  • the impurity concentration at the surface of the P + type diffusion region 104 and the P + type diffusion region 111 is, for example, 10 18 ⁇ 10 19 cm ⁇ 3 .
  • the impurity concentration on the surface of the N + type source region 105 is, for example, 10 19 ⁇ 10 2 G cm ⁇ 3 .
  • the impurity concentration at the surface of the carrier extraction regions 109 and 110 is, for example, 10 1 7 ⁇ 10 18 cm ⁇ 3 .
  • Source electrode film 112 is grounded and drained.
  • a positive voltage is applied to the gate electrode film 114 and a positive voltage is applied to the gate electrode 108, an inversion layer is formed at the interface between the P-type body region 103 and the trench 106, and the drain electrode film 114 moves toward the source electrode film 112.
  • Current flows by force.
  • the ground force is also applied to the gate electrode 108 as its state force, the inversion layer formed at the interface between the P-type body region 103 and the trench 106 is extinguished, and the current is cut off.
  • the parasitic diode formed by the drift layer 102, the P-type body region 103, and the P + type diffusion region 104 is in order. Biased and current flows through the parasitic diode. Minority carriers are injected into the drift layer 102 by the current. In this state, when the voltage between the source electrode film 112 and the drain electrode film 114 is inverted, the minority carriers injected into the drift layer 102 flow into the P-type body region 103 connected to the source electrode film 112.
  • the drift layer 102 is formed by epitaxial growth on the main surface 301 of the drain layer 101, and an oxide such as SiO is deposited on the drift layer 102 to form an oxide film 115 (FIG. 2).
  • a resist is applied on the oxide film 115, and a resist pattern is formed by a photographic process.
  • the oxide film 115 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed (FIG. 3).
  • P-type impurities such as B (boron) are added to the surface of the drift layer 102 so as to pass through the oxide film 116.
  • Implantation forms implant layers 117 and 118 (FIG. 4).
  • a resist is applied on the oxide film 115, and a pattern of the resist film 119 is formed by a photographic process.
  • a P-type impurity is again implanted into the implantation layer 117 (FIG. 5).
  • the process shown in FIGS. 3 to 5 may be constituted by a process of forming only the injection layer 117 and a process of forming only the injection layer 118.
  • the resist film 119 is removed and annealing is performed in a high-temperature oxygen atmosphere, the P-type impurities in the implantation layers 117 and 118 diffuse into the drift layer 102, and the carrier extraction regions 109 and 110 become Formed ( Figure 6).
  • the surface of the drift layer 102 is oxidized to form an oxide film 120 (FIG. 7).
  • a resist is applied on the oxide film 120, and a resist pattern is formed by a photographic process.
  • the oxide film 120 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed. At this time, an insulating film 113 is formed.
  • Thermal oxidation is performed in a high-temperature oxygen atmosphere to form a thin oxide film 121 on the surface of the drift layer 102 other than the portion covered with the oxide film 120.
  • An oxide film 122 (NS G: Non-doped Silicate Glass) is deposited on the oxide film 121 by CVD (Chemical Vapor Deposition) (FIG. 8).
  • a film composed of the oxide films 121 and 122 is referred to as an oxide film 123.
  • a resist is applied on the oxide film 123, and a resist pattern is formed by a photographic process.
  • alignment of the photomask is performed so that an opening of the resist is formed between the carrier extraction region 109 and the carrier extraction region 110.
  • the oxide film 123 is etched to expose the surface of the drift layer 102, and then the resist is removed.
  • the drift layer 102 is etched to form a trench 106 (FIG. 9).
  • the depth of the trench 106 A in which the width of the outermost trench 106 A is larger than the width of the other trench 106 is larger than the depth of the other trench 106.
  • the oxide film 123 is removed, and the gate insulating film 107 is formed by thermal oxidation in a high-temperature oxygen atmosphere.
  • Polysilicon is deposited so as to fill trench 106 and cover the surface of drift layer 102. This polysilicon is etched to a height near the surface of the drift layer 102 to form a gate electrode 108.
  • Thermal oxidation is performed in a high-temperature oxygen atmosphere, and the gate electrode The surface of 108 is covered with a gate insulating film 107.
  • a resist is applied on the surface of the drift layer 102, and a resist pattern is formed through a photographic process, in which the region where the P-type body region 103 is formed is exposed.
  • P-type impurities such as B are implanted into the surface of the drift layer 102. After removing the resist and annealing at a high temperature, the implanted P-type impurities diffuse into the drift layer 102. A P-type body region 103 is formed.
  • the P + type diffusion regions 104 and 111 are formed. It is formed.
  • an N type impurity such as As (arsenic) is selectively implanted into the surface of the P type body region 103 and annealing is performed at a high temperature, an N + type diffusion region 105 is formed.
  • the gate insulating film 107 above the upper surface of the gate electrode 108 is etched.
  • An interlayer insulating film 124 is formed by CVD, and a portion of the interlayer insulating film 124 that is exposed outside the trench 106 is etched.
  • An electrode material is deposited on the surface of the drift layer 102 to form the source electrode film 112, and an electrode material is deposited on the main surface 302 of the drain layer 101 to form the drain electrode film 114 (FIG. 10).
  • FIG. 11 shows a cross-sectional structure of the semiconductor device lb according to the present embodiment. Structures having the same functions as those shown in FIG. 1 are given the same reference numerals.
  • the depth of the surface force of the drift layer 102 in the carrier extraction region 110 is the outermost tray.
  • the depth from the surface of the drift layer 102 of the 106A is smaller (distance X in the figure)! /.
  • FIG. 12 shows a cross-sectional structure of a semiconductor device lc according to a modification of the present embodiment. Structures having the same functions as those shown in Fig. 1 are given the same reference numerals.
  • the width of the outermost trench 106A (distance X in the figure) is larger than the width of other trenches 106 (distance X in the figure). This is the outermost
  • the shape of the mask is designed so that the width of one trench 106 is wider than the width of the other trench 106.
  • the depth (distance X in the figure) of the outermost trench 106A from the surface of the drift layer 102 is different from the surface of the drift layer 102 of the other trench 106. Greater than the depth (distance X in the figure).
  • the breakdown voltage can be improved and the occurrence of device breakdown can be reduced.

Abstract

Selon l'invention, sur la région de surface d'une couche de dérive (102), deux régions d'extraction de porteuses (109, 110) renfermant une impureté de type P sont formées. La région d'extraction de porteuses (109) est amenée en contact avec une tranchée (106) étant en contact avec une région de corps de type P (103) et la région d'extraction est également amenée en contact avec la région de corps de type P (103). La région d'extraction de porteuses (109) est également amenée en contact avec la tranchée située le plus à l'extérieur (106). La région d'extraction de porteuses (110) est amenée en contact avec la tranchée (106) étant en contact avec la région d'extraction de porteuses (109) et est séparée de celle-ci (109). Un petit nombre de porteuses, ayant été injecté dans la couche de dérive (102) alors qu'un dispositif semi-conducteur (1a) est mis en oeuvre, s'écoule dans les régions d'extraction de porteuses (109, 110).
PCT/JP2005/001331 2005-01-31 2005-01-31 Dispositif semi-conducteur et procédé de fabrication de celui-ci WO2006082618A1 (fr)

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JP2007501456A JP4794546B2 (ja) 2005-01-31 2005-01-31 半導体装置およびその製造方法
PCT/JP2005/001331 WO2006082618A1 (fr) 2005-01-31 2005-01-31 Dispositif semi-conducteur et procédé de fabrication de celui-ci

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JP2008294240A (ja) * 2007-05-25 2008-12-04 Panasonic Corp 半導体装置及びその製造方法
JP2013084905A (ja) * 2011-09-27 2013-05-09 Denso Corp 縦型半導体素子を備えた半導体装置
US9825164B2 (en) 2013-08-01 2017-11-21 Mitsubishi Electric Corporation Silicon carbide semiconductor device and manufacturing method for same
WO2018074425A1 (fr) * 2016-10-17 2018-04-26 富士電機株式会社 Dispositif à semi-conducteur
US20220254875A1 (en) * 2019-10-28 2022-08-11 Suzhou Oriental Semiconductor Co., Ltd. Semiconductor power device terminal structure

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JP2005019734A (ja) * 2003-06-26 2005-01-20 Renesas Technology Corp 半導体装置およびその製造方法

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JPH09275212A (ja) * 1996-04-04 1997-10-21 Hitachi Ltd 電圧駆動型半導体装置
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Publication number Priority date Publication date Assignee Title
JP2008294240A (ja) * 2007-05-25 2008-12-04 Panasonic Corp 半導体装置及びその製造方法
JP2013084905A (ja) * 2011-09-27 2013-05-09 Denso Corp 縦型半導体素子を備えた半導体装置
US9825164B2 (en) 2013-08-01 2017-11-21 Mitsubishi Electric Corporation Silicon carbide semiconductor device and manufacturing method for same
WO2018074425A1 (fr) * 2016-10-17 2018-04-26 富士電機株式会社 Dispositif à semi-conducteur
CN109075192A (zh) * 2016-10-17 2018-12-21 富士电机株式会社 半导体装置
JPWO2018074425A1 (ja) * 2016-10-17 2019-02-21 富士電機株式会社 半導体装置
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US20220254875A1 (en) * 2019-10-28 2022-08-11 Suzhou Oriental Semiconductor Co., Ltd. Semiconductor power device terminal structure

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