JPH0878668A - Semiconductor device for power - Google Patents

Semiconductor device for power

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Publication number
JPH0878668A
JPH0878668A JP6206799A JP20679994A JPH0878668A JP H0878668 A JPH0878668 A JP H0878668A JP 6206799 A JP6206799 A JP 6206799A JP 20679994 A JP20679994 A JP 20679994A JP H0878668 A JPH0878668 A JP H0878668A
Authority
JP
Japan
Prior art keywords
type
layer
type semiconductor
resurf
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6206799A
Other languages
Japanese (ja)
Inventor
Kenichi Matsushita
憲一 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6206799A priority Critical patent/JPH0878668A/en
Publication of JPH0878668A publication Critical patent/JPH0878668A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: To provide a semiconductor device for power which is high enough in breakdown strength and besides does not incur the increase of cost. CONSTITUTION: This semiconductor device is equipped with a semiconductor element region for power, which has an IGBT, being made in an n<-> -type semiconductor substrate 1, and a resurf structure 16, which is made in the n<-> -type semiconductor substrate 1, and a p-type base layer 2, which constitutes the termination of junction together with first trench groove and the n<-> -type semiconductor substrate la is made on the surface of the n<-> -type semiconductor substrate in the semiconductor element region for power. And the resurf structure 16 consists of a p<-> -type resurf layer 3 which contacts with a p-type base layer 2, being made on the surface of the n<-> -type semiconductor substrate 1, and a second trench groove which is made on the surface of this p<-> -type resurf layer 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、リサーフ構造を有する
電力用半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device having a resurf structure.

【０００２】[0002]

【従来の技術】図１０には電力用半導体素子の一つであ
るトレンチゲート型ＩＧＢＴの素子断面図が示されてい
る。図中、１０１は高抵抗のｎ- 型半導体基板（ｎ- 型
ベース層）を示しており、このｎ- 型半導体基板１０１
の表面には複数のトレンチ溝が選択的に形成されてい
る。このトレンチ溝はゲート絶縁膜１０５を介してゲー
ト電極１０４により充填されている。2. Description of the Related Art FIG. 10 shows a sectional view of a trench gate type IGBT which is one of power semiconductor elements. In the figure, 101 is a high-resistance n - represents the - (type base layer n), the n - -type semiconductor substrate type semiconductor substrate 101
A plurality of trench grooves are selectively formed on the surface of the. The trench groove is filled with the gate electrode 104 via the gate insulating film 105.

【０００３】また、トレンチ溝間のｎ- 型半導体基板１
０１の表面にはｐ型ベース層１０２が形成され、このｐ
型ベース層１０２の表面にｎ型ソース層１０７が選択的
に形成されている。The n -- type semiconductor substrate 1 between the trench grooves is also used.
On the surface of 01, a p-type base layer 102 is formed.
An n-type source layer 107 is selectively formed on the surface of the mold base layer 102.

【０００４】このｎ型ソース層１０７およびｐ型ベース
層１０２の表面にはカソード電極１０６が設けられてい
る。また、ｎ- 型半導体基板１０１の表面に形成された
ｎ+型ストッパ層１１２の表面にはストッパ電極１１３
が設けられている。A cathode electrode 106 is provided on the surfaces of the n-type source layer 107 and the p-type base layer 102. The stopper electrode 113 is formed on the surface of the n + type stopper layer 112 formed on the surface of the n − type semiconductor substrate 101.
Is provided.

【０００５】一方、ｎ- 型半導体基板１０１の裏面には
ｐ+ 型ドレイン層１０８が形成されており、このｐ+ 型
ドレイン層１０８の表面にはドレイン電極１０９が設け
られている。On the other hand, ap + type drain layer 108 is formed on the back surface of the n − type semiconductor substrate 101, and a drain electrode 109 is provided on the surface of this p + type drain layer 108.

【０００６】トレンチゲート型ＩＧＢＴは電力用半導体
素子であるので、ｎ- 型半導体基板１０１には高耐圧化
のための特別の構造が形成されている。すなわち、トレ
ンチゲート型ＩＧＢＴの接合終端（ｎ- 型半導体基板１
０１とストッパ電極１１３に最も近いｐ型ベース層１０
２との接合面）の周囲には、第１のｐ- 型リサーフ層１
０３、第２のｐ- - 型リサーフ層１１５からなる２段リ
サーフ構造１１６が形成されている。Since the trench gate type IGBT is a power semiconductor element, the n -- type semiconductor substrate 101 has a special structure for increasing the breakdown voltage. That is, the junction termination of the trench gate type IGBT (n − type semiconductor substrate 1
01 and the p-type base layer 10 closest to the stopper electrode 113
The first p − -type RESURF layer 1 is formed around the bonding surface 2).
03, the two-step RESURF structure 116 including the second p − − -type RESURF layer 115 is formed.

【０００７】リサーフ構造の電界を緩和する効果は、リ
サーフ層のドーズ量、幅、深さにより調整できるが、図
１０の場合のように、場所によってドーズ量、幅、深さ
を変えるという多段リサーフ構造は、単段リサーフ構造
に比べて、より効果的に電界を緩和することができる。The effect of relaxing the electric field of the RESURF structure can be adjusted by the dose amount, width and depth of the RESURF layer, but as in the case of FIG. 10, the dose amount, width and depth are changed depending on the location. The structure can relax the electric field more effectively than the single-stage RESURF structure.

【０００８】しかしながら、多段リサーフ構造を形成す
るためには、単段リサーフ構造の場合に比べて、リサー
フ層の作成に必要なマスク数や、製造プロセス数が増加
するため、コストが上昇するという問題がある。However, in order to form the multi-stage RESURF structure, the number of masks required for forming the RESURF layer and the number of manufacturing processes are increased as compared with the case of the single-stage RESURF structure, so that the cost is increased. There is.

【０００９】図１１には従来の他のＩＧＢＴの素子断面
図が示されている。図中、２０１は高抵抗のｎ- 型半導
体基板（ｎ- 型ベース層）を示しており、このｎ- 型半
導体基板２０１の表面にはｐ型ベース層２０２が選択的
に形成されている。FIG. 11 shows a sectional view of an element of another conventional IGBT. In the figure, reference numeral 201 denotes a high resistance n − type semiconductor substrate (n − type base layer), and a p type base layer 202 is selectively formed on the surface of the n − type semiconductor substrate 201.

【００１０】このｐ型ベース層２０２の表面にはｎ+ 型
ソース層２０７が選択的に形成されており、このｎ+ 型
ソース層２０７およびｐ型ベース層２０２の表面にはソ
ース電極２０６が設けられている。また、ｎ- 型半導体
基板２０１の表面に形成されたｎ+ 型ストッパ層２１２
の表面にはストッパ電極２１３が設けられている。An n + type source layer 207 is selectively formed on the surface of the p type base layer 202, and a source electrode 206 is provided on the surfaces of the n + type source layer 207 and the p type base layer 202. Has been. In addition, the n + type stopper layer 212 formed on the surface of the n − type semiconductor substrate 201.
A stopper electrode 213 is provided on the surface of the.

【００１１】ｎ+ 型ソース層２０７とｎ- 型半導体基板
２０１とで挟まれたｐ型ベース層２０２上にはゲート絶
縁膜２０５を介してゲート電極２０４が配設されてい
る。一方、ｎ- 型半導体基板２０１の裏面にはｐ+ 型ド
レイン層２０８が形成されており、このｐ+ 型ドレイン
層２０８の表面にはドレイン電極２０９が設けられてい
る。A gate electrode 204 is provided on a p-type base layer 202 sandwiched between an n + type source layer 207 and an n − type semiconductor substrate 201 with a gate insulating film 205 interposed therebetween. On the other hand, ap + type drain layer 208 is formed on the back surface of the n − type semiconductor substrate 201, and a drain electrode 209 is provided on the surface of this p + type drain layer 208.

【００１２】そして、ＩＧＢＴの接合終端（ｎ- 型半導
体基板２０１とｐ型ベース層２０２との接合面）の周囲
には、一つのｐ- 型リサーフ層２０３が形成されてい
る。図１２は、ソース電極２０６とドレイン電極２０９
との間、およびソース電極２０６とストッパ電極２１３
との間に逆電圧を印加した場合のソース電極２０６とス
トッパ電極２１３との間の基板表面の電界分布を示す図
である。なお、縦軸は電界の大きさ（電界の絶対値）を
示している。Further, one p − type RESURF layer 203 is formed around the junction termination (junction surface between the n − type semiconductor substrate 201 and the p type base layer 202) of the IGBT. FIG. 12 shows a source electrode 206 and a drain electrode 209.
Between the source electrode 206 and the stopper electrode 213.
FIG. 6 is a diagram showing an electric field distribution on the substrate surface between a source electrode 206 and a stopper electrode 213 when a reverse voltage is applied between and. The vertical axis represents the magnitude of the electric field (absolute value of the electric field).

【００１３】このような逆電圧が印加されるとｐ- 型リ
サーフ層２０３は空乏化し、図１２に示すように、ｐ-
型リサーフ層２０３の両端側にはそれぞれ強い電界Ｅ
１，Ｅ２が発生する。[0013] Such a reverse voltage is applied p - type RESURF layer 203 is depleted, as shown in FIG. 12, p -
A strong electric field E is applied to both ends of the RESURF layer 203.
1 and E2 occur.

【００１４】ｐ- 型リサーフ層２０３のドーズ量、幅、
深さを変えると、電界Ｅ１，Ｅ２の値は変化し、そし
て、これら電界Ｅ１，Ｅ２のどちらかが臨界値（約２×
１０5Ｖ／ｃｍ）を少しでも越えると、ブレークダウン
電流が流れ、耐圧が急激に低下してしまう。The dose amount, width, and p - type RESURF layer 203
When the depth is changed, the values of the electric fields E1 and E2 change, and either of the electric fields E1 and E2 has a critical value (about 2 ×
If it exceeds 10 5 V / cm even for a short time, a breakdown current will flow and the breakdown voltage will drop sharply.

【００１５】したがって、単段リサーフ構造において高
い耐圧を確保するには、電界Ｅ１，Ｅ２のバランスが崩
れないように、つまり、逆電圧が増加してもＥ１＝Ｅ２
を維持できるように、ｐ- 型リサーフ層２０３のドーズ
量（不純物の濃度プロファイル）を設定しなければなら
ない。Therefore, in order to secure a high breakdown voltage in the single-stage RESURF structure, the balance between the electric fields E1 and E2 is not disturbed, that is, E1 = E2 even if the reverse voltage is increased.
The dose amount (impurity concentration profile) of the p − -type RESURF layer 203 must be set so that the above can be maintained.

【００１６】しかしながら、最適なドーズ量を見出すの
は困難であり、しかも、ドーズ量を最適化できたとして
も、理想耐圧の約８０％しか実際には実現できない。よ
って、単段リサーフ構造では、多段リサーフ構造の場合
のように高耐圧を実現するのは困難である。However, it is difficult to find the optimum dose amount, and even if the dose amount can be optimized, only about 80% of the ideal withstand voltage can actually be realized. Therefore, with the single-stage RESURF structure, it is difficult to realize a high breakdown voltage as in the case of the multi-stage RESURF structure.

【００１７】[0017]

【発明が解決しようとする課題】上述の如く、従来の多
段リサーフ構造を有する電力用半導体装置では、コスト
が増加するという問題があった。また、単段リサーフ構
造を有する電力用半導体装置では、十分に高い耐圧を得
ることができないという問題があった。As described above, the conventional power semiconductor device having the multi-stage resurf structure has a problem of increased cost. Further, in the power semiconductor device having the single-stage RESURF structure, there is a problem that a sufficiently high breakdown voltage cannot be obtained.

【００１８】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、耐圧が十分に高く、し
かも、コストの増加を招かない電力用半導体装置を提供
することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power semiconductor device having a sufficiently high breakdown voltage and not causing an increase in cost.

【００１９】[0019]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の電力用半導体装置（請求項１）は、第１
導電型半導体基板に形成された電力用半導体素子領域
と、前記第１導電型半導体基板に形成されたリサーフ構
造とを備え、前記電力用半導体素子領域の前記第１導電
型半導体基板の表面には、第１のトレンチ溝ならびに前
記第１導電型半導体基板と伴に接合終端を構成する第１
の第２導電型半導体層が形成され、前記リサーフ構造
は、前記第１導電型半導体基板の表面に形成され、前記
第１の第２導電型半導体層と接する低濃度の第２の第２
導電型半導体層と、この第２の第２導電型半導体層の表
面に形成されたトレンチ溝とからなることを特徴とす
る。In order to achieve the above object, a power semiconductor device (claim 1) according to the present invention has a first structure.
A power semiconductor element region formed on a conductive type semiconductor substrate; and a RESURF structure formed on the first conductive type semiconductor substrate, wherein a surface of the first conductive type semiconductor substrate in the power semiconductor element region is provided. A first trench groove and a first termination forming junction end together with the first conductivity type semiconductor substrate
Second conductivity type semiconductor layer is formed, the RESURF structure is formed on the surface of the first conductivity type semiconductor substrate, and the second low concentration second contact layer is in contact with the first second conductivity type semiconductor layer.
It is characterized by comprising a conductive type semiconductor layer and a trench groove formed on the surface of the second second conductive type semiconductor layer.

【００２０】また、本発明の他の電力用半導体装置（請
求項２）は、第１導電型半導体基板に形成された電力用
半導体素子領域と、前記第１導電型半導体基板に形成さ
れたリサーフ構造とを備え、前記電力用半導体素子領域
の前記第１導電型半導体基板の表面には、第１の第１導
電型半導体層ならびに前記第１の第１導電型半導体基板
と伴に接合終端を構成する第１の第２導電型半導体層が
形成され、前記リサーフ構造は、前記第１導電型半導体
基板の表面に形成され、前記第１の第２導電型半導体層
と接する低濃度の第２の第２導電型半導体層と、この第
２の第２導電型半導体層の表面に形成された第２の第１
導電型半導体層とからなることを特徴とする。Another power semiconductor device of the present invention (claim 2) is a power semiconductor element region formed on a first conductivity type semiconductor substrate and a RESURF formed on the first conductivity type semiconductor substrate. And a junction termination on the surface of the first conductivity type semiconductor substrate in the power semiconductor element region together with the first first conductivity type semiconductor layer and the first first conductivity type semiconductor substrate. A first second-conductivity-type semiconductor layer is formed, the RESURF structure is formed on the surface of the first-conductivity-type semiconductor substrate, and a second low-concentration second layer is in contact with the first second-conductivity-type semiconductor layer. Second conductive type semiconductor layer and a second first conductive layer formed on the surface of the second second conductive type semiconductor layer.
It is characterized by comprising a conductive type semiconductor layer.

【００２１】[0021]

【作用】本発明（請求項１）によれば、低濃度の第２の
第２導電型半導体層表面にトレンチ溝が形成されている
ので、このトレンチ溝が存在する部分の第２の第２導電
型半導体層の不純物濃度は他の部分よりも低くなり、こ
れにより、実効的（等価的）に多段リサーフ構造が形成
されたことになる。したがって、単段リサーフ構造でも
多段リサーフ構造と同様に高耐圧を実現できるようにな
る。According to the present invention (claim 1), since the trench groove is formed on the surface of the second semiconductor layer of the second conductivity type having a low concentration, the second second portion of the portion where the trench groove exists. The impurity concentration of the conductive type semiconductor layer is lower than that of the other portions, which effectively (equivalently) forms the multi-stage RESURF structure. Therefore, a high breakdown voltage can be realized in the single-stage RESURF structure as in the multi-stage RESURF structure.

【００２２】また、前記トレンチ溝は、電力半導体素子
領域のトレンチ溝を形成する際に同時に形成すれば、製
造プロセスが増加したり、複雑化することはない。本発
明（請求項２）によれば、低濃度の第２の第２導電型半
導体層表面に第２の第１導電型半導体層が形成されてい
るので、この第２の第１導電型半導体層が存在する部分
の第２の第２導電型半導体層の不純物濃度は他の部分よ
りも低くなり、これにより、実効的（等価的）に多段リ
サーフ構造が形成されたことになる。したがって、単段
リサーフ構造でも多段リサーフ構造と同様に高耐圧を実
現できるようになる。Further, if the trench groove is formed at the same time when the trench groove in the power semiconductor element region is formed, the manufacturing process will not be increased or complicated. According to the present invention (claim 2), since the second first-conductivity-type semiconductor layer is formed on the surface of the low-concentration second second-conductivity-type semiconductor layer, the second first-conductivity-type semiconductor layer is formed. The impurity concentration of the second second-conductivity-type semiconductor layer in the portion where the layer exists is lower than that in the other portions, which means that the multi-stage RESURF structure is effectively (equivalently) formed. Therefore, a high breakdown voltage can be realized in the single-stage RESURF structure as in the multi-stage RESURF structure.

【００２３】また、前記第２の第１導電型半導体層は、
電力半導体素子領域の第１の第１導電型半導体層を形成
する際に同時に形成すれば、製造プロセスが増加した
り、複雑化することはない。Further, the second first-conductivity-type semiconductor layer is
If the first semiconductor layer of the power semiconductor element region is formed simultaneously with the formation of the first first-conductivity-type semiconductor layer, the manufacturing process will not be increased or complicated.

【００２４】[0024]

【実施例】以下、図面を参照しながら実施例を説明す
る。図１は、本発明の第１の実施例に係る電力用半導体
装置のトレンチゲート型ＩＧＢＴ部の断面図である。Embodiments will be described below with reference to the drawings. FIG. 1 is a sectional view of a trench gate type IGBT portion of a power semiconductor device according to a first embodiment of the present invention.

【００２５】図中、１は高抵抗のｎ- 型半導体基板（ｎ
- 型ベース層）を示しており、このｎ- 型半導体基板１
の表面には複数のトレンチ溝（第１のトレンチ溝）が選
択的に形成されている。このトレンチ溝はゲート絶縁膜
５を介してゲート電極４により充填されている。In the figure, 1 is a high resistance n -- type semiconductor substrate (n
A n - type semiconductor substrate 1 is shown.
A plurality of trench grooves (first trench grooves) are selectively formed on the surface of the. The trench groove is filled with the gate electrode 4 via the gate insulating film 5.

【００２６】また、トレンチ溝間のｎ- 型半導体基板１
の表面にはｐ型ベース層２が形成され、このｐ型ベース
層２の表面にｎ型ソース層７が選択的に形成されてい
る。このｎ型ソース層７およびｐ型ベース層２の表面に
はカソード電極６が設けられている。また、ｎ- 型半導
体基板１１の表面に形成されたｎ+ 型ストッパ層１２に
はストッパ電極１３が設けられている。The n -- type semiconductor substrate 1 between the trench grooves is also used.
A p-type base layer 2 is formed on the surface of, and an n-type source layer 7 is selectively formed on the surface of the p-type base layer 2. A cathode electrode 6 is provided on the surfaces of the n-type source layer 7 and the p-type base layer 2. A stopper electrode 13 is provided on the n + type stopper layer 12 formed on the surface of the n − type semiconductor substrate 11.

【００２７】一方、ｎ- 型半導体基板１の裏面にはｐ+
型ドレイン層８が形成されており、このｐ+ 型ドレイン
層８の表面にはドレイン電極９が設けられている。トレ
ンチゲート型ＩＧＢＴは電力用半導体素子であるので、
ｎ- 型半導体基板１には高耐圧化のためのリサーフ構造
が形成されている。On the other hand, p + is formed on the back surface of the n -- type semiconductor substrate 1.
A type drain layer 8 is formed, and a drain electrode 9 is provided on the surface of the p + type drain layer 8. Since the trench gate type IGBT is a power semiconductor device,
A resurf structure for increasing the breakdown voltage is formed on the n − type semiconductor substrate 1.

【００２８】すなわち、トレンチゲート型ＩＧＢＴの接
合終端（ｎ- 型半導体基板１とストッパ電極１３に最も
近いｐ型ベース層２との接合面）の周囲には、ｐ- 型リ
サーフ層３が形成されており、このｐ- 型リサーフ層３
のストッパ側の表面には、選択的に三つのトレンチ溝１
１1 ，１１2 ，１１3 （第２のトレンチ溝）が形成され
ている。That is, the p − type RESURF layer 3 is formed around the junction end of the trench gate type IGBT (the junction surface between the n − type semiconductor substrate 1 and the p type base layer 2 closest to the stopper electrode 13). This p - type RESURF layer 3
On the stopper side surface of the, three trench grooves 1 are selectively
11 1 , 11 2 and 11 3 (second trench grooves) are formed.

【００２９】各トレンチ溝１１1 ，１１2 ，１１3 の内
面は、それぞれ、絶縁膜１４1 ，１４2 ，１４3 により
覆われ、また、各トレンチ溝１１1 ，１１2 ，１１3 の
上面は絶縁膜１０により覆われている。The inner surface of each trench groove 11 1 , 11 2 , 11 3 is covered with an insulating film 14 1 , 14 2 , 14 3 , respectively, and the upper surface of each trench groove 11 1 , 11 2 , 11 3 is It is covered with the insulating film 10.

【００３０】ストッパ側のｐ- 型リサーフ層３は、トレ
ンチ溝１１1 ，１１2 ，１１3 の分だけ、ｐ- 型リサー
フ層３を構成するｐ- 型の半導体層が減っているので、
ストッパ側のｐ- 型リサーフ層３のドーズ量（不純物濃
度）は、カソード側のそれよりも低くなっている。[0030] p of the stopper-side - -type RESURF layer 3, the amount corresponding trench 11 1, 11 2, 11 3, p - p constituting the type RESURF layer 3 - Since type semiconductor layer is reduced,
The dose amount (impurity concentration) of the p − -type RESURF layer 3 on the stopper side is lower than that on the cathode side.

【００３１】したがって、本実施例のリサーフ構造１６
は、低不純物濃度の拡散層はｐ- 型リサーフ層３の一つ
だけであるが、等価的には図１０の多段リサーフ構造１
１６と同じものである。Therefore, the RESURF structure 16 of this embodiment
Is only one of the p − type RESURF layers 3 having a low impurity concentration, but equivalently, the multi-stage RESURF structure 1 of FIG.
It is the same as 16.

【００３２】また、ｐ- 型リサーフ層３はＩＧＢＴの製
造工程の前に形成されるので、ＩＧＢＴのトレンチ溝、
ゲート絶縁膜５を形成するときに、ｐ- 型リサーフ層３
のトレンチ溝１１1 ，１１2 ，１１3 および絶縁膜１４
1 ，１４2 ，１４3 を同時に形成すれば、製造工程が増
えたり、複雑化するという問題は生じない。Since the p -- type RESURF layer 3 is formed before the manufacturing process of the IGBT, the trench groove of the IGBT,
When forming the gate insulating film 5, the p − -type RESURF layer 3
Trench grooves 11 1 , 11 2 , 11 3 and insulating film 14
If 1 , 14, 2 and 14 3 are formed at the same time, there is no problem that the number of manufacturing steps is increased or the manufacturing process is complicated.

【００３３】したがって、本実施例によれば、多段リサ
ーフ構造を用いた場合と同様に高い耐圧が得られ、しか
も、多段リサーフ構造を用いた場合とは異なりコストの
増加を招かない電力用半導体装置を実現できるようにな
る。Therefore, according to this embodiment, a high breakdown voltage can be obtained as in the case of using the multi-stage RESURF structure, and, unlike the case of using the multi-stage RESURF structure, the power semiconductor device does not increase in cost. Will be realized.

【００３４】図２は、ｐ- 型リサーフ層３のトレンチ溝
パターンを示す平面図である。これは素子領域の周りを
囲むトレンチ溝１１1 ，１１2 ，１１3 を示している。
図３は、ｐ- 型リサーフ層３の他のトレンチ溝パターン
を示す平面図である。これも素子領域の周りを囲むトレ
ンチ溝１１1 ，１１2 ，１１3 を示しているが、図２の
場合とは異なり、トレンチ溝１１1 ，１１2 ，１１3 は
部分的に切断されている。FIG. 2 is a plan view showing a trench groove pattern of the p − type RESURF layer 3. This shows trench grooves 11 1 , 11 2 , and 11 3 surrounding the element region.
FIG. 3 is a plan view showing another trench groove pattern of the p − -type RESURF layer 3. This also shows the trench grooves 11 1 , 11 2 , 11 3 surrounding the element region, but unlike the case of FIG. 2, the trench grooves 11 1 , 11 2 , 11 3 are partially cut. .

【００３５】図４は、本発明の第２の実施例に係る電力
用半導体装置のトレンチゲート型ＩＧＢＴ部の断面図で
ある。なお、図１の電力用半導体装置と対応する部分に
は図１と同一符号を付してあり、詳細な説明は省略す
る。FIG. 4 is a sectional view of a trench gate type IGBT portion of a power semiconductor device according to a second embodiment of the present invention. The portions corresponding to those of the power semiconductor device of FIG. 1 are designated by the same reference numerals as those of FIG. 1, and detailed description thereof will be omitted.

【００３６】本実施例の電力用半導体装置が第１の実施
例のそれと異なる点は、トレンチ溝１１1 ，１１2 ，１
１3 の深さがこの順でより深くなっていることにある。
これにより、実効的に三つのリサーフ層からなる３段リ
サーフ構造が形成されることになる。The power semiconductor device of this embodiment is different from that of the first embodiment in that trench grooves 11 1 , 11 2 , 1 are provided.
The depth of 1 3 is deeper in this order.
As a result, a three-step RESURF structure consisting of three RESURF layers is effectively formed.

【００３７】本発明者の研究によれば、このように構成
された多段リサーフ構造１６によれば、表１に示すよう
に、効果的に耐圧を高くできることが分かった。すなわ
ち、実効的なリサーフ層の数と、リサーフ層の個数が１
個の場合の耐圧を基準とした耐圧向上率を調べたとこ
ろ、実効的なリサーフ層の数を多くすることにより、効
果的に耐圧を向上できることが分かった。According to the research conducted by the present inventor, it has been found that the multi-stage RESURF structure 16 thus constructed can effectively increase the breakdown voltage as shown in Table 1. That is, the effective number of RESURF layers and the number of RESURF layers are 1
When the withstand voltage improvement rate based on the withstand voltage in the case of individual pieces was investigated, it was found that the withstand voltage can be effectively improved by increasing the number of effective RESURF layers.

【００３８】[0038]

【表１】 [Table 1]

【００３９】図５は、本発明の第３の実施例に係る電力
用半導体装置のＩＧＢＴ部の断面図である。図中、２１
は高抵抗のｎ- 型半導体基板（ｎ- 型ベース層）を示
し、このｎ-型半導体基板２１の表面にはｐ型ベース層
２２が選択的に形成されている。FIG. 5 is a sectional view of the IGBT portion of the power semiconductor device according to the third embodiment of the present invention. 21 in the figure
Indicates a high resistance n − type semiconductor substrate (n − type base layer), and a p type base layer 22 is selectively formed on the surface of the n − type semiconductor substrate 21.

【００４０】このｐ型ベース層２２の表面にはｎ+ 型ソ
ース層２７が選択的に形成されており、このｎ+ 型ソー
ス層２７およびｐ型ベース層２２の表面にはソース電極
２６が設けられている。また、ｎ- 型半導体基板２１の
表面に形成されたｎ+ 型ストッパ層３２の表面にはスト
ッパ電極３３が設けられている。An n + type source layer 27 is selectively formed on the surface of the p type base layer 22, and a source electrode 26 is provided on the surfaces of the n + type source layer 27 and the p type base layer 22. Has been. A stopper electrode 33 is provided on the surface of the n + type stopper layer 32 formed on the surface of the n − type semiconductor substrate 21.

【００４１】ｎ+ 型ソース層２７とｎ- 型半導体基板２
１とで挟まれたｐ型ベース層２２の表面には、ゲート絶
縁膜２５を介して、ゲート電極２４が配設されている。
一方、ｎ- 型半導体基板２１の裏面にはｐ+ 型ドレイン
層２８が形成されており、このｐ+ 型ドレイン層２８の
表面にはドレイン電極２９が設けられている。N + type source layer 27 and n − type semiconductor substrate 2
A gate electrode 24 is provided on the surface of the p-type base layer 22 which is sandwiched between 1 and 2, with a gate insulating film 25 interposed therebetween.
On the other hand, ap + type drain layer 28 is formed on the back surface of the n − type semiconductor substrate 21, and a drain electrode 29 is provided on the surface of the p + type drain layer 28.

【００４２】そして、ＩＧＢＴの接合終端（ｎ- 型半導
体基板２１とｐ型ベース層２２との接合面）の周囲に
は、一つのｐ- 型リサーフ層２３が形成されており、こ
のｐ-型リサーフ層２３の表面には選択的にｎ+ 型拡散
層３１1 ，３１2 ，３１3 ，３１4 ，３１5 が形成され
ている。[0042] Then, the bonding end of the IGBT - Around the (n junction surface of the type semiconductor substrate 21 and the p-type base layer 22), a p - type RESURF layer 23 is formed, the p - type On the surface of the RESURF layer 23, n + type diffusion layers 31 1 , 31 2 , 31 3 , 31 4 , 31 5 are selectively formed.

【００４３】本発明者の研究によれば、このように構成
されたリサーフ構造３４によれば、効果的に耐圧を高く
できることが分かった。図８にはそのことを示すリサー
フ層２３の表面の電界分布である。これはソース電極２
６とドレイン電極２９との間、およびソース電極２６と
ストッパ電極３３との間に逆電圧を印加した場合のリサ
ーフ層２３の表面の電界分布である。なお、縦軸は電界
の大きさ（電界の絶対値）を示している。According to the research conducted by the present inventor, it has been found that the resurf structure 34 thus constructed can effectively increase the breakdown voltage. FIG. 8 shows the electric field distribution on the surface of the RESURF layer 23 showing this fact. This is the source electrode 2
6 is an electric field distribution on the surface of the RESURF layer 23 when a reverse voltage is applied between the drain electrode 29 and the drain electrode 29 and between the source electrode 26 and the stopper electrode 33. The vertical axis represents the magnitude of the electric field (absolute value of the electric field).

【００４４】図８から、本実施例の場合、リサーフ層２
３の表面に従来よりも電界が高くなる部分の数（ピーク
を示す部分）が多いことが分かる。したがって、印加す
る逆電圧が同じであれば、つまり、電界分布の曲線と縦
軸と横軸とで囲まれる面積が同じであれば、最大電界値
は本実施例の場合の方が従来よりも低くなる。よって、
本実施例の方が耐圧が高くなる。From FIG. 8, in the case of this embodiment, the resurf layer 2
It can be seen that the surface of No. 3 has a larger number of parts (parts showing peaks) where the electric field is higher than before. Therefore, if the reverse voltage to be applied is the same, that is, if the area surrounded by the curve of the electric field distribution and the vertical axis and the horizontal axis is the same, the maximum electric field value is higher in this example than in the conventional case. Get lower. Therefore,
This embodiment has a higher breakdown voltage.

【００４５】また、ｐ- 型リサーフ層２３はＩＧＢＴの
製造工程の前に形成するので、ＩＧＢＴのｎ+ 型ソース
層２７を形成するときに、同時にｎ+ 型拡散層３１1 〜
３１5 を形成すれば、製造工程が増えたり、複雑化する
という問題は生じない。Further, since the p − type RESURF layer 23 is formed before the manufacturing process of the IGBT, when the n + type source layer 27 of the IGBT is formed, the n + type diffusion layers 31 1 ...
By forming the 31 5, or increasing the manufacturing process, there is no problem that complicated.

【００４６】かくして本実施例によれば、表面にｎ+ 型
拡散層３１1 〜３１5 が選択的に形成されたｐ- 型リサ
ーフ層２３を用いることにより、耐圧が高く、しかも、
コストの上昇を招かない電力用半導体装置を実現できる
ようになる。[0046] Thus, according to this embodiment, p n + -type diffusion layer 31 1-31 5 is selectively formed on the surface - by using a type RESURF layer 23, high breakdown voltage, moreover,
It becomes possible to realize a power semiconductor device that does not increase the cost.

【００４７】図６は、ｐ- 型リサーフ層２３のｎ+ 型拡
散層トレンチ溝パターンを示す平面図である。これは素
子領域の周りを囲むｎ+ 型拡散層３１1 ，３１2 ，３１
3 を示している。FIG. 6 is a plan view showing an n + type diffusion layer trench groove pattern of the p − type RESURF layer 23. This is the n + type diffusion layers 31 1 , 31 2 , 31 surrounding the element region.
3 is shown.

【００４８】図７は、ｐ- 型リサーフ層２３の他のｎ+
型拡散層パターンを示す平面図である。これも素子領域
の周りを囲むｎ+ 型拡散層３１1 ，３１2 ，３１3 を示
しているが、図６の場合とは異なり、ｎ+ 型拡散層３１
1 ，３１2 ，３１3 は部分的に切断されている。FIG. 7 shows another n + of the p − -type RESURF layer 23.
It is a top view showing a type diffusion layer pattern. This also shows the n + type diffusion layers 31 1 , 31 2 , 31 3 surrounding the element region, but unlike the case of FIG. 6, the n + type diffusion layer 31
1 , 31 2 and 31 3 are partially cut.

【００４９】図９は、本発明の第４の実施例に係る電力
用半導体装置のＩＧＢＴ部の断面図である。なお、図５
の電力用半導体装置と対応する部分には図５と同一符号
を付してあり、詳細な説明は省略する。FIG. 9 is a sectional view of the IGBT portion of the power semiconductor device according to the fourth embodiment of the present invention. Note that FIG.
The parts corresponding to those of the power semiconductor device are designated by the same reference numerals as those in FIG. 5, and detailed description thereof will be omitted.

【００５０】本実施例の電力用半導体装置が第３の実施
例のそれと異なる点は、不純物濃度の異なるｎ型拡散層
がｐ- 型リサーフ層２３の表面に選択的に形成されてい
ることになる。The power semiconductor device of this embodiment is different from that of the third embodiment in that n-type diffusion layers having different impurity concentrations are selectively formed on the surface of the p − -type RESURF layer 23. Become.

【００５１】すなわち、ソース側には二つの高濃度のｎ
+ 型拡散層３１1 ，３１2 が形成されており、ストッパ
側には三つの更に高濃度のｎ++型拡散層３１3 ´，３１
4 ´，３１5 ´が形成されている。That is, on the source side, two high concentration n
+ Type diffusion layers 31 1 and 31 2 are formed, and three higher concentration n ++ type diffusion layers 31 3 ′ and 31 3 are formed on the stopper side.
4 ', 31 5' are formed.

【００５２】このように不純物濃度が異なる拡散層の数
を多くし、そして、ストッパ側に向かって不純物濃度が
全体として高くなるように不純物拡散層を配置すれば、
ストッパ側のｐ- 型リサーフ層２３のドーズ量は、カソ
ード側のドーズ料よりも低くなる。By thus increasing the number of diffusion layers having different impurity concentrations and arranging the impurity diffusion layers so that the impurity concentration becomes higher as a whole toward the stopper side,
The dose amount of the p − -type RESURF layer 23 on the stopper side is lower than the dose amount on the cathode side.

【００５３】したがって、リサーフ構造３４は、低不純
物濃度の拡散層はｐ- 型リサーフ層２３の一つだけであ
るが、等価的には図１０の多段リサーフ構造１１６と同
じものとなり、多段リサーフ構造の場合と同様に、耐圧
が高くなる。Therefore, although the RESURF structure 34 has only one diffusion layer having a low impurity concentration as the p -- type RESURF layer 23, it is equivalently the same as the multi-stage RESURF structure 116 in FIG. As in the case of, the breakdown voltage becomes high.

【００５４】なお、ソース側よりもストッパ側のｐ- 型
リサーフ層２３の表面により多くのｎ+ 型拡散層を形成
しても同様な効果が得られることが分かった。そして、
この手法と本実施例の手法とを組み合わせると、第２の
実施例の場合と同様に、効果的に耐圧を高めることでき
ることが分かった。It has been found that the same effect can be obtained even if more n + type diffusion layers are formed on the surface of the p − type RESURF layer 23 on the stopper side than on the source side. And
It has been found that by combining this method with the method of this embodiment, the breakdown voltage can be effectively increased as in the case of the second embodiment.

【００５５】なお、本発明は上述した実施例に限定され
るものではない。例えば、上記実施例では、電力用半導
体素子としてＩＧＢＴを用いた場合について説明した
が、他の電力用半導体素子、例えば、ＧＴＯ、ＩＧＢ
Ｔ，ＩＥＧＴ等でも良い。要は接合終端を有する電力用
半導体素子であれば良い。その他、本発明の要旨を逸脱
しない範囲で、種々変形して実施できる。The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the IGBT is used as the power semiconductor element has been described, but other power semiconductor elements, for example, GTO and IGBT.
It may be T, IEGT or the like. In short, any power semiconductor element having a junction termination may be used. In addition, various modifications can be made without departing from the scope of the present invention.

【００５６】[0056]

【発明の効果】以上詳述したように本発明によれば、低
濃度の第２の第２導電型半導体層内に実効的（等価的）
に低不純物濃度構造を設けることにより、耐圧が十分に
高く、しかも、コストの増加を招かない電力用半導体装
置を実現できるようになる。As described in detail above, according to the present invention, it is effective (equivalent) in the low concentration second semiconductor layer of the second conductivity type.
By providing the low-impurity-concentration structure in the power semiconductor device, it is possible to realize a power semiconductor device that has a sufficiently high breakdown voltage and does not increase the cost.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例に係る電力用半導体装置
のトレンチゲート型ＩＧＢＴ部の断面図FIG. 1 is a sectional view of a trench gate type IGBT portion of a power semiconductor device according to a first embodiment of the present invention.

【図２】ｐ- 型リサーフ層のトレンチ溝パターンを示す
平面図FIG. 2 is a plan view showing a trench groove pattern of a p − type RESURF layer.

【図３】ｐ- 型リサーフ層の他のトレンチ溝パターンを
示す平面図FIG. 3 is a plan view showing another trench groove pattern of the p − type RESURF layer.

【図４】本発明の第２の実施例に係る電力用半導体装置
のトレンチゲート型ＩＧＢＴ部の断面図FIG. 4 is a sectional view of a trench gate type IGBT portion of a power semiconductor device according to a second embodiment of the present invention.

【図５】本発明の第３の実施例に係る電力用半導体装置
のＩＧＢＴ部の断面図FIG. 5 is a sectional view of an IGBT portion of a power semiconductor device according to a third embodiment of the present invention.

【図６】ｐ- 型リサーフ層のｎ+ 拡散層パターンを示す
平面図FIG. 6 is a plan view showing an n + diffusion layer pattern of a p − type RESURF layer.

【図７】ｐ- 型リサーフ層の他のｎ+ 拡散層パターンを
示す平面図FIG. 7 is a plan view showing another n + diffusion layer pattern of the p − type RESURF layer.

【図８】図５の電力用半導体装置のリサーフ層表面の電
界分布を示す図8 is a diagram showing an electric field distribution on the surface of the RESURF layer of the power semiconductor device of FIG.

【図９】本発明の第４の実施例に係る電力用半導体装置
のＩＧＢＴ部の断面図FIG. 9 is a sectional view of an IGBT portion of a power semiconductor device according to a fourth embodiment of the present invention.

【図１０】従来の多段リサーフ構造の問題を説明するた
めの断面図FIG. 10 is a cross-sectional view for explaining the problem of the conventional multi-stage RESURF structure.

【図１１】従来の単段リサーフ構造の問題を説明するた
めの断面図FIG. 11 is a cross-sectional view for explaining the problem of the conventional single-stage RESURF structure.

【図１２】従来の電力用半導体装置内のリサーフ層表面
の電界分布を示す図FIG. 12 is a diagram showing an electric field distribution on the surface of a RESURF layer in a conventional power semiconductor device.

【符号の説明】[Explanation of symbols]

１…ｎ- 型半導体基板（第１導電型半導体基板） ２…ｐ型ベース層（第１の第２導電型半導体層） ３…ｐ- 型リサーフ層（第２の第２導電型半導体層） ４…ゲート電極 ５…ゲート絶縁膜 ６…カソード電極 ７…ｎ型ソース層 ８…ｐ+ 型ドレイン層 ９…ドレイン電極 １０…絶縁膜 １１1 〜１１3 …第２のトレンチ溝（低不純物濃度構
造） １２…ｎ+ 型ストッパ層 １３…ストッパ電極 １４1 〜１４3 …絶縁膜 １６…リサーフ構造 ２１…ｎ- 型半導体基板（第１導電型半導体基板） ２２…ｐ型ベース層（第１の第２導電型半導体層） ２３…ｐ- 型リサーフ層（第２の第２導電型半導体層） ２４…ゲート電極 ２５…ゲート絶縁膜 ２６…ソース電極 ２７…ｎ+ 型ソース層 ２８…ｐ+ 型ドレイン層 ２９…ドレイン電極 ３１1 〜３１5 …ｎ+ 型拡散層 ３２…ｎ+ 型ストッパ層 ３３…ストッパ電極 ３４…リサーフ構造DESCRIPTION OF SYMBOLS 1 ... n - type semiconductor substrate (first conductivity type semiconductor substrate) 2 ... p type base layer (first second conductivity type semiconductor layer) 3 ... p - type RESURF layer (second second conductivity type semiconductor layer) 4 ... Gate electrode 5 ... Gate insulating film 6 ... Cathode electrode 7 ... N type source layer 8 ... P + type drain layer 9 ... Drain electrode 10 ... Insulating film 11 1 to 11 3 ... Second trench groove (low impurity concentration structure) ) 12 ... n ... + -type stopper layer 13 ... stopper electrode 14 1-14 3 ... insulating film 16 RESURF structure 21 ... n - -type semiconductor substrate (first conductivity type semiconductor substrate) 22 ... p-type base layer (first second 2 conductivity type semiconductor layer) 23 ... P - type RESURF layer (second second conductivity type semiconductor layer) 24 ... Gate electrode 25 ... Gate insulating film 26 ... Source electrode 27 ... N + type source layer 28 ... P + type drain layer 29 ... drain electrode 31 1 ~31 5 ... n + -type diffusion 32 ... n + -type stopper layer 33 ... stopper electrode 34 ... RESURF structure

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】第１導電型半導体基板に形成された電力用
半導体素子領域と、 前記第１導電型半導体基板に形成されたリサーフ構造と
を具備してなり、 前記電力用半導体素子領域の前記第１導電型半導体基板
の表面には、第１のトレンチ溝ならびに前記第１導電型
半導体基板と伴に接合終端を構成する第１の第２導電型
半導体層が形成され、 前記リサーフ構造は、前記第１導電型半導体基板の表面
に形成され、前記第１の第２導電型半導体層と接する低
濃度の第２の第２導電型半導体層と、この第２の第２導
電型半導体層の表面に形成されたトレンチ溝とからなる
ことを特徴とする電力用半導体装置。1. A power semiconductor element region formed on a first conductivity type semiconductor substrate, and a RESURF structure formed on the first conductivity type semiconductor substrate. A first trench groove and a first second conductivity type semiconductor layer forming a junction termination together with the first conductivity type semiconductor substrate are formed on the surface of the first conductivity type semiconductor substrate, and the RESURF structure comprises: A second low-concentration second conductivity type semiconductor layer formed on the surface of the first conductivity type semiconductor substrate and in contact with the first second conductivity type semiconductor layer; and a second concentration of the second conductivity type semiconductor layer. A power semiconductor device comprising: a trench groove formed on the surface. 【請求項２】第１導電型半導体基板に形成された電力用
半導体素子領域と、 前記第１導電型半導体基板に形成されたリサーフ構造と
を具備してなり、 前記電力用半導体素子領域の前記第１導電型半導体基板
の表面には、第１の第１導電型半導体層ならびに前記第
１の第１導電型半導体基板と伴に接合終端を構成する第
１の第２導電型半導体層が形成され、 前記リサーフ構造は、前記第１導電型半導体基板の表面
に形成され、前記第１の第２導電型半導体層と接する低
濃度の第２の第２導電型半導体層と、この第２の第２導
電型半導体層の表面に形成された第２の第１導電型半導
体層とからなることを特徴とする電力用半導体装置。2. A power semiconductor element region formed on a first conductivity type semiconductor substrate, and a RESURF structure formed on the first conductivity type semiconductor substrate. On the surface of the first conductivity type semiconductor substrate, a first first conductivity type semiconductor layer and a first second conductivity type semiconductor layer forming a junction termination together with the first first conductivity type semiconductor substrate are formed. The RESURF structure is formed on the surface of the first conductivity type semiconductor substrate and has a low concentration second second conductivity type semiconductor layer in contact with the first second conductivity type semiconductor layer; A power semiconductor device comprising a second first-conductivity-type semiconductor layer formed on a surface of the second-conductivity-type semiconductor layer. 【請求項３】前記第２の第２導電型半導体層の表面に形
成される前記トレンチ溝の深さまたは前記第２の第１の
導電型半導体層の間隔を変えることを特徴とする請求項
１または請求項２に記載の電力用半導体装置。3. The depth of the trench groove formed on the surface of the second second-conductivity-type semiconductor layer or the interval between the second first-conductivity-type semiconductor layers is changed. The power semiconductor device according to claim 1 or 2.
JP6206799A 1994-08-31 1994-08-31 Semiconductor device for power Pending JPH0878668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6206799A JPH0878668A (en) 1994-08-31 1994-08-31 Semiconductor device for power

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6206799A JPH0878668A (en) 1994-08-31 1994-08-31 Semiconductor device for power

Publications (1)

Publication Number Publication Date
JPH0878668A true JPH0878668A (en) 1996-03-22

Family

ID=16529295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6206799A Pending JPH0878668A (en) 1994-08-31 1994-08-31 Semiconductor device for power

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Country Link
JP (1) JPH0878668A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0813250A2 (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Limited Trench semiconductor device
US6476458B2 (en) 2000-11-29 2002-11-05 Denso Corporation Semiconductor device capable of enhancing a withstand voltage at a peripheral region around an element in comparison with a withstand voltage at the element
JP2003529209A (en) * 2000-02-29 2003-09-30 ゼネラル セミコンダクター，インク． Trench double diffused metal oxide semiconductor transistor structure
US6777780B2 (en) 2001-08-07 2004-08-17 Koninklijke Philips Electronics N.V. Trench bipolar transistor
JP2004349556A (en) * 2003-05-23 2004-12-09 Sanken Electric Co Ltd Semiconductor element
USRE38953E1 (en) 1996-04-01 2006-01-31 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method of manufacturing the same
US7045857B2 (en) * 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
WO2006082618A1 (en) * 2005-01-31 2006-08-10 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
JP2007266570A (en) * 2006-03-02 2007-10-11 Denso Corp Insulated gate bipolar transistor
JP2009016618A (en) * 2007-07-05 2009-01-22 Denso Corp Semiconductor device and manufacturing method thereof
US7871888B2 (en) 2007-10-24 2011-01-18 Fuji Electric Systems Co., Ltd. Method of manufacturing semiconductor device
JP2013051434A (en) * 2012-11-05 2013-03-14 Toshiba Corp Semiconductor device
JP2018046139A (en) * 2016-09-14 2018-03-22 三菱電機株式会社 Semiconductor device, and method of manufacturing the same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE38953E1 (en) 1996-04-01 2006-01-31 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method of manufacturing the same
EP0813250A3 (en) * 1996-06-13 1998-10-07 Mitel Semiconductor Limited Trench semiconductor device
EP0813250A2 (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Limited Trench semiconductor device
JP2003529209A (en) * 2000-02-29 2003-09-30 ゼネラル セミコンダクター，インク． Trench double diffused metal oxide semiconductor transistor structure
US6476458B2 (en) 2000-11-29 2002-11-05 Denso Corporation Semiconductor device capable of enhancing a withstand voltage at a peripheral region around an element in comparison with a withstand voltage at the element
US6777780B2 (en) 2001-08-07 2004-08-17 Koninklijke Philips Electronics N.V. Trench bipolar transistor
JP2004349556A (en) * 2003-05-23 2004-12-09 Sanken Electric Co Ltd Semiconductor element
US7268032B2 (en) 2004-03-26 2007-09-11 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US7045857B2 (en) * 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
WO2006082618A1 (en) * 2005-01-31 2006-08-10 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
JP4794546B2 (en) * 2005-01-31 2011-10-19 新電元工業株式会社 Semiconductor device and manufacturing method thereof
JP2007266570A (en) * 2006-03-02 2007-10-11 Denso Corp Insulated gate bipolar transistor
JP2009016618A (en) * 2007-07-05 2009-01-22 Denso Corp Semiconductor device and manufacturing method thereof
US7871888B2 (en) 2007-10-24 2011-01-18 Fuji Electric Systems Co., Ltd. Method of manufacturing semiconductor device
JP2013051434A (en) * 2012-11-05 2013-03-14 Toshiba Corp Semiconductor device
JP2018046139A (en) * 2016-09-14 2018-03-22 三菱電機株式会社 Semiconductor device, and method of manufacturing the same

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