JP3507732B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3507732B2
JP3507732B2 JP27825599A JP27825599A JP3507732B2 JP 3507732 B2 JP3507732 B2 JP 3507732B2 JP 27825599 A JP27825599 A JP 27825599A JP 27825599 A JP27825599 A JP 27825599A JP 3507732 B2 JP3507732 B2 JP 3507732B2
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semiconductor
layer
region
semiconductor region
type
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JP2001102577A (en
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和敏 中村
彰博 八幡
孝 四戸
雄介 川口
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株式会社東芝
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a super junction element for electric power. FIG. 7 is a sectional view showing the element structure of a conventional vertical super junction MOSFET. The basic structure of this device is as follows: an n + -type drain layer 1 formed on an n + -type semiconductor substrate; an n -type base layer (not shown) epitaxially grown thereon; + Source layer 4, p + layer 5, drain electrode 6, source electrode 7, gate electrode 8, gate insulating film 9, n
- n-type by type base layer low-concentration layer 10 and the p-type low concentration layer 1
1 are constituted by auxiliary areas arranged alternately and repeatedly. FIG. 1 shows only a unit region composed of regions corresponding to the left half of the n-type low concentration layer 10 and the right half of the p-type low concentration layer 11, but actually, the unit regions adjacent to each other are arranged. A plurality of ladders are arranged so as to be plane symmetric at a boundary surface between the unit areas. The effect of the auxiliary region in which the n-type low-concentration layers 10 and the p-type low-concentration layers 11 are alternately and repeatedly arranged is described below.
For example, see "T. Fujihira, Jpn. J. App.
l. Phys. Vol. 36 (1997) pp. 625
4-6262 ". According to this, if the carrier integration amount in the repetition direction of the n-type low-concentration layer 10 and the p-type low-concentration layer 11 in the auxiliary region is designed to be substantially the same at about 5 × 10 12 cm −2 or less, When a reverse voltage is applied between these low-concentration layers, these low-concentration layers are completely depleted. According to this principle, for example, the n-type low concentration layer 1
Even if the concentration of 0 is set to 100 times the concentration of the n -type base layer, the width of the n-type low-concentration layer 10 is narrowed and the carrier integration amount is adjusted to be 5 × 10 12 cm −2 or less. Thus, no breakdown occurs in the auxiliary area. Therefore, if such an auxiliary region is formed in a region sandwiched between the n + -type drain layer 1 and the p-type base layer 3, the resistance at this portion can be significantly reduced. Since the auxiliary region has a property that the breakdown voltage increases in proportion to the length in the thickness direction, the on-resistance is linearly proportional to the breakdown voltage. On the other hand, when there is no auxiliary region, the breakdown voltage does not increase unless the thickness is increased while decreasing the concentration of the n -type base layer, so that the on-resistance increases significantly in proportion to the square of the breakdown voltage. Therefore, the effect of reducing the on-resistance due to the provision of the auxiliary region increases as the element requires a higher breakdown voltage. The p-type low-concentration layer 11 in the auxiliary region is connected to the p-type base layer 3 and is set at substantially the same potential as the source electrode 7, and the n-type low-concentration layer 10 in the auxiliary region is n + -type. It is connected to the drain layer 1 and set at substantially the same potential as the drain electrode 6. Therefore, when the vertical MOSFET starts to turn off, the carriers in the auxiliary region are quickly discharged to the outside of the element, the depletion layer spreads, and it is possible to turn off at high speed. Further, a method for manufacturing such an element is as follows.
"G. Deboy et al., IEDM 98 (19
98) pp. 683-685 ". According to this, an epitaxial layer having a thickness of, for example, 10 μm is formed on the n + -type semiconductor substrate, and the region where the n-type low-concentration layer 10 and the p-type low-concentration layer 11 are formed as auxiliary regions is formed. Impurities are selectively introduced by ion implantation. Further, an epitaxial layer is formed and the same steps are performed, and this is repeated several times depending on the breakdown voltage and thickness of the device. Next, after ion implantation of the p-type base layer 3 and the like, impurities are diffused from the ion-implanted layers formed inside the respective epitaxial layers by thermal diffusion, and the n-type low Concentration layer 10 and p-type low concentration layer 11
To be connected. Then, the n + type source layer 4,
The p + type layer 5, the gate insulating film 9, the gate electrode 8, the source electrode 7, the drain electrode 6, and the like are formed to complete the device. By using the above-described manufacturing method, the auxiliary region can be formed relatively easily. However, in the above-described conventional device structure, “PM Shenoy et al., ISPSD
99 (1999) pp. 99-102, when the carrier integration amount of the n-type low concentration layer 10 and the p-type low concentration layer 11 in the auxiliary region is shifted, the turn-off time and the reverse recovery time of the built-in reverse conducting diode greatly vary. At the same time, there arises a problem that the withstand voltage is significantly reduced. In addition, since the epitaxial growth is performed at a high temperature, the impurity introduced into the epitaxially grown layer which has been initially formed gradually diffuses, so that there is a problem that the carrier integration amount under the auxiliary region is easily shifted. In the conventional element structure, the p of the auxiliary region
Since the low-concentration type layer 11 is in contact with the n + -type drain layer 1, the depletion layer in this portion spreads only inside the low-concentration p-type layer 11. On the other hand, since the n-type low-concentration layer 10 in the auxiliary region is in contact with the p-type base layer 3 having a relatively low concentration, the depletion layer in this portion is not only in the n-type low-concentration layer 10 but also in the p-type base layer 3. Spread inside. As a result, the electric field strength at the portion where the p-type low-concentration layer 11 and the n + -type drain layer 1 are in contact with each other is increased, and there is a problem that the breakdown voltage of the entire device is limited at this portion. According to the result of the two-dimensional numerical calculation, the length L of the auxiliary region is 350 μm, and the widths Wn and Wp of the n-type low concentration layer 10 and the p-type low concentration layer 11 in the auxiliary region are both 3.5 μm.
Concentration Cn of m, n-type low concentration layer 10 and p-type low concentration layer 11
When both Cp and Cp were 3 × 10 15 cm −3 , the breakdown voltage of the device was 4950V. Since the withstand voltage of an ideal device without local electric field concentration should be 7000 V, which is expressed by the product of the breakdown electric field strength of the semiconductor and the length of the auxiliary region, this device structure can provide only a withstand voltage of 70%. Will not be. As described above, the super junction element has excellent performance such as reduction of on-resistance and high-speed turn-off. However, in the conventional super junction element, when the carrier integration amount of the n-type low concentration layer and the p-type low concentration layer in the auxiliary region deviates, the turn-off time and the reverse recovery time of the built-in reverse conducting diode greatly vary, and the breakdown voltage also increases. There has been a problem that it is significantly reduced. Further, there is also a problem that the electric field strength is increased in a portion where the p-type low-concentration layer and the n + -type drain layer are in contact, and the withstand voltage of the entire device is limited in this portion. The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide a semiconductor device capable of improving the breakdown voltage and the turn-off characteristics as compared with the conventional elements. A semiconductor device according to the present invention has the following configuration. In order to facilitate understanding of the present invention, the configuration of the present invention is indicated by reference numerals of the drawings described in the embodiments described later. According to the present invention, a first semiconductor region (1) containing a first conductivity type impurity and a second conductivity type impurity formed separately from the first semiconductor region (1) are contained. A second semiconductor region (3), and a first semiconductor region provided between the first semiconductor region (1) and the second semiconductor region (3) and containing a first conductivity type impurity. Direction in which the first semiconductor region (1) and the second semiconductor region (3) face each other with the semiconductor layer (10) and the second semiconductor layer (11) containing impurities of the second conductivity type. Third semiconductor regions (10, 1
1), wherein the first semiconductor layer (10) and the second semiconductor layer (11), which are alternately and repeatedly arranged, have a carrier integration amount in the repetition direction of the second semiconductor layer (10).
The semiconductor layer (11) is configured to be larger than the first semiconductor layer (10), and at least the first semiconductor region (1) and the third semiconductor region (10, 11) A fourth semiconductor region (13) having a first conductivity type lower in impurity concentration than the first semiconductor region (1) is formed between the second semiconductor layer (11) and the second semiconductor layer (11). In the present invention, the carrier integration amount (Q2) of the third semiconductor region (auxiliary region) in the repetition direction of the second semiconductor layer is larger than the carrier integration amount (Q1) of the first semiconductor layer in the repetition direction. (Q2>
Because of Q1), a non-depleted region remains in the center of the second semiconductor layer even after the first semiconductor layer is depleted during turn-off. Therefore, a current is discharged through the non-depleted region, and it is possible to turn off at a high speed (in particular, since the mobility of the p-type carrier is smaller than that of the n-type, the first The effect is great when the semiconductor layer is n-type and the second semiconductor layer is p-type. Even if there is some variation in the amount of carrier integration due to the manufacturing process or the like, if the values of Q2 and Q1 are set so that the magnitude relationship between Q2 and Q1 does not reverse, elements with uniform turn-off times can be easily manufactured. Can be manufactured. Further, since the non-depleted region remains at the center of the second semiconductor layer, the potential of the second semiconductor region reaches the vicinity of the first semiconductor region via the non-depleted region. However, since the fourth semiconductor region having an impurity concentration lower than that of the first semiconductor region is formed between the first semiconductor region and the third semiconductor region, the depletion layer has a fourth impurity region having a lower impurity concentration. It is possible to reduce the electric field by expanding into the inside of the semiconductor region, thereby achieving a high breakdown voltage. In the above invention, the second semiconductor layer (11) of the third semiconductor region (10, 11) is formed by the first semiconductor layer (10, 11).
The semiconductor region (1) side preferably includes a plurality of semiconductor layers configured to have a lower impurity concentration than the second semiconductor region (3) side. With such a configuration, the region of the second semiconductor layer of the third semiconductor region (auxiliary region) on the side closer to the first semiconductor region is easily depleted, so that the potential of the second semiconductor region is reduced. Can be further suppressed, and a higher breakdown voltage can be further enhanced. Further, in the region near the second semiconductor region, the second semiconductor layer has a relatively low resistance, so that the discharge current is limited and the turn-off speed is not impaired. In the above invention, the fourth semiconductor region (13) may be a buffer region formed between the first semiconductor region (1) and the third semiconductor region (10, 11). It may be. With such a configuration, even if the reverse recovery current of the built-in reverse conducting diode becomes large due to the relatively high concentration of the second semiconductor layer in the third semiconductor region (auxiliary region), the buffer region is formed in the buffer region. By accumulating carriers, a soft recovery characteristic is obtained, and voltage oscillation can be effectively prevented. Embodiments of the present invention will be described below with reference to the drawings. In the following embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is p-type. It is also possible to use an n-type. (First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET. The basic element structure and the basic manufacturing method are almost the same as those of the conventional vertical super junction MOSFET already described with reference to FIG. 7, and correspond to the components shown in FIG. The same reference numerals are given to the constituent elements, and a detailed description thereof will be omitted here (the same applies to the second to fifth embodiments shown in FIGS. 2 to 5). In the vertical type super junction MOSFET of the present embodiment, the p of the auxiliary region (third semiconductor region)
Integration amount Q of the low-concentration type layer (second semiconductor layer) 11
p is set to be larger than the carrier integral Qn of the n-type low concentration layer (first semiconductor layer) 10 (Qp> Qn). In addition, these carrier integration amounts are set so that both Qp and Qn are 5 × 10 12 cm −2 or less. Further, between the p-type low concentration layer 11 and the n + -type drain layer (first semiconductor region) 1, an n -type layer (the fourth
Semiconductor region 13) is formed. According to the present embodiment, even when the turn-off starts and the n-type low-concentration layer 10 is completely depleted, it is located near the center of the p-type low-concentration layer 11 (corresponding to the region near the left end in the figure). The non-depleted region remains, and the current due to the p-type carriers (holes) having a lower mobility than the n-type is discharged through the non-depleted region, so that a high-speed turn-off can be realized. The turn-off time is suddenly delayed when Qn> Qp because the magnitude relationship between Qp and Qn is reversed, but if the margin is set in advance so that Qp> Qn, some process may be required. Even if there is a change, the relationship of Qp> Qn is maintained, so that the turn-off time does not greatly vary. For example, the difference between Qp and Qn may vary by about 5% due to process variation.
Is set to be about 7 to 8% larger than Qn, it is possible to reliably maintain the relationship of Qp> Qn even if there is a process variation. Since the non-depleted region remains near the center of the p-type low-concentration layer 11, the potential of the lower region at the center of the p-type low-concentration layer 11 is increased via the non-depleted region. There is a problem that the potential becomes the same as the potential of the layer 3 and the electric field intensity increases near the boundary with the n + -type drain layer 1.
In the present embodiment, the depletion layer can be expanded by the n -type layer 13, so that the electric field is alleviated and a high breakdown voltage can be maintained, and such a problem can be prevented. The n-type low concentration layer 10 and the p-type low concentration layer 1
1, a p-type low-concentration layer 11 having a half carrier integration amount is disposed at the end of the auxiliary region, and a guard ring or RESUR for a normal n -type base layer is provided.
It is desirable to apply a junction termination structure such as F. (Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET. In the present embodiment, in addition to the element structure of the first embodiment, a p type layer 14 is formed in a lower region of the p type low concentration layer 11 in the auxiliary region. According to the present embodiment, the p -type layer 14 is depleted earlier than the p-type low-concentration layer 11 having a higher impurity concentration, so that a region having the same potential as the p-type base layer 3 does not enter. . As a result, the electric field is alleviated and a higher breakdown voltage can be maintained. Although the p-type low-concentration layer has two concentration regions in the example shown in the figure, three or more concentration regions may be provided so that the impurity concentration becomes lower toward the lower layer. Good. Further, in the example shown in FIG.
Although 0 is formed so as to have a uniform concentration, the concentration may become lower toward the lower layer side in accordance with the change in the concentration of the p-type low concentration layer 11. According to such a configuration, when the device is formed by epitaxial growth several times, the lower part of the auxiliary region, which is exposed to a high temperature for a long time and has a large variation in Q due to thermal diffusion, is exposed to a low concentration and exposed to a high temperature. Since the upper portion of the auxiliary region having a small variation in Q is formed with high concentration for a short period of time, it is possible to increase the breakdown voltage while keeping the on-resistance low. (Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET. In this embodiment, an n-type buffer layer 15 having a lower concentration than the n + -type drain layer is formed between the n + -type drain layer 1 and the auxiliary region. According to this embodiment, a built-in reverse conducting diode having the p-type base layer 3 and the p-type low concentration layer 11 as an anode layer and the n + -type drain layer 1 and the n-type low concentration layer 10 as a cathode layer. The reverse recovery characteristic can be a soft recovery. Further, since the depletion layer extends not only in the p-type low-concentration layer 11 but also in the n-type buffer layer 15, the electric field is reduced, and the withstand voltage of the element can be improved. The super junction MO according to the present invention
In the SFET, since Qp> Qn, the reverse recovery current increases, and when the voltage of the diode recovers, a voltage jump proportional to the current decrease rate occurs, which tends to cause a problem of causing voltage oscillation. Even in such a case, the formation of the n-type buffer layer 15 accumulates carriers, has the effect of reducing the current decrease rate in the tail region during reverse recovery and reducing the voltage jump. From the viewpoint of carrier accumulation, it is desirable to set the thickness of the n-type buffer layer 15 to be equal to or longer than the carrier diffusion length. For example, the thickness of the n-type buffer layer 15 is set to about 75 μm in a device having a withstand voltage of 4500 V. (Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET. In the present embodiment, a p type layer 14 is further formed in addition to the element structure of the third embodiment. That is, the present embodiment has a structure in which the second embodiment and the third embodiment are combined.
The respective effects obtained in the third embodiment and the third embodiment can be obtained. (Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET. In the present embodiment, an n-type buffer layer 15 is further formed in addition to the element structure of the second embodiment, and according to the present embodiment, the n-type buffer layer 15 is used in the second and third embodiments. The same effect as the obtained effect can be obtained. (Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
Super junction MOSF according to the embodiment of the present invention
It is the perspective view which showed the element structure of ET. The basic principle is the same as that of the vertical type super junction MOSFET shown in FIG. 1 and the like, and the components corresponding to the components shown in FIG. 1 and the like are denoted by the same reference numerals. I have. In the vertical super junction MOSFET described in the first to fifth embodiments, the drain electrode 6
Is formed on one main surface of the semiconductor substrate, and the source electrode 7 is formed on the other main surface of the semiconductor substrate.
In ET, the drain electrode 6 and the source electrode 7 are formed on the same main surface side of the semiconductor substrate. Such a horizontal super junction M
Also in OSFET, vertical super junction M
Like the OSFET, the p-type low concentration layer 11 in the auxiliary region
Is set so that Qp> Qn, and n is located between the p-type low-concentration layer 11 and the n + -type drain layer 1. - by providing the mold layer 13, it is possible to obtain the same effect as the vertical superjunction MOSFET. Although the horizontal super junction MOSFET shown in FIG. 6 has a structure corresponding to the vertical super junction MOSFET of the first embodiment shown in FIG. 1, the vertical super junction MOSFET described in the other embodiments is used. It is also possible to apply the structure corresponding to the type super junction MOSFET to the lateral type super junction MOSFET. Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment. For example, in the above embodiment, the basic element structure is MOSF
Although ET has been described, it can be applied to other element structures such as SIT. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof. According to the present invention, the relationship between the carrier integral Q1 of one semiconductor layer in the auxiliary region and the carrier integral Q2 of the other semiconductor layer is such that Q2> Q1. At the time of turn-off, a non-depleted region remains in the other semiconductor layer, and current is discharged through this non-depleted region, so that turn-off can be sped up.
Also, by providing a low impurity concentration region between the high impurity concentration region on the drain side and the auxiliary region, the depletion layer spreads to the low impurity concentration region and relaxes the electric field, so that a high breakdown voltage can be achieved. Become.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an element structure of a vertical super junction MOSFET according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing an element structure of a vertical super junction MOSFET according to a second embodiment of the present invention. FIG. 3 is a cross-sectional view showing an element structure of a vertical super junction MOSFET according to a third embodiment of the present invention. FIG. 4 is a sectional view showing an element structure of a vertical super junction MOSFET according to a fourth embodiment of the present invention. FIG. 5 is a sectional view showing an element structure of a vertical super junction MOSFET according to a fifth embodiment of the present invention. FIG. 6 is a perspective view showing an element structure of a lateral super junction MOSFET according to a sixth embodiment of the present invention. FIG. 7 shows a vertical super junction M according to the prior art.
FIG. 3 is a cross-sectional view illustrating an element structure of an OSFET. [Description of Signs] 1 ... n + type drain layer (first semiconductor region) 3 ... p type base layer (second semiconductor region) 4 ... n + type source layer 5 ... p + type layer 6 ... drain electrode 7 ... Source electrode 8 Gate electrode 9 Gate insulating film 10 n-type low concentration layer (first semiconductor layer) 11 p-type low concentration layer (second semiconductor layer) 13 n - type layer (fourth layer) Semiconductor region) 14 p - type layer 15 n-type buffer layer (fourth semiconductor region)

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazutoshi Nakamura 1 Toshiba-cho, Komukai, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba R & D Center (56) References JP-A-7-7154 (JP, A) JP-A-10-223896 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78 H01L 21/336

Claims (1)

  1. (57) Claims 1. A first semiconductor region containing a first conductivity type impurity and a second conductivity type impurity formed separately from the first semiconductor region. A first semiconductor layer provided between the first semiconductor region and the second semiconductor region, the first semiconductor layer containing a first conductivity type impurity and a second conductivity type; And a third semiconductor region in which the first semiconductor region and the second semiconductor region are alternately and repeatedly arranged in a direction intersecting a direction in which the first semiconductor region and the second semiconductor region face each other. A semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are alternately and repeatedly arranged.
    The second semiconductor layer is configured so that the carrier integration amount in the repetition direction of the semiconductor layer is larger than the first semiconductor layer, and between the first semiconductor region and the second semiconductor layer. A fourth semiconductor region having a first conductivity type impurity concentration lower than that of the first semiconductor region is selectively formed in the first semiconductor region;
    A semiconductor device , wherein a conductor region is in contact with the first semiconductor layer . 2. A first half containing an impurity of a first conductivity type.
    A conductive region and a second conductive type formed separately from the first semiconductor region;
    A second semiconductor region containing an impurity, between the first semiconductor region and the second semiconductor region;
    A first semiconductor including an impurity of a first conductivity type
    Body layer and second semiconductor layer containing second conductivity type impurity
    Means that the first semiconductor region and the second semiconductor region face each other
    No. is arranged alternately and repeatedly in the direction that intersects
    3. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are alternately and repeatedly arranged.
    Of the semiconductor layer in the repetition direction is the second
    So that the semiconductor layer is larger than the first semiconductor layer
    It consists less of said first semiconductor region and the third semiconductor region
    Between the first semiconductor region and the second semiconductor layer
    Also, the fourth semiconductor region of the first conductivity type having a low impurity concentration is formed.
    A second semiconductor layer of the third semiconductor region, the semiconductor layer having a lower impurity concentration on the first semiconductor region side than on the second semiconductor region side. A semiconductor device comprising:
JP27825599A 1999-09-30 1999-09-30 Semiconductor device Expired - Lifetime JP3507732B2 (en)

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