CN116722033A - Super junction schottky diode with improved P column and preparation method - Google Patents
Super junction schottky diode with improved P column and preparation method Download PDFInfo
- Publication number
- CN116722033A CN116722033A CN202311008130.5A CN202311008130A CN116722033A CN 116722033 A CN116722033 A CN 116722033A CN 202311008130 A CN202311008130 A CN 202311008130A CN 116722033 A CN116722033 A CN 116722033A
- Authority
- CN
- China
- Prior art keywords
- layer
- schottky diode
- type bottom
- bottom auxiliary
- super junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims description 51
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 193
- 238000000034 method Methods 0.000 description 51
- 230000008569 process Effects 0.000 description 35
- 150000002500 ions Chemical class 0.000 description 26
- 239000004065 semiconductor Substances 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 18
- 230000001965 increasing effect Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 8
- 230000002441 reversible effect Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000010884 ion-beam technique Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000000927 vapour-phase epitaxy Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011343 solid material Substances 0.000 description 4
- 238000000348 solid-phase epitaxy Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000003877 atomic layer epitaxy Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a super junction Schottky diode with an improved P column and a preparation method thereof, wherein the super junction Schottky diode comprises the following components: a P-type doped layer; the P-type doping layer is positioned between the P column and the N-drift layer; and the included angle between the contact surface of the P-type doped layer and the N-drift layer and the central axis of the super junction Schottky diode is 5-15 degrees. According to the invention, the uneven edge of the P column in the traditional super junction Schottky diode is doped with a layer of P type material, so that the edge of the P column is smooth, and the existence of the P type doped layer can optimize charge balance and simultaneously has high voltage resistance and lower on-resistance, so that the performance of the super junction Schottky diode is greatly enhanced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super junction Schottky diode with an improved P column and a preparation method thereof.
Background
Silicon carbide is a typical representation of third generation wide bandgap semiconductor materials, and has the characteristics of wide bandgap, high critical breakdown field strength, high thermal conductivity, high carrier saturation rate and the like. The silicon carbide power semiconductor device has wide application prospect in the application fields of high-voltage withstand level in new energy power generation, high-speed rail traction equipment, hybrid electric vehicles and the like. In the super junction schottky diode, since the P-type region is arranged in the n-type epitaxial layer, when the reverse voltage is applied to the drift region, an electric field is generated in the horizontal direction, and if the n-type epitaxial layer and the P-type region reach a charge balance state, the charges in the drift region are completely consumed, and the electric field is uniformly distributed in the drift region, so that the breakdown voltage of the device can be greatly improved. In addition, the breakdown voltage of the device in the super junction structure is irrelevant to the doping concentration of the n-type epitaxial layer and the P-type region, so that the on-resistance of the device can be further reduced by increasing the doping concentration of the n-type epitaxial layer and the P-type region. Generally, in the silicon carbide superjunction schottky diode, a compromise relationship exists between high reverse breakdown voltage and low forward on-resistance, and the choice of the superjunction structure can significantly improve the compromise between the two. In addition, for the super junction structure, the doping concentration and the width of the n-type epitaxial layer and the P-type region are strictly controlled so as to ensure that charge balance is realized. The essence of the super junction is to utilize an electric field generated by a P region inserted in a drift region to carry out charge compensation on an N region, so as to achieve the purposes of improving breakdown voltage and reducing on-resistance. The super junction is formed by using N columns and P columns which are alternately arranged in the composite buffer layer to carry out charge compensation, so that the P region and the N region are mutually depleted, and ideal flat-top electric field distribution and uniform electric potential distribution are formed, thereby achieving the purposes of improving breakdown voltage and reducing on-resistance. The ideal effect is achieved if the charge balance is the precondition. Thus, superjunction technology began with the advent of the fabrication process around how to fabricate the charge balanced P and N regions.
The currently used super junction structure manufacturing technology mainly comprises the following steps: multiple epitaxy and implantation techniques, deep trench etching and trench filling techniques. However, due to process level limitations, the superjunction P-pillars may diffuse during the epitaxial process anneal, resulting in P-pillar edge irregularities. The irregularity of the P-pillar results in a charge balance effect that cannot be optimized, and in the practical process, the charge balance problem is extremely important, and the superjunction structure is a device working by using the charge compensation principle, and if the charge of the device is unbalanced, the breakdown characteristic of the device can be obviously affected. The excessive high requirement of charge balance on the process results in that the charge balance between the P-type injection region and the epitaxial layer of the super-junction Schottky diode obtained by the existing manufacturing process is difficult to realize, and the compromise relationship between the breakdown voltage and the on-resistance of the silicon carbide super-junction Schottky diode cannot be improved.
Disclosure of Invention
The invention aims to provide a super junction Schottky diode with an improved P column and a preparation method thereof. .
A superjunction schottky diode with an improved P-pillar, comprising: a P-type doped layer;
the P-type doping layer is positioned between the P column and the N-drift layer;
and the included angle between the contact surface of the P-type doped layer and the N-drift layer and the central axis of the super junction Schottky diode is 5-15 degrees.
Preferably, the method further comprises: an N-type bottom auxiliary layer;
the N-type bottom auxiliary layer is positioned between the P column and the N+ substrate;
the N-drift layer forms a conductive channel with the N-type bottom auxiliary layer and the N+ substrate.
Preferably, the width of the N-type bottom auxiliary layer is the minimum width of the P-pillar;
the width of the N-type bottom auxiliary layer is the sum of the width of the P column and the width of the N-drift layer at most.
Preferably, the doping concentration of the N-type bottom auxiliary layer is smaller than that of the N+ substrate.
Preferably, the doping concentration of the N-type bottom auxiliary layer is greater than that of the N-drift layer.
Preferably, the doping concentration of the N-type bottom auxiliary layer is 10 16 ~10 19 cm -3 。
Preferably, the method further comprises: an anode and a cathode;
the cathode is positioned below the N+ substrate;
the anode is located over the N-drift layer and the P-pillars.
Preferably, the N-type bottom auxiliary layer comprises a plurality of layers of regions with different doping concentrations;
and in the areas with different doping concentrations, the doping concentration of the area positioned on the upper layer of the N-type bottom auxiliary layer is smaller than that of the area positioned on the lower layer of the N-type bottom auxiliary layer.
A method of fabricating a superjunction schottky diode with an improved P-pillar, comprising:
epitaxial N-drift layer and P column above N+ substrate;
doping a P-type doped layer on the side wall of the P column;
and depositing a metal electrode.
Preferably, the method further comprises: and doping the N-drift layer for multiple times to form a plurality of N-type bottom auxiliary layers with different concentrations.
When the traditional super junction Schottky diode is manufactured, the edge of the P column formed finally is not smooth due to the imperfect annealing process, the charge balance of the super junction Schottky diode is affected by the edge of the P column which is not smooth, and therefore the electrical performance of the super junction Schottky diode is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a super junction Schottky diode of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing a super junction Schottky diode in accordance with the present invention;
FIG. 3 is a schematic diagram of the process flow structure of the super junction Schottky diode of the present invention;
fig. 4 is a schematic diagram of a super junction schottky diode with an N-type bottom auxiliary layer according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The currently used super junction structure manufacturing technology mainly comprises the following steps: multiple epitaxy and implantation techniques, deep trench etching and trench filling techniques. However, due to process level limitations, the superjunction P-pillars may diffuse during the epitaxial process anneal, resulting in P-pillar edge irregularities. The irregularity of the P-pillar results in a charge balance effect that cannot be optimized, and in the practical process, the charge balance problem is extremely important, and the superjunction structure is a device working by using the charge compensation principle, and if the charge of the device is unbalanced, the breakdown characteristic of the device can be obviously affected. The excessive high requirement of charge balance on the process results in that the charge balance between the p-type injection region and the epitaxial layer of the super-junction Schottky diode obtained by the existing manufacturing process is difficult to realize, and the compromise relationship between the breakdown voltage and the on-resistance of the silicon carbide super-junction Schottky diode cannot be improved.
When the traditional super junction Schottky diode is manufactured, the edge of the P column formed finally is not smooth due to the imperfect annealing process, the charge balance of the super junction Schottky diode is affected by the edge of the P column which is not smooth, and therefore the electrical performance of the super junction Schottky diode is reduced.
Example 1
A superjunction schottky diode with improved P-pillars, referring to fig. 1, comprising: a P-type doped layer;
the P-type doped layer is positioned between the P column and the N-drift layer;
the substrate of the PN junction is divided into P type and N type, and +is heavily doped (high doping concentration), is lightly doped (low doping concentration), and P type doped with IIIA group elements, such as: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc).
The included angle between the contact surface of the P-doped layer and the N-drift layer and the central axis of the super junction Schottky diode is 5-15 degrees.
Compared with the traditional resistive voltage-resistant layer, the super-junction voltage-resistant layer has the advantages that PN junctions are introduced into the super-junction voltage-resistant layer, N-region ionization positive charges emit P-region ionization negative charges of which most of electric field lines flow to the side under the off-state condition, obvious two-dimensional field effects are introduced into the voltage-resistant layer, and the peak value of the electric field on the surface of the device is greatly reduced by complex field modulation, and the in-vivo field distribution is optimized. The electric field distribution generated by ionized charges under the boundary condition of the junction voltage-resistant layer electric field line and zero potential is that the ionized charges in most areas in the longitudinal direction inside the super junction Schottky diode generate longitudinal field zero because the electric field lines in the voltage-resistant layer flow away transversely, and only local electric field distribution is generated at the PN junction position of the surface, and the high electric field rapidly decays in an exponential function within a short longitudinal distance range.
The transverse charge field modulates the longitudinal charge field to enable the internal electric field of the junction voltage-resistant layer to be distributed in a periodic function under the condition of super junction closing state, the end face of the junction voltage-resistant layer of the device also presents periodic peak distribution, and the peak and the trough of the junction voltage-resistant layer are located on the center position of each P column or N column unlike the internal device. The longitudinal high electric field is limited within a certain distance, so that the longitudinal field distribution inside the voltage-resistant layer is hardly affected. And as the length increases, the high field region remains the same distribution and relative position to the surface is unchanged. For the super junction structure, the doping concentration and the width of the N-type epitaxial layer and the P-type region need to be strictly controlled so as to ensure that charge balance is realized.
In the embodiment of the invention, the combination of the P-pillar and the P-type doped layer is set to be trapezoid or the combination of trapezoid and rectangle (the upper part is trapezoid and the lower part is rectangle), the included angle between the oblique side of the trapezoid and the central axis of the superjunction diode is 5-15 degrees, if the included angle between the oblique side of the trapezoid and the central axis of the superjunction diode exceeds 15 degrees, the charge balance effect cannot be maximized, the path of current passing through the drift region is overlong, the resistance of the drift region is increased, and the on-resistance is greatly improved. In the embodiment of the invention, the included angle between the inclined side of the trapezoid and the central axis of the superjunction diode is set to be 10 degrees. According to the invention, the uneven edge of the P column in the traditional super junction Schottky diode is doped with a layer of P type material, so that the edge of the P column is smooth, and the existence of the P type doped layer can optimize charge balance and simultaneously has high voltage resistance and lower on-resistance, so that the performance of the super junction Schottky diode is greatly enhanced.
Preferably, referring to fig. 4, further comprising: an N-type bottom auxiliary layer;
the N-type bottom auxiliary layer is positioned between the P column and the N+ substrate;
the N-drift layer forms a conductive channel with the N-type bottom auxiliary layer and the N+ substrate.
The basic structure of the super junction Schottky diode is to change the drift region of the common Schottky barrier diode into alternative PN columns, and the concentration of the PN columns is higher and can be higher than the doping concentration of the drift region of the common Schottky diode by more than one order of magnitude. Wherein the N pilar forms a schottky contact with the anode and the P pillars form an ohmic contact with the anode. Ohmic contact: no potential barrier exists between the metal and the semiconductor, carriers can smoothly flow into the semiconductor from the metal or flow into the semiconductor from the semiconductor, the corresponding current-voltage curve is a straight line, ohm law is met, the corresponding slope is the conductance of the semiconductor, and the contact resistance of the metal and the semiconductor is negligible.
Schottky contact: there is a barrier-schottky barrier between a metal and a semiconductor, and it is classified into two cases of a barrier to electrons and a barrier to holes. When a schottky barrier is present, the current-voltage curve is no longer a straight line, but a curve. When the voltage is relatively low, the current increases slowly with the voltage; when the voltage exceeds a certain value, the current becomes significantly large. The resistance of the whole system comprises three parts: the resistance of the semiconductor, the contact resistance of the two metal-semiconductor contacts. The contact resistance of the metal-semiconductor is a variable value that is related to the potential difference that falls across the barrier. The metal-semiconductor-metal structure corresponds to the resistance of two reverse contact schottky diodes plus one semiconductor.
Under forward bias, N pilar participates in conduction, and P pillar does not participate in conduction, and although the conduction channel area is reduced compared with that of a common Schottky diode, the concentration of N pilar is far higher than that of the common Schottky diode driftThe on-resistance of the mobile region is obviously reduced due to the concentration of the mobile region. Under reverse bias, an effect similar to that of the intrinsic semiconductor drift region is achieved due to the charge compensation effect of the PN column. When smaller reverse bias voltage is applied, the alternate PN columns can be rapidly depleted in the transverse direction, so that a transverse PN junction is formed, the drift region is depleted in the longitudinal direction and also rapidly depleted in the transverse direction, the whole drift region is similar to an intrinsic layer, and the breakdown voltage of the device is improved. The biggest advantage of the super junction structure is that the breakdown characteristic of the device is improved under the condition of reducing the on-resistance of the device, which solves the problem of Ron and V of the common structure B A compromise relation problem which is difficult to solve. For a common diode power device, the on-resistance must be reduced to reduce the power consumption, and the concentration of the drift region needs to be increased and the thickness of the drift region needs to be reduced to reduce the on-resistance, however, as the concentration of the drift region increases and the thickness of the drift region decreases, the breakdown voltage of the device decreases and the reverse leakage current increases, which must be selected in a compromise. The super junction structure can well solve the problem, and the technical effects of reducing on-resistance and improving breakdown voltage are achieved through charge compensation of the PN column.
Because N pilar conducts electricity and P pillar does not conduct electricity when the super junction Schottky diode is connected with forward voltage, in order to increase the conducting area of the super junction Schottky diode, an N-type bottom auxiliary layer is added below the P pillar to increase the conducting area, the conducting current is increased under the condition that the withstand voltage performance of the super junction Schottky diode is unchanged, the conducting resistance is reduced, and the ratio of the withstand voltage and the conducting resistance of the super junction Schottky diode can be improved.
Preferably, the width of the N-type bottom auxiliary layer is the minimum width of the P column;
the width of the N-type bottom auxiliary layer is the sum of the width of the P column and the width of the N-drift layer at most.
The width of the N-type bottom auxiliary layer can be changed according to the concentration of the N-drift layer or the P column, and the optimal structure of the width of the N-type bottom auxiliary layer is equal to the width of the P column, alternatively, the width of the N-type bottom auxiliary layer can be freely changed within a range that is larger than the width of the P column and smaller than the sum of the width of the P column and the width of the N-drift, which is equivalent to that the N-type bottom auxiliary layer extends to the N-drift layer, and the current density of the conducting current can be increased, so that the on-resistance is reduced.
It is apparent that increasing the doping concentration of the N-drift layer reduces the on-resistance and reduces the breakdown voltage performance of the superjunction schottky diode, because the P-pillar depletes the wider N-type bottom auxiliary layer more difficult than the least depleted N-type bottom auxiliary layer when the superjunction schottky diode is reverse biased, the reverse breakdown voltage performance of the superjunction schottky diode is reduced, and the final breakdown voltage to on-resistance ratio is smaller than when the N-type bottom auxiliary layer is equal in width to the P-pillar, but the breakdown voltage to on-resistance ratio is still greater than that of the conventional superjunction schottky diode.
If the width of the N-type bottom auxiliary layer is set to be the maximum, in the actual process production, the specific steps are as follows: an N-type bottom auxiliary layer is epitaxially formed over the N+ substrate, and then an N-drift layer and a P column are epitaxially formed over the N-type bottom auxiliary layer. When the width of the N-type bottom auxiliary layer is set to be minimum, in actual process production, a thinner N-drift layer is formed above an N+ substrate in an epitaxial mode, doping is conducted on the formed N-drift layer, so that an N-type bottom auxiliary layer is formed, then an N-drift layer with the same doping concentration is formed above the originally formed N-drift layer in an epitaxial mode, and a P column is formed above the N-type bottom auxiliary layer in an epitaxial mode.
The thickness of the N-type bottom auxiliary layer can be adjusted according to the doping concentration of the P column, if the doping concentration of the P column is larger, the thickness of the N-type bottom auxiliary layer is correspondingly increased, and if the doping concentration of the P column is smaller, the thickness of the N-type bottom auxiliary layer is correspondingly reduced. Because the concentration of the P-pillar is large, the N-type bottom auxiliary layer is easier to deplete, so that the thickness of the N-type bottom auxiliary layer is set to be a little larger, or the doping concentration of the N-type bottom auxiliary layer is increased, if the thickness of the N-type bottom auxiliary layer is too small, the P-pillar is depleted in advance, a conductive channel formed by the N-drift layer, the N-type bottom auxiliary layer and the n+ substrate cannot be formed, and if the thickness of the N-type bottom auxiliary layer is too large, the on-resistance becomes large and the voltage-withstand capability of the super junction schottky diode is also reduced.
Preferably, the doping concentration of the N-type bottom auxiliary layer is less than that of the n+ substrate.
Preferably, the doping concentration of the N-type bottom auxiliary layer is greater than that of the N-drift layer.
The doping concentration of the N-type bottom auxiliary layer can be adjusted in a concentration range smaller than the n+ substrate and larger than the N-drift layer, because the conductive path formed by the N-drift layer, the N-type bottom auxiliary layer and the n+ substrate can be formed only when the doping concentration of the N-type bottom auxiliary layer is smaller than the n+ substrate and larger than the N-drift layer.
The specific adjustment mode is determined by the doping concentration of the P column, the technical effect generated by the technical means of changing the doping concentration of the N-type bottom auxiliary layer is similar to the technical effect generated by changing the thickness and the width of the N-type bottom auxiliary layer, increasing or decreasing the doping concentration of the N-type bottom auxiliary layer is equivalent to increasing or decreasing the width and the thickness of the doping concentration of the N-type bottom auxiliary layer, if the doping concentration of the N-type bottom auxiliary layer is too high, the on-resistance becomes larger when the P column cannot deplete the N-type bottom auxiliary layer, the voltage withstand capability of the superjunction schottky diode is also reduced, if the doping concentration of the N-type bottom auxiliary layer is too small, the N-type bottom auxiliary layer is caused to be depleted by the P column in advance, and a conductive channel consisting of the N-drift layer, the N-type bottom auxiliary layer and the n+ substrate cannot be formed, so that the current density of the on-current of the superjunction schottky diode cannot be increased.
Preferably, the doping concentration of the N-type bottom auxiliary layer is 10 16 ~10 19 cm -3 。
Due to the higher doping concentration in the actual process productionThe P-pillars are difficult to manufacture and have high production cost, so in the embodiment of the invention, the doping concentration of the P-pillars is set to be lightly doped in order to save the production cost, correspondingly, the doping concentration of the N-type bottom auxiliary layer is also relatively low, and in order to form a conductive channel consisting of the N-drift layer, the N-type bottom auxiliary layer and the n+ substrate, the doping concentration of the N-type bottom auxiliary layer must be set to be greater than the doping concentration of the N-drift layer and less than the doping concentration of the n+ substrate. As a preferred embodiment, the doping concentration of the N-type bottom auxiliary layer is 10 16 cm -3 The doping concentration of the N-drift layer is 10 15 cm -3 The doping concentration of the N+ substrate is 10 18 cm -3 。
Preferably, the method further comprises: an anode and a cathode;
the cathode is positioned below the N+ substrate;
the anode is located over the N-drift layer and the P-pillars.
The anode metal is positioned above the N-drift layer and the P column, the cathode metal is positioned below the N+ substrate, when the super junction Schottky diode is connected with forward voltage, namely the anode is connected with high potential, and the cathode is connected with low potential, current flows from the anode metal to the N-drift layer, then flows from the N-drift layer to the N-type bottom auxiliary layer and the N+ substrate, and flows to the N+ substrate after flowing to the N-type bottom auxiliary layer, and finally flows from the N+ substrate to the cathode metal.
The anode metal is made of materials with good conductivity and corrosion resistance, such as molybdenum, aluminum, copper, silver, zinc, magnesium, nickel and the like, and copper is used as the anode metal in a preferred embodiment, because the copper has high stability, can bear extremely high current density, is convenient for process production, and is cheap to sell and can be recycled. The cathode metal also employs copper as the electrode material.
Preferably, the N-type bottom auxiliary layer comprises a plurality of layers of regions with different doping concentrations;
in the regions with different doping concentrations, the doping concentration of the region positioned on the upper layer of the N-type bottom auxiliary layer is smaller than that of the region positioned on the lower layer of the N-type bottom auxiliary layer.
The N-type bottom auxiliary layer can be provided with a plurality of layers of regions with different doping concentrations, the regions with different doping concentrations are sequentially stacked to form the N-type bottom auxiliary layer, the doping concentration of each layer is sequentially decreased from the substrate to the upper side, the concentration of each layer is sequentially increased to the substrate direction, and current can be ensured to smoothly pass through the N-type bottom auxiliary layer and flow to the N+ substrate.
As a preferred embodiment, the N-type bottom auxiliary layer is provided in two layers, the concentration of the upper layer is smaller than the doping concentration of the next time, specifically, the doping concentration of the upper layer of the N-type bottom auxiliary layer is set to 10 16 cm -3 The doping concentration of the upper layer of the N-type bottom auxiliary layer is set to be 10 17 cm -3 The current flows from the N-drift layer to the upper layer of the N-type bottom auxiliary layer, from the upper layer of the N-type bottom auxiliary layer to the lower layer of the N-type bottom auxiliary layer, and from the lower layer of the N-type bottom auxiliary layer to the N+ substrate. The N-type bottom auxiliary layer may be formed of three or more layers, but in industrial production, the more the number of N-type bottom auxiliary layers is, the higher the production cost is, and as the number of N-type bottom auxiliary layers is increased, the more difficult the control of the region and doping concentration of each layer of the N-type bottom auxiliary layer is, so the production cost is correspondingly increased. Therefore, in order to save the production cost, the invention only needs to arrange the N-type bottom auxiliary layer into one layer or two layers.
Example 2
A method of fabricating a superjunction schottky diode with an improved P-pillar, comprising:
s100, an N-drift layer and a P column are epitaxially arranged above an N+ substrate;
epitaxy is one of the semiconductor processes, which refers to a process of growing a fully aligned single crystal layer on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. The epitaxial growth modes can be classified into solid phase epitaxy, liquid phase epitaxy and vapor phase epitaxy according to the different phases of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During the implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, and amorphization occurs to form a surface amorphous silicon layer; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, doping a P-type doped layer on the side wall of the P column;
the invention adopts ion implantation to dope the P-type doped layer. Ion implantation is to emit an ion beam in vacuum to the solid material, and after the ion beam is emitted to the solid material, the ion beam is resisted by the solid material and slowly reduced in speed, and finally stays in the solid material to form an N-type bottom auxiliary layer. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). Ion implantation also causes chemical and physical changes when ions strike the target at high energies, and the crystal structure of the target may be destroyed or even destroyed by the high energy collision cascade.
Ion implantation equipment typically includes an ion source in which ions of a desired element are generated, and a target chamber in which the ions are electrostatically accelerated to high energy and implanted upon impact with a target as a material. Typical ion energies are in the range of 10 to 500 keV (1600-80000 aJ). Energy in the range of 1 to 10 keV (160-1600 aJ) can be used, but the permeability is only a few nanometers or less. Higher energies may also be used: typically with an accelerator of 5 MeV (800000 aJ). However, there is typically a significant structural damage to the target and, due to the wide depth profile, the net composition change at any point in the target will be small.
The energy of the ions, the type of ions and the composition of the target determine the depth of penetration of the ions in the solid: the unienergetic ion beam typically has a broad depth profile. The average penetration depth is referred to as the ion range. Typically, the ion range will be between 10 nanometers and 1 micrometer. Thus, ion implantation is the best way in cases where chemical or structural changes are desired near the surface of the target. The ions gradually lose energy as they pass through the solid, both due to accidental collisions with the target atoms (causing abrupt energy transfer) and due to slight drag from electron orbit overlap, the loss of ion energy in the target is called a stop and can be simulated using a binary collision approximation method. Accelerator systems for ion implantation are typically classified as medium current (ionBeamlet currents between 10uA and-2 mA), high currents (beam currents up to 30 mA), high energies (ion energies above 200 keV and above 10 MeV) and very high doses (effective implant doses greater than 10) 16 /cm 2 ）。
Various ion implantation beam line designs include a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for a p-type dopant and an electron may be created for an n-type dopant. The conductivity of the semiconductor near the doped region is changed, often to adjust the threshold of the diode.
S300, depositing a metal electrode.
Deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
Preferably, the method further comprises: and doping the N-drift layer for multiple times to form a plurality of N-type bottom auxiliary layers with different concentrations.
In the embodiment of the invention, a layer of N-drift layer is firstly extended, then ion implantation is carried out on the N-drift layer, the range and the concentration of the ion implantation are controlled, and finally a plurality of layers of N-type bottom auxiliary layers with different concentrations are formed.
The N-type bottom auxiliary layer can be provided with a plurality of layers of regions with different doping concentrations, the regions with different doping concentrations are sequentially stacked to form the N-type bottom auxiliary layer, the doping concentration of each layer is sequentially decreased from the substrate, the concentration of each layer of the N-type bottom auxiliary layer is sequentially increased to the direction of the substrate, so that current can be ensured to smoothly pass through the N-type bottom auxiliary layer and flow to the N+ substrate.
When the traditional super junction Schottky diode is manufactured, the edge of the P column formed finally is not smooth due to the imperfect annealing process, the charge balance of the super junction Schottky diode is affected by the edge of the P column which is not smooth, and therefore the electrical performance of the super junction Schottky diode is reduced.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A superjunction schottky diode with an improved P-pillar, comprising: a P-type doped layer;
the P-type doping layer is positioned between the P column and the N-drift layer;
and the included angle between the contact surface of the P-type doped layer and the N-drift layer and the central axis of the super junction Schottky diode is 5-15 degrees.
2. The super junction schottky diode with improved P-pillar of claim 1, further comprising: an N-type bottom auxiliary layer;
the N-type bottom auxiliary layer is positioned between the P column and the N+ substrate;
the N-drift layer forms a conductive channel with the N-type bottom auxiliary layer and the N+ substrate.
3. The super junction schottky diode with improved P-pillars of claim 2, wherein the width of said N-type bottom auxiliary layer is at a minimum the width of said P-pillars;
the width of the N-type bottom auxiliary layer is the sum of the width of the P column and the width of the N-drift layer at most.
4. The super junction schottky diode with improved P-pillars of claim 2, wherein said N-type bottom auxiliary layer has a doping concentration less than said n+ substrate.
5. The super junction schottky diode with improved P-pillars of claim 2, wherein said N-type bottom auxiliary layer has a doping concentration greater than said N-drift layer.
6. The super junction schottky diode with improved P-pillars of claim 2, wherein said N-type bottom auxiliary layer has a doping concentration of 10 16 ~10 19 cm -3 。
7. The super junction schottky diode with improved P-pillar of claim 1, further comprising: an anode and a cathode;
the cathode is positioned below the N+ substrate;
the anode is located over the N-drift layer and the P-pillars.
8. The super junction schottky diode with improved P-pillars of claim 2, wherein said N-type bottom auxiliary layer comprises multiple layers of regions of different doping concentrations;
and in the areas with different doping concentrations, the doping concentration of the area positioned on the upper layer of the N-type bottom auxiliary layer is smaller than that of the area positioned on the lower layer of the N-type bottom auxiliary layer.
9. A method of fabricating a superjunction schottky diode with an improved P-pillar, comprising:
epitaxial N-drift layer and P column above N+ substrate;
doping a P-type doped layer on the side wall of the P column;
and depositing a metal electrode.
10. The method of manufacturing a super junction schottky diode with improved P-pillars of claim 9, further comprising: and doping the N-drift layer for multiple times to form a plurality of N-type bottom auxiliary layers with different concentrations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311008130.5A CN116722033A (en) | 2023-08-11 | 2023-08-11 | Super junction schottky diode with improved P column and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311008130.5A CN116722033A (en) | 2023-08-11 | 2023-08-11 | Super junction schottky diode with improved P column and preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116722033A true CN116722033A (en) | 2023-09-08 |
Family
ID=87875624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311008130.5A Pending CN116722033A (en) | 2023-08-11 | 2023-08-11 | Super junction schottky diode with improved P column and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116722033A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102577A (en) * | 1999-09-30 | 2001-04-13 | Toshiba Corp | Semiconductor device |
| CN103594523A (en) * | 2013-11-07 | 2014-02-19 | 哈尔滨工程大学 | Double-layer super-junction Schottky diode |
| US20140252456A1 (en) * | 2013-03-07 | 2014-09-11 | Silergy Semiconductor Technology (Hangzhou) Ltd | Semiconductor device and its manufacturing method |
| US20160197201A1 (en) * | 2015-01-02 | 2016-07-07 | Cree, Inc. | Power semiconductor devices having superjunction structures with implanted sidewalls and methods of fabricating such devices |
| CN106158922A (en) * | 2015-04-13 | 2016-11-23 | 北大方正集团有限公司 | A kind of epitaxial wafer of super-junction semiconductor device and preparation method thereof |
| CN107482060A (en) * | 2016-06-08 | 2017-12-15 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN112002750A (en) * | 2020-08-26 | 2020-11-27 | 上海华虹宏力半导体制造有限公司 | Super junction and manufacturing method thereof |
| CN112201686A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and terminal |
| CN112786677A (en) * | 2019-11-01 | 2021-05-11 | 南通尚阳通集成电路有限公司 | Super junction device and manufacturing method thereof |
| CN114639718A (en) * | 2022-02-24 | 2022-06-17 | 山东大学 | Gallium nitride-based vertical super-junction Schottky diode and preparation method thereof |
| CN115241286A (en) * | 2022-09-21 | 2022-10-25 | 深圳平创半导体有限公司 | SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof |
-
2023
- 2023-08-11 CN CN202311008130.5A patent/CN116722033A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102577A (en) * | 1999-09-30 | 2001-04-13 | Toshiba Corp | Semiconductor device |
| US20140252456A1 (en) * | 2013-03-07 | 2014-09-11 | Silergy Semiconductor Technology (Hangzhou) Ltd | Semiconductor device and its manufacturing method |
| CN103594523A (en) * | 2013-11-07 | 2014-02-19 | 哈尔滨工程大学 | Double-layer super-junction Schottky diode |
| US20160197201A1 (en) * | 2015-01-02 | 2016-07-07 | Cree, Inc. | Power semiconductor devices having superjunction structures with implanted sidewalls and methods of fabricating such devices |
| CN106158922A (en) * | 2015-04-13 | 2016-11-23 | 北大方正集团有限公司 | A kind of epitaxial wafer of super-junction semiconductor device and preparation method thereof |
| CN107482060A (en) * | 2016-06-08 | 2017-12-15 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN112786677A (en) * | 2019-11-01 | 2021-05-11 | 南通尚阳通集成电路有限公司 | Super junction device and manufacturing method thereof |
| CN112002750A (en) * | 2020-08-26 | 2020-11-27 | 上海华虹宏力半导体制造有限公司 | Super junction and manufacturing method thereof |
| CN112201686A (en) * | 2020-09-08 | 2021-01-08 | 浙江大学 | Super junction device and terminal |
| CN114639718A (en) * | 2022-02-24 | 2022-06-17 | 山东大学 | Gallium nitride-based vertical super-junction Schottky diode and preparation method thereof |
| CN115241286A (en) * | 2022-09-21 | 2022-10-25 | 深圳平创半导体有限公司 | SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7968919B2 (en) | Integrated circuit including a charge compensation component | |
| CN114744037A (en) | Shielding gate groove type field effect transistor with variable doping concentration structure and preparation method thereof | |
| CN117334746A (en) | Source electrode groove integrated SBD super-junction SiC MOS with oxide layer and preparation method | |
| CN117253905A (en) | SiC device with floating island structure and preparation method thereof | |
| CN117423730A (en) | sJ SiC VDMOS with split gate and preparation method thereof | |
| CN117334745A (en) | Source electrode groove integrated SBD super junction SiC MOS and preparation method | |
| CN116779685A (en) | SJ VDMOS with SJ SBD and preparation method thereof | |
| CN113555286B (en) | Gallium oxide super junction Schottky diode and preparation method thereof | |
| CN116722033A (en) | Super junction schottky diode with improved P column and preparation method | |
| CN114141860A (en) | Shielding gate structure groove type power semiconductor device and preparation method thereof | |
| CN116741812A (en) | N-BAL-based super junction Schottky diode for improving current density and preparation method thereof | |
| CN117457749B (en) | SiC LMOS with P-type space layer below grid electrode and preparation method | |
| CN111106012B (en) | Method for realizing local service life control of semiconductor device | |
| CN117334748B (en) | Source electrode trench integrated SBD and HK medium SiC UMOS and preparation method | |
| CN117457748A (en) | SiC super-junction MOS with P-type space layer below grid electrode and preparation method | |
| CN117317007A (en) | SiC UMOS with stepped CSL layer and preparation method | |
| CN117423731A (en) | SJ SiC VDMOS with heterojunction and preparation method thereof | |
| CN117727756A (en) | High-voltage-resistant GaN HEMT suitable for high-frequency application and preparation method | |
| CN117476758A (en) | IGBT (insulated Gate Bipolar transistor) capable of improving latch-up resistance based on N+ region and N-region and preparation method | |
| CN117438469A (en) | SiC super-junction MOS with homoheterojunction freewheel channel and preparation method | |
| CN117476757A (en) | IGBT with high latch-up resistance and preparation method | |
| CN117276342A (en) | Groove SiC MOSFET with built-in channel diode and preparation method | |
| CN117334740A (en) | SiC SGT MOSFET with reverse freewheel channel and preparation method | |
| CN117525136A (en) | SiC UMOS with N buried layer and preparation method | |
| CN117497591A (en) | SiC MOSFET integrated with double follow current channels and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |