CN115241286A - SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof - Google Patents
SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of power semiconductors, and particularly provides a SiC semi-super junction type gate bipolar transistor device and a manufacturing method thereof. The junction type gate bipolar transistor structure adopted by the invention can thoroughly eliminate the defects caused by a gate oxide layer, has excellent conduction characteristic and switching performance, and introduces a semi-super junction structure, thereby further improving the breakdown voltage of the junction type gate bipolar transistor structure and reducing the on-resistance.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a SiC semi-super junction type gate bipolar transistor device and a manufacturing method thereof.
Background
Because the forbidden band width of Si (silicon) material is narrow and the bearing capacity to the environment of high temperature, high pressure and the like is poor, the traditional Si power device can not meet the requirements of advanced fields such as aerospace, rail transit, new energy and the like on the device performance.
SiC (silicon carbide) is a novel wide bandgap semiconductor material, has the advantages of wide bandgap, high critical electric field, high electronic saturation velocity, high thermal conductivity and the like, and is an ideal material for manufacturing high-temperature and high-pressure resistant high-power devices.
In recent years, MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors) and JFETs (junction field effect transistors) have been commercialized as SiC-based products, but SiC MOSFETs have been commercialized due to SiC/SiO thereof 2 High interface defect density, si/SiO ratio 2 The interface is higher by about 2-3 orders of magnitude, so that the reliability of a grid oxide layer is low, the electron mobility of a channel is reduced, and the switching speed and the withstand voltage grade of a device are seriously influenced; although the on-resistance of the SiC IGBT is significantly reduced compared to the MOSFET due to the injection of collector holes, the problem of early breakdown of the device still remains because the reliability of the gate oxide layer of the MOSFET at the front stage of the device is low. The existing SiC MOSFET and SiC IGBT both have the defect of low reliability of a grid oxide layer, so that the breakdown voltage of a device is limited, and the grid oxide layer needs to be protected preferentially in the design of the device, so that the flexibility of the design is greatly reduced. Although the SiC JFET device can eliminate the defect of low reliability of a grid oxide layer, the SiC JFET device still has a promotion space in the aspects of breakdown voltage and on-resistance.
Disclosure of Invention
The invention aims to solve at least one technical problem in the background technology and provides a SiC semi-super junction type gate bipolar transistor device and a manufacturing method thereof.
In order to achieve the above object, the present invention provides a SiC semi-super junction type gate bipolar transistor device, including:
a collector metal layer;
the P + type substrate layer is positioned above the collector metal layer and forms a back collector ohmic contact of the device;
an N-type auxiliary layer formed on the P + -type substrate layer;
an N-pillar region formed on the N-type auxiliary layer;
p column regions alternately formed on the N type auxiliary layer with the N column regions along a width direction of the N type auxiliary layer;
the N-drift region is formed on the N column region and the P column region, and one side of the N-drift region, which is far away from the N column region, is provided with two symmetrical ion implantation regions;
the P + doped region is formed on the side walls of the two ion implantation regions of the N-drift region;
a gate metal layer formed on the P + doped region;
an N + emitter region formed on the N-drift region;
an emitter metal layer formed on the N + emitter region;
and a vertical channel is formed between the two ion implantation regions on the N-drift region through the P + doping regions on two sides.
According to one aspect of the invention, the P + type substrate layer is a P-type heavily doped SiC layer.
According to one aspect of the invention, the N-type auxiliary layer is an N-type SiC layer.
According to one aspect of the invention, the N-drift region is an N-type lightly doped SiC layer.
According to one aspect of the invention, the P + doped region is a P-type heavily doped SiC layer.
According to an aspect of the invention, the N + emitter region is an N-type heavily doped SiC layer, formed by ion implantation of N ions.
According to an aspect of the present invention, the collector metal layer is formed of metal Al.
According to an aspect of the invention, the gate metal layer is formed of metal Al.
According to an aspect of the invention, the emitter metal layer is formed of metallic Al.
In order to achieve the above object, the present invention further provides a method for manufacturing the SiC semi-super junction gate bipolar transistor device, including the following steps:
s01, preparing the P + type substrate layer;
s02, forming the N-type auxiliary layer on the P + type substrate layer through heterogeneous epitaxial growth;
s03, forming the N column region on the N type auxiliary layer through homoepitaxial growth;
s04, forming the P column region on two sides of the N column region through an etching process and heteroepitaxial growth;
s05, forming the N-drift region on the N column region through homogeneous epitaxial growth;
s06, forming two symmetrical ion injection regions on one side, far away from the N column region, of the N-drift region through an etching process;
s07, forming the P + doped region on the side wall of the two ion implantation regions through vertical ion implantation and lateral ion implantation;
s08, forming an N + emitter region on the top of the N-drift region through vertically injecting Al ions;
and S09, depositing metal Al on one side of the P + type substrate layer, which is far away from the N type auxiliary layer, on the P + doping region and on the N + emitter region respectively to form the collector metal layer, the grid metal layer and the emitter metal layer.
According to the scheme of the invention, the SiC semi-super Junction Bipolar Transistor device adopts a Junction Gate Bipolar Transistor (JGBT) structure, namely a JFET (Junction field effect Transistor) structure is combined with a BJT (Bipolar Transistor) structure, so that the defects caused by a Gate oxide layer can be thoroughly eliminated, and the device has excellent conducting property and switching performance.
According to the scheme of the invention, the SiC Semi-super junction type gate bipolar transistor device adopts a Semi-super junction (Semi-super junction) structure, and a P column region and an N column region are alternately arranged between an N type auxiliary layer and an N-drift region along the width direction of the N type auxiliary layer. The depth of the P column region and the N column region can be shortened, the process difficulty and the cost are reduced, and the N type auxiliary layer is not influenced by the P column region and the N column region, so that the reverse recovery softness factor of the device body diode is greatly improved, the breakdown voltage is further improved, and the on-resistance is reduced. And the problems that the super-junction depth of the full super-junction is too deep, the manufacturing process difficulty is high, the cost is high, the full super-junction P/N column region is directly connected with the substrate, the drift region is extremely easy to exhaust when the device body diode is in reverse recovery, the reverse recovery hardness of the body diode is high, the reverse recovery charge is large and the like are solved.
According to the scheme of the invention, negative voltage is applied to the grid metal layer-emitter metal layer of the SiC semi-super junction type gate bipolar transistor device, the P + doping region is depleted towards the vertical channel of the N-drift region, and the depletion layer is widened along with the increase of the absolute value of the negative voltage. When the depletion layer is wide enough to expand and fully occupy the vertical channel, the vertical channel is pinched off. At the moment, almost no current flows between a collector metal layer and an emitter metal layer of the SiC semi-super junction gate bipolar transistor device, the SiC semi-super junction gate bipolar transistor device is in a turn-off state, meanwhile, adjacent P column regions and N column regions are mutually depleted, electric fields of the P column regions and the N column regions are distributed in a rectangular mode, and the breakdown voltage of the device is improved; when negative voltage or positive voltage is applied to a gate metal layer-an emitter metal layer of the SiC semi-super junction type gate bipolar transistor device, the P + doped region does not form a widened depletion layer, so that current flows from a collector metal layer to the emitter metal layer through the N type auxiliary layer, the N column region and the N-drift region in sequence, the SiC semi-super junction type gate bipolar transistor device is in a conducting state, and the N column region provides a low-resistance path for the current, so that the conducting resistance is reduced.
According to the scheme of the invention, the groove gate structure adopted by the SiC semi-super junction type gate bipolar transistor device can reduce the cell size of the device, improve the design flexibility and reduce the manufacturing cost.
Drawings
Fig. 1 schematically shows a structural view of a SiC semi super junction gate bipolar transistor device according to an embodiment of the present invention;
fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, and fig. 8 are structural diagrams showing a state in which a SiC semi-superjunction type gate bipolar transistor device is manufactured;
in the figure:
100-P + type substrate layer, 110-N type auxiliary layer, 120-N column region, 130-P column region, 140-N-drift region, 141-ion implantation region, 142-P + doping region, 143-N + emitter region, 144-vertical channel, 150-collector metal layer, 160-gate metal layer and 170-emitter metal layer.
Detailed Description
The content of the invention will now be discussed with reference to exemplary embodiments. It is to be understood that the embodiments discussed are merely intended to enable one of ordinary skill in the art to better understand and thus implement the teachings of the present invention, and do not imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment".
Fig. 1 schematically shows a structural view of a SiC semi super junction gate bipolar transistor device according to an embodiment of the present invention. As shown in fig. 1, in the SiC semi-superjunction bipolar transistor device according to this embodiment, a collector metal layer 150, a P + -type substrate layer 100, an N-type auxiliary layer 110, N-pillar regions 120 and P-pillar regions 130 alternately formed on the N-type auxiliary layer 110 in the width direction of the N-type auxiliary layer 110, an N-drift region 140 located on the N-pillar regions 120 and the P-pillar regions 130, P + -doped regions 142 located on both sides of the N-drift region 140, a gate metal layer 160 on the P + -doped regions 142, and emitter metal layers 170 on the N + -emitter regions 143 and the N + -emitter regions 143 on the N-drift region 140 are sequentially arranged from bottom to top.
Specifically, in the present embodiment, the collector metal layer 150 is formed by depositing Al metal to form collector conduction.
The P + type substrate layer 100 is a P-type heavily doped SiC layer forming a backside collector ohmic contact.
The N-type auxiliary layer 110 is an N-type SiC layer and is formed on the P + -type substrate layer 100 by epitaxial growth.
The N column region 120 is an N type SiC layer formed on the N type auxiliary layer 110 by homoepitaxial growth.
P-column region 130 is a P-type SiC layer and is formed on N-type auxiliary layer 110 by heteroepitaxial growth, N-column regions 120 and P-column regions 130 are alternately formed on N-type auxiliary layer 110, and adjacent N-column regions 120 and P-column regions 130 form a super junction structure.
The N-drift region 140, which is an N-type lightly doped SiC layer, provides a drift path, i.e., a conductive path, for carriers and also provides voltage protection for reverse breakdown.
The P + doped region 142, which is a P-type heavily doped SiC layer, is formed by ion implantation of Al ions for pinching off the vertical channel 144, i.e., closing the conductive path.
The gate metal layer 160 is formed by depositing Al metal to form a gate conductor.
The N + emitter region 143, which is an N-type heavily doped SiC layer, is formed by ion implantation of N ions, forming an emitter ohmic contact.
The emitter metal layer 170 is formed by depositing Al metal to form an emitter conductor.
Wherein, a side of the N-drift region 140 away from the N column region 120 has two symmetrical ion implantation regions 141, i.e., two symmetrical regions with L-shaped sidewalls for supporting the P + doping region 142 in fig. 1.
According to the scheme of the invention, the third-generation semiconductor material SiC (silicon carbide) used by the invention becomes an ideal material for preparing high-voltage, high-temperature, high-power and radiation-resistant power electronic devices by virtue of excellent material characteristics. SiC-based devices exhibit application potential far beyond traditional Si-based devices, especially in power devices. Compared with the traditional Si-based power device, the SiC-based device can effectively relieve the contradiction between the breakdown voltage and the on-resistance of the device, and the required epitaxial thickness of the SiC-based device under the same withstand voltage is only 1/10 of that of the Si-based device, so that the characteristic on-resistance is greatly reduced, the working temperature and frequency of the system are improved, the power loss of the system is reduced, and the like. This allows the application system to have a smaller volume, weight and cooling equipment.
Specifically, in the present embodiment, the upper portion of the SiC semi-super junction gate bipolar transistor device includes an N-drift region 140, P + doped regions 142 located at both sides of the N-drift region 140, a gate metal layer 160 on the P + doped regions 142, an emitter metal layer 170 on the N + emitter region 143 and the N + emitter region 143 on the N-drift region 140, and forms a JFET (junction field effect transistor) structure; the lower part comprises a collector metal layer 150 and a P + type substrate layer 100; wherein the lower P + type substrate layer 100 and the upper N-drift region 140 and P + type substrate layer 100 constitute a P-N-P type BJT (bipolar transistor) structure. In this embodiment, the SiC semi-super Junction Bipolar Transistor device adopts a JFET structure in combination with a BJT structure to form a Junction Gate Bipolar Transistor (JGBT) structure, which has the dual advantages of the JFET and the BJT: the high-voltage switch has the advantages of high breakdown voltage, low on-resistance, high switching speed, large current gain and the like. And the design of the grid oxide layer is removed, so that the defects caused by the grid oxide layer can be thoroughly eliminated. Further, in the present embodiment, a Semi-super junction (Semi-super junction) structure is introduced, specifically, the N-type auxiliary layer 110, the N column regions 120 and the P column regions 130 alternately formed on the N-type auxiliary layer 110 in the width direction of the N-type auxiliary layer 110, and the N-drift region 140 located on the N column regions 120 and the P column regions 130, wherein the N column regions 120 and the P column regions 130 are formed on the N-type auxiliary layer 110. Compared with a full super junction structure, the semi super junction structure can shorten the depths of the P column region and the N column region 120, reduce the process difficulty and cost, greatly improve the reverse recovery softness factor of the device body diode because the N type auxiliary layer 110 is not influenced by the P column region 130 and the N column region 120, further improve the breakdown voltage of the invention and reduce the on resistance.
In operation, a negative voltage is applied to the gate metal layer 160 of the SiC semi-super junction gate bipolar transistor device, the P + doped region 142 is depleted towards the vertical channel 144 of the N-drift region 140, and the depletion layer widens as the absolute value of the negative voltage increases. When the depletion layer is wide enough to expand and fully occupy the vertical channel 144, the vertical channel 144 is pinched off. At this time, almost no current flows between the collector metal layer 150 and the emitter metal layer 170 of the SiC half super junction type gate bipolar transistor device, the SiC half super junction type gate bipolar transistor device is in a turn-off state, meanwhile, the adjacent P column region 130 and the N column region 120 are mutually depleted, the electric fields of the P column region 130 and the N column region 120 are in rectangular distribution, and the breakdown voltage of the device is improved; when no voltage or a positive voltage is applied to the gate metal layer 160 of the SiC half super junction gate bipolar transistor device, the P + doped region 142 does not form a widened depletion layer, and therefore, a current flows from the collector metal layer 150 to the emitter metal layer 170 through the N-type auxiliary layer 110, the N column region 120, and the N-drift region 140 in this order, the SiC half super junction gate bipolar transistor device is in an on state, and at this time, the N column region 120 provides a low resistance path for the current, thereby reducing the on resistance. And the unit cell of the invention can be made smaller, thus reducing the manufacturing cost of the device.
Further, in order to achieve the above object, the present invention further provides a method for manufacturing the above SiC half super junction type gate bipolar transistor device, including the following steps:
s01, preparing a P + type substrate layer 100, wherein the doping concentration of the P + type substrate layer 100 is C1, the thickness is 100-500 mu m, and 1e19cm -3 ≤C1＜1e21cm -3 ；
S02. As shown in figure 2, an N-type auxiliary layer 110 is formed on the P + type substrate layer 100 through heterogeneous epitaxial growth, the doping concentration of the N-type auxiliary layer 110 is C2, the thickness of the N-type auxiliary layer is 1 mu m to 20 mu m, and 1e17cm -3 ＜C2＜1e20cm -3 ；
S03. As shown in FIG. 3, an N column region 120 is formed on the N type auxiliary layer 110 by homoepitaxial growth, the doping concentration of the N column region 120 is C3, the thickness is 1 μm to 50 μm, the width is 2 μm to 50 μm, wherein 1e14cm -3 ＜C4＜1e18cm -3 ；
S04, as shown in figure 4, forming a P column region 130 on two sides of the N column region 120 through an etching process and heterogeneous epitaxial growth, wherein the doping concentration of the P column region 130 is C4, the thickness is 1-50 μm, the width is 1-25 μm, and 1e14cm -3 ＜C4＜1e18cm -3 The width of the N pillar region 120 is typically 2 times the width of the P pillar region 130;
s05, as shown in FIG. 5, an N-drift region 140 is formed on the N column region 120 by homoepitaxial growth, the doping concentration of the N-drift region 140 is C5, wherein 1e13cm -3 ＜C5＜1e17cm -3 ；
S06, as shown in FIG. 6, forming two symmetrical ion implantation regions 141 on one side of the N-drift region 140 away from the N column region 120 through an etching process;
s07. As shown in FIG. 7, a P + doped region 142 is formed on the sidewall of two ion implantation regions 141 by vertical ion implantation and lateral ion implantation, the doping concentration of the P + doped region 142 is C6, wherein 1e19cm -3 ＜C6＜1e21cm -3 ；
S08. As shown in FIG. 8, an N + emitter region 143 is formed on the top of the N-drift region 140 by vertically implanting Al ions;
s09, depositing Al metal on the P + type substrate layer 100, the P + doped region 142, and the N + emitter region 143, respectively, to form a collector metal layer 150, a gate metal layer 160, and an emitter metal layer 170, and finally forming the structure shown in fig. 1.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A SiC semi-superjunction junction gate bipolar transistor device, comprising:
a collector metal layer (150);
a P + type substrate layer (100) located above the collector metal layer (150) forming a backside collector ohmic contact of the device;
an N-type auxiliary layer (110) formed on the P + -type substrate layer (100);
an N-pillar region (120) formed on the N-type auxiliary layer (110);
p column regions (130) alternately formed on the N type auxiliary layer (110) with the N column regions (120) in a width direction of the N type auxiliary layer (110);
an N-drift region (140) which is formed on the N column region (120) and the P column region (130) and has two symmetrical ion implantation regions (141) on one side away from the N column region (120);
a P + doped region (142) formed on sidewalls of both of the ion implantation regions (141) of the N-drift region (140);
a gate metal layer (160) formed on the P + doped region (142);
an N + emitter region (143) formed on the N-drift region (140);
an emitter metal layer (170) formed on the N + emitter region (143);
a vertical channel (144) is formed between the two ion implantation regions (141) on the N-drift region (140) through the P + doping regions (142) on two sides.
2. The SiC half superjunction junction bipolar transistor device of claim 1, wherein the P + -type substrate layer (100) is a P-type heavily doped SiC layer.
3. The SiC half superjunction bipolar transistor device of claim 1, wherein the N-type auxiliary layer (110) is an N-type SiC layer.
4. The SiC semi-superjunction junction gate bipolar transistor device of claim 1, wherein the N-drift region (140) is an N-type lightly doped SiC layer.
5. The SiC half superjunction junction bipolar transistor device of claim 1, wherein the P + doped region (142) is a P-type heavily doped SiC layer.
6. The SiC semi-superjunction junction gate bipolar transistor device according to claim 1, wherein the N + emitter region (143) is an N-type heavily doped SiC layer formed by ion implantation of N ions.
7. The SiC semi superjunction junction gate bipolar transistor device of claim 1, wherein the collector metal layer (150) is formed of metal Al.
8. The SiC semi-superjunction junction gate bipolar transistor device of claim 1, wherein the gate metal layer (160) is formed of metal Al.
9. The SiC semi superjunction junction gate bipolar transistor device of claim 1, wherein the emitter metal layer (170) is formed of metal Al.
10. Method of manufacturing a SiC semi superjunction junction gate bipolar transistor device according to any of claims 1 to 9, comprising the steps of:
s01, preparing the P + type substrate layer (100);
s02, forming the N-type auxiliary layer (110) on the P + type substrate layer (100) through heterogeneous epitaxial growth;
s03, forming the N column region (120) on the N type auxiliary layer (110) through homoepitaxial growth;
s04, forming the P column region (130) on two sides of the N column region (120) through an etching process and heteroepitaxial growth;
s05, forming the N-drift region (140) on the N column region (120) through homogeneous epitaxial growth;
s06, forming two symmetrical ion implantation regions (141) on one side, far away from the N column region (120), of the N-drift region (140) through an etching process;
s07, forming the P + doped region (142) on the side wall of the two ion implantation regions (141) through vertical ion implantation and lateral ion implantation;
s08, forming an N + emitter region (143) on the top of the N-drift region (140) by vertically injecting Al ions;
and S09, depositing metal Al on the side, far away from the N-type auxiliary layer (110), of the P + type substrate layer (100), on the P + doping region (142) and on the N + emitter region (143) to form the collector metal layer (150), the gate metal layer (160) and the emitter metal layer (170).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211146638.7A CN115241286B (en) | 2022-09-21 | 2022-09-21 | SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211146638.7A CN115241286B (en) | 2022-09-21 | 2022-09-21 | SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof |
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| CN116544273A (en) * | 2023-07-07 | 2023-08-04 | 深圳平创半导体有限公司 | Reverse conducting-junction gate bipolar transistor device and manufacturing method thereof |
| CN116544282A (en) * | 2023-07-06 | 2023-08-04 | 深圳平创半导体有限公司 | Silicon carbide junction gate bipolar transistor device and manufacturing method thereof |
| CN116722033A (en) * | 2023-08-11 | 2023-09-08 | 深圳天狼芯半导体有限公司 | Super junction schottky diode with improved P column and preparation method |
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| CN115241286B (en) | 2023-01-31 |
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