CN114613861B - Groove type SiC JFET device and preparation method thereof - Google Patents
Groove type SiC JFET device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 53
- 229910010271 silicon carbide Inorganic materials 0.000 description 51
- 239000000463 material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
- H01L29/66909—Vertical transistors, e.g. tecnetrons
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Abstract
The invention relates to the technical field of power semiconductors, and particularly provides a groove type SiC JFET device and a preparation method thereof, wherein the device comprises: a drain metal layer; the N + type substrate layer is formed on the drain metal and forms the back drain ohmic contact of the device; an N-type buffer layer formed on the N + type substrate layer; the N-type drift region is formed on the N-type buffer layer, and one side of the N-type drift region, which is far away from the N-type buffer layer, is provided with two symmetrical ion injection regions; the P-type doped region is formed on the side walls of the two ion implantation regions of the N-type drift region; a P + ohmic contact region formed on the P-type doped region; a gate metal layer formed on the P + ohmic contact region; the N + ohmic contact region is positioned on the P + ohmic contact region and is connected with the P-type doped region and the N-type drift region; a source metal layer formed on the N + ohmic contact region; and a vertical channel is formed between the two ion implantation regions on the N-type drift region through a P-type doping region and a P + ohmic contact region formed in the two ion implantation regions.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a groove type SiC JFET device and a preparation method thereof.
Background
Because the forbidden band width of the silicon (Si) material is narrow and the silicon (Si) material has poor bearing capacity to environments such as high temperature and high pressure, the traditional Si power device can not meet the requirements of advanced fields such as aerospace, rail transit, new energy and the like on the device performance.
In the existing unipolar type power semiconductor device, the SiC mosfet device has lower reliability of the gate oxide layer and lower short-circuit capability of the device due to the lower than expected SiC/SiO2 interface performance.
The existing SiC JFET device is a planar device, and current flows from the source, needs to pass through a long and narrow horizontal channel region, then flows into the drift region, and is finally collected by the drain. Due to the existence of the long and narrow transverse channel, the on-resistance of the planar SiC JFET device is larger, and the cell size of the device is difficult to be smaller. In addition, in the preparation of the planar SiC JFET device, a channel region at the top of the device needs to be obtained through secondary epitaxial growth, so that the process is complex and the cost is high.
Disclosure of Invention
The invention aims to solve at least one technical problem in the background art and provides a groove type SiC JFET device and a preparation method thereof.
To achieve the above object, the present invention provides a trench type SiC JFET device, comprising:
a drain metal layer;
the N + type substrate layer is formed on the drain metal to form back drain ohmic contact of the device;
an N-type buffer layer formed on the N + type substrate layer;
the N-type drift region is formed on the N-type buffer layer, and one side of the N-type drift region, which is far away from the N-type buffer layer, is provided with two symmetrical ion injection regions;
the P-type doped region is formed on the side walls of the two ion implantation regions of the N-type drift region;
the P + ohmic contact region is formed on the P-type doped region;
a gate metal layer formed on the P + ohmic contact region;
the N + ohmic contact region is positioned on the P + ohmic contact region and is connected with the P-type doped region and the N-type drift region;
a source metal layer formed on the N + ohmic contact region;
and a vertical channel is formed between the two ion implantation regions on the N-type drift region through the P-type doping region and the P + ohmic contact region formed in the two ion implantation regions.
According to an aspect of the invention, the drain metal layer is formed of metal Al.
According to one aspect of the invention, the N + type substrate layer is an N-type heavily doped SiC layer.
According to one aspect of the invention, the N-type buffer layer is an N-type doped SiC layer.
According to one aspect of the invention, the N-type drift region is an N-type lightly doped SiC layer.
According to one aspect of the invention, the P-type doped region is a P-type doped SiC layer formed by ion implantation of Al ions.
According to one aspect of the invention, the P + ohmic contact region is a P-type heavily doped SiC layer formed by ion implantation of Al ions to form a gate ohmic contact.
According to one aspect of the invention, the N + ohmic contact region is an N-type heavily doped SiC layer formed by ion implantation of N ions to form a source ohmic contact.
According to an aspect of the present invention, the gate metal layer and the source metal layer are each formed of metal Al.
In order to achieve the above object, the present invention further provides a method for preparing the above trench type SiC JFET device, including:
extending an N-type buffer layer on the N + type substrate layer;
extending an N-type drift region on the N-type buffer layer;
etching two symmetrical ion injection regions on one side of the N-type drift region, which is far away from the N-type buffer layer;
implanting ions into the P-type doped region on the side walls of the two ion implantation regions;
implanting ions into a P + ohmic contact region on the P-type doped region;
forming an N + ohmic contact region on the P-type doped region and the N-type drift region;
respectively depositing metal Al on one side of the N + type substrate layer, which is far away from the N type buffer layer, on the P + ohmic contact region and on the N + ohmic contact region to form a drain metal layer, a gate metal layer and a source metal layer;
a vertical channel is formed between the two ion implantation regions on the N-type drift region through a P-type doping region and a P + ohmic contact region formed in the two ion implantation regions.
According to the scheme of the invention, a negative voltage is applied to the grid electrode and the source electrode, the P-type doped region is depleted towards the N-type drift region, and the depletion layer is widened along with the increase of the absolute value of the negative voltage. The vertical channel is pinched off when the depletion layer is wide enough to expand and fully occupy the N-type drift region. At this time, almost no current flows between the source and the drain of the SiCJFET, and the device is in an off state. When no voltage or a positive voltage is applied to the gate-source, the P-type doped region does not form a widened depletion layer, and therefore, current flows from the source to the drain through the vertical channel, and the device is in an on state.
According to the scheme of the invention, the third-generation semiconductor material silicon carbide (SiC) used by the invention has the advantages of wide forbidden band, high critical electric field, high electronic saturation velocity, high thermal conductivity and the like, so that the SiC becomes an ideal material for manufacturing high-temperature and high-pressure resistant high-power devices.
The SiC JFET device controls the on and off of the device by depending on the grid PN junction depletion layer, and a series of problems caused by overlarge defect density of a SiC/SiO2 interface are avoided. Therefore, SiC JFET devices are believed to be able to exploit to the greatest extent the superior performance of SiC materials in high voltage and high frequency applications.
According to the groove type SiC JFET device, after current flows out of the source electrode, the current rapidly enters the drift region after passing through the vertical channel region, and is finally collected by the drain electrode. The vertical channel is shorter, so that the on resistance of the device is smaller, and the unit cell of the device can be smaller, so that the manufacturing cost of the device is reduced. And the groove type SiC JFET device does not need secondary epitaxial growth to prepare a channel, so that the process difficulty is reduced.
The groove type SiC JFET device is formed by combining mesa etching and lateral ion implantation, so that a channel of the device is positioned in the vertical direction. Current flows from the source, through the channel region at the top of the device, directly into the drift region, and is collected by the drain. Through the introduction of mesa etching and side wall ion implantation, the structure of the groove type SiC JFET device avoids multiple epitaxial growth and strict photoetching alignment requirements, and the preparation process is relatively simple. Meanwhile, the length and the width of the channel of the device can be determined by the SiC etching depth, the width of the table top and the ion implantation condition respectively, and the design space of the device is larger.
The SiC-based power device provided by the invention has the performance far superior to that of a Si-based device. And the reliability problem of a grid oxide layer is avoided, and the reliability of the device is superior to that of a SiCMOS MOSFET device. And the performance and the cost of the device are far superior to those of a planar SiJFET device.
The invention does not need to grow a grid oxide layer, thereby improving the reliability of the device. And a horizontally long and narrow channel does not need to be grown by secondary epitaxy, so that the process difficulty and the on-resistance of the device are reduced. And the cell size can be smaller, and the cost of the device can be further reduced.
Drawings
Figure 1 schematically illustrates a block diagram of a trench type SiC JFET device according to one embodiment of the invention;
fig. 2, 3 and 4 show the structural diagrams of the trench type SiC JFET device in different states of manufacture, respectively.
Detailed Description
The content of the invention will now be discussed with reference to exemplary embodiments. It is to be understood that the embodiments discussed are merely intended to enable one of ordinary skill in the art to better understand and thus implement the teachings of the present invention, and do not imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment".
Fig. 1 schematically shows a structural view of a trench type SiC JFET device according to an embodiment of the present invention. As shown in fig. 1, in the present embodiment, a trench type SiC JFET device includes:
from bottom to top in proper order drain electrode metal level, N + type substrate layer, N type buffer layer, N-type drift region, the P type doping region of both sides, P + ohmic contact zone to and grid metal level, the top is N + ohmic contact zone and source metal level.
Specifically, in this embodiment mode, the drain metal layer is formed by depositing Al metal to form the drain electrode.
The N + type substrate layer is an N type heavily doped SiC layer, and ohmic contact of a back drain electrode is formed.
The N-type buffer layer is an N-type doped SiC layer and provides a field stop region for reverse breakdown so that the device can be broken through and broken down.
The N-type drift region is an N-type light doped SiC layer, provides a drift path, namely a conductive path, for a current carrier, and also provides voltage-resistant protection for reverse breakdown.
The P-type doped region is a P-type doped SiC layer and is formed by injecting Al ions into the P-type doped region and is used for pinching off the vertical channel, namely closing the conductive path.
The P + ohmic contact region is a P-type heavily doped SiC layer and is formed by injecting Al ions into the P + ohmic contact region to form gate ohmic contact.
The gate metal layer is formed by depositing Al metal to form a gate conductor.
The N + ohmic contact region is an N-type heavily doped SiC layer and is formed by injecting N ions through ions to form source ohmic contact.
The source metal layer is formed by depositing Al metal to form a source conductor.
As shown in fig. 1, in this embodiment, the side of the N-type drift region away from the N-type buffer layer has two symmetrical ion implantation regions, i.e., two symmetrical regions with L-shaped sidewalls for supporting the P-type doped region in fig. 1.
As shown in fig. 1, in this embodiment, the P-type doped region formed by ion implantation is located on the sidewall of the ion implanted region, which includes the lateral sidewall of the ion implanted region in fig. 1 and the longitudinal sidewall of the ion implanted region, i.e., as can be seen from fig. 1, two symmetrical L-shaped structures are also formed by forming the P-type doped region by ion implantation.
As shown in fig. 1, in the present embodiment, the vertical channel is formed by mesa etching and lateral ion implantation (i.e., by etching two symmetrical ion implantation regions on the N-type drift region as described above, and then forming a vertical channel in the region between the two ion implantation regions after passing through the P-type doped region and the P + ohmic contact region formed in the two ion implantation regions), and the vertical channel is an N-type lightly doped SiC channel. Current flows in from the source, through the vertical channel into the drift region, and finally out of the drain.
Further, in order to achieve the above object, the present invention also provides a method for manufacturing the above trench type SiC JFET device, fig. 2, fig. 3 and fig. 4 respectively show structural diagrams in different states of manufacturing the trench type SiC JFET device, and referring to fig. 2 to fig. 4, the method includes the following steps:
extending an N-type buffer layer on the N + type substrate layer;
extending an N-type drift region on the N-type buffer layer;
forming an N + ohmic contact region on the N-type drift region;
forming a source metal layer on the N + ohmic contact region;
etching two symmetrical ion injection regions on one side of the N-type drift region, which is far away from the N-type buffer layer;
implanting ions into P-type doped regions on the side walls of the two ion implantation regions, wherein the P-type doped regions are connected with the N-type drift region and the N + ohmic contact region;
implanting ions into a P + ohmic contact region on the P-type doped region;
respectively depositing metal Al on one side of the N + type substrate layer, which is far away from the N type buffer layer, and the P + ohmic contact region to form a drain metal layer and a gate metal layer;
and a vertical channel is formed in a region between the two ion implantation regions on the N-type drift region after passing through a P-type doping region and a P + ohmic contact region formed in the two ion implantation regions.
According to the scheme of the invention, when negative voltage is applied to the grid electrode and the source electrode, the P-type doped region is depleted towards the N-type drift region, and the depletion layer becomes wider as the absolute value of the negative voltage is increased. The vertical channel is pinched off when the depletion layer is wide enough to expand and fully occupy the N-type drift region. At this time, almost no current flows between the source and the drain of the SiCJFET, and the device is in an off state. When no voltage or a positive voltage is applied to the gate-source, the P-type doped region does not form a widened depletion layer, and therefore, current flows from the source to the drain through the vertical channel, and the device is in an on state.
According to the scheme of the invention, the third-generation semiconductor material silicon carbide (SiC) used by the invention has the advantages of wide forbidden band, high critical electric field, high electron saturation velocity, high thermal conductivity and the like, so that the SiC becomes an ideal material for manufacturing high-temperature and high-pressure resistant high-power devices.
The SiC JFET device controls the on and off of the device by depending on the grid PN junction depletion layer, and a series of problems caused by overlarge defect density of a SiC/SiO2 interface are avoided. Therefore, SiC JFET devices are believed to be able to exploit to the greatest extent the superior performance of SiC materials in high voltage and high frequency applications.
According to the groove type SiC JFET device, after current flows out of the source electrode, the current rapidly enters the drift region after passing through the vertical channel region, and is finally collected by the drain electrode. The vertical channel is shorter, so that the on resistance of the device is smaller, and the unit cell of the device can be smaller, so that the manufacturing cost of the device is reduced. And the groove type SiC JFET device does not need secondary epitaxial growth to prepare a channel, so that the process difficulty is reduced.
The groove type SiC JFET device is formed by combining mesa etching and lateral ion implantation, so that a channel of the device is positioned in the vertical direction. Current flows from the source, through the channel region at the top of the device, directly into the drift region, and is collected by the drain. Through the introduction of mesa etching and side wall ion implantation, the structure of the groove type SiC JFET device avoids multiple epitaxial growth and strict photoetching alignment requirements, and the preparation process is relatively simple. Meanwhile, the length and the width of the channel of the device can be determined by the SiC etching depth, the width of the table top and the ion implantation condition respectively, and the design space of the device is larger.
The SiC-based power device provided by the invention has the performance far superior to that of a Si-based device. And the reliability problem of a grid oxide layer is avoided, and the reliability of the device is superior to that of a SiCMOS MOSFET device. And the performance and the cost of the device are far superior to those of a planar SiJFET device.
The invention does not need to grow a grid oxide layer, thereby improving the reliability of the device. And a horizontally long and narrow channel does not need to be grown by secondary epitaxy, so that the process difficulty and the on-resistance of the device are reduced. And the cell size can be smaller, and the cost of the device can be further reduced.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (7)
1. A trench type SiC JFET device, comprising:
a drain metal layer;
the N + type substrate layer is positioned above the drain metal layer and forms back drain ohmic contact of the device;
the N-type buffer layer is formed on the N + type substrate layer;
the N-type drift region is formed on the N-type buffer layer, and one side of the N-type drift region, which is far away from the N-type buffer layer, is provided with two symmetrical ion injection regions;
the P-type doped region is formed on the side walls of the two ion implantation regions of the N-type drift region;
the P + ohmic contact region is formed on the P-type doped region;
a gate metal layer formed on the P + ohmic contact region;
the N + ohmic contact region is positioned on the P + ohmic contact region and is connected with the P-type doped region and the N-type drift region;
a source metal layer formed on the N + ohmic contact region;
a vertical channel is formed between the two ion implantation regions on the N-type drift region through the P-type doping region and the P + ohmic contact region formed in the two ion implantation regions;
the drain metal layer is formed by metal Al;
the P-type doped region is a P-type doped SiC layer and is formed by injecting Al ions into the P-type doped SiC layer;
the P + ohmic contact region is a P-type heavily doped SiC layer and is formed by injecting Al ions into the P + ohmic contact region to form gate ohmic contact.
2. The trench type SiC JFET device of claim 1, wherein the N + type substrate layer is an N type heavily doped SiC layer.
3. The trench type SiC JFET device of claim 1, wherein the N type buffer layer is an N type doped SiC layer.
4. The trench type SiC JFET device of claim 1, wherein the N-type drift region is an N-type lightly doped SiC layer.
5. The trench type SiC JFET device of claim 1, wherein the N + ohmic contact region is an N type heavily doped SiC layer formed by ion implantation of N ions to form a source ohmic contact.
6. The trench SiC JFET device of any one of claims 1 to 5, wherein the gate metal layer and the source metal layer are both formed of metallic Al.
7. A method of making the trench SiC JFET device of any of claims 1 to 6, comprising:
extending an N-type buffer layer on the N + type substrate layer;
extending an N-type drift region on the N-type buffer layer;
etching two symmetrical ion injection regions on one side of the N-type drift region, which is far away from the N-type buffer layer;
implanting ions into the P-type doped region on the side walls of the two ion implantation regions;
implanting ions into a P + ohmic contact region on the P-type doped region;
forming an N + ohmic contact region on the P-type doped region and the N-type drift region;
respectively depositing metal Al on one side of the N + type substrate layer, which is far away from the N type buffer layer, on the P + ohmic contact region and on the N + ohmic contact region to form a drain metal layer, a gate metal layer and a source metal layer;
a vertical channel is formed between the two ion injection regions on the N-type drift region through a P-type doping region and a P + ohmic contact region formed in the two ion injection regions;
the drain metal layer is formed by metal Al;
the P-type doped region is a P-type doped SiC layer and is formed by injecting Al ions into the P-type doped SiC layer;
the P + ohmic contact region is a P-type heavily doped SiC layer and is formed by injecting Al ions into the P + ohmic contact region to form gate ohmic contact.
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| US20050067630A1 (en) * | 2003-09-25 | 2005-03-31 | Zhao Jian H. | Vertical junction field effect power transistor |
| US7834376B2 (en) * | 2005-03-04 | 2010-11-16 | Siliconix Technology C. V. | Power semiconductor switch |
| CN104409335B (en) * | 2014-11-18 | 2017-11-21 | 中国电子科技集团公司第五十五研究所 | A kind of preparation method of the carborundum JFET grid structures with rectification |
| US10050154B2 (en) * | 2015-07-14 | 2018-08-14 | United Silicon Carbide, Inc. | Trench vertical JFET with ladder termination |
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