CN109065608B

CN109065608B - Transverse bipolar power semiconductor device and preparation method thereof

Info

Publication number: CN109065608B
Application number: CN201810949847.2A
Authority: CN
Inventors: 张金平; 殷鹏飞; 赵阳; 刘竞秀; 李泽宏; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2018-08-20
Filing date: 2018-08-20
Publication date: 2020-12-18
Anticipated expiration: 2038-08-20
Also published as: CN109065608A

Abstract

A lateral bipolar semiconductor power device and a preparation method thereof belong to the technical field of semiconductor power devices. On the premise of keeping the cathode structure of the traditional bipolar power semiconductor device unchanged, the anode trench gate structure and the source region and/or the base region are introduced into the anode region of the device, and the forward conduction voltage drop of the anode diode is bypassed by controlling the anode trench gate structure under the condition of not influencing the normal work and the opening of the device, so that the effect of reducing the forward conduction voltage drop of the power semiconductor device is achieved. After the anode diode is bypassed, minority carrier injection from the anode region to the drift region is reduced, the reverse recovery process time of the device is shortened when the device is turned off, the turn-off speed of the device is improved, and the switching loss is reduced. The invention improves the carrier concentration distribution of the whole N-type drift region and the compromise of forward conduction voltage drop and switching loss; and the manufacturing method of the device does not need to add extra process steps and is compatible with the traditional device manufacturing method.

Description

Transverse bipolar power semiconductor device and preparation method thereof

Technical Field

The invention belongs to the technical field of power semiconductor devices and preparation, and particularly relates to a bipolar semiconductor power device with a transverse MOS control anode and a preparation method thereof.

Background

As a large category of electronic technologies, power electronic technology (another category is information electronic technology) is a technology capable of realizing transmission, processing, storage and control of electric energy, and is suitable for high-power conversion and processing. The technology can change voltage, current, frequency and phase to meet the power consumption requirement of the system, thereby ensuring that the electric energy is properly applied. In addition, the electric energy is processed by the power electronic technology and then used, so that the energy-saving, efficient and environment-friendly effects can be achieved. The power electronic technology is born in the 50 th century and supports the development of modern industry and national defense industry as a new technology. In the civil field, the power electronic technology is mainly applied to the aspects of industrial motor design, power grid construction, household electrical appliances and the like. Modern power electronics technology has begun to be applied in more emerging fields, including new energy (such as high-power wind power generation), smart grids, rail transit, and variable frequency home appliances. In the field of national defense, power electronic technology has played an important role in aerospace, fighters, ships and warships and the like. The application of power electronic technology depends on various power electronic systems, and the core devices of the power electronic systems are power semiconductor devices.

In order to improve the performance and reliability of the power semiconductor device, it is necessary to increase the switching speed of the device under a certain blocking voltage capability, reduce the switching loss of the device, and reduce the forward conduction voltage drop. Fig. 1 shows a structure of a lateral bipolar power semiconductor device, i.e., an IGBT device, when the device is turned on in the forward direction, a P-type anode region (also called P-type anode region) 9 injects hole carriers into an N-type drift region 7, so that the N-type drift region 7 is subjected to conductance modulation, and thus the device obtains a relatively low forward-direction turn-on voltage drop; during the device turn-off process, these minority carriers existing in the N-type drift region 7 need to be extracted during the expansion of the depletion region, which is a reverse recovery process of the device turn-off process. The presence of reverse recovery increases the turn-off time of the device and thus the turn-off loss. Therefore, the contradictory relationship between the on-voltage drop and the off-loss of the device needs to be further optimized.

At present, power semiconductor devices which are developed fastest and applied most widely at home and abroad belong to Insulated Gate Bipolar Transistors (IGBT) and MOS Control Thyristors (MCT). The IGBT device integrates the characteristics of an MOS and a BJT, has the advantages of high input impedance, gate control capability and simple driving circuit of the MOSFET, and also has the advantages of high current density, low conduction voltage drop and high current processing capability of the BJT, and is incomparable to other power semiconductor devices in the field of high-voltage and high-current application, so that the IGBT is an ideal power switch device in the field of power semiconductor application. MCT is a field control bipolar semiconductor power device, belongs to the third generation of power semiconductor devices, has the characteristic that the device can be controlled to be turned on and turned off through one gate, has extremely low conduction voltage drop and high surge current bearing capacity, and has the characteristic of temperature negative feedback. MCTs, by virtue of their significant advantages, have received considerable attention from researchers in semiconductor power devices once they have been proposed.

Lateral power semiconductor devices are generally favored in the power integrated circuit field due to their ease of compatibility with integrated circuit processes, with LIGBT and LMCT being no exceptions, and they also combine the advantages of LDMOS device structures. The LIGBT device and the LMCT are lateral bipolar integrated power devices developed on the basis of an IGBT and an MCT respectively, and the main difference between the LMCT device and the LIGBT device is the cathode structures of the LMCT device and the LIGBT device. Taking LIGBT as an example, the first proposed LIGBT structures are M darwinh and K Board of schwangsi university. In a typical LIGBT structure, P + is replaced by N + at the LDMOS drain, so that a PN junction hole injection mechanism is introduced at the drain, which has the same characteristics as the IGBT structure, and thus the operating principle is basically the same as that of the IGBT, and the difference is only in the difference between the lateral structure and the longitudinal structure. The lateral power device has the characteristic that peak electric fields at a surface anode and a cathode are equal when the device is in voltage resistance, so that a drift region is completely depleted when the device is in voltage resistance. The lateral LIGBT structure is mostly an NPT structure, and an n-buffer layer is required to be added below the p + region of the anode to bear the lateral high voltage.

The lateral power semiconductor device also has the same characteristics as the conventional power semiconductor device, and the contradiction between the conduction voltage drop and the turn-off loss needs to be considered. The turn-off loss of the device is influenced by the minority carrier concentration distribution of a drift region of the device when the device is in forward conduction, and the forward conduction voltage drop of the IGBT (MCT) mainly comprises the following three parts: the voltage drop of the channel in the MOS unit, the voltage drop of the drift region and the voltage drop of the anode diode. Because of the conductivity modulation effect in forward conduction, the voltage drop of the drift region is smaller and the channel voltage drop is lower than that of the anode diode. It is important to consider how the voltage drop of the anode diode is reduced when considering reducing the conduction voltage drop.

Disclosure of Invention

In view of the above, the present invention provides a lateral bipolar power semiconductor device and a manufacturing method thereof, in which an MOS structure controlled by a trench gate is introduced into an anode structure of the lateral bipolar power semiconductor device to control an anode channel inversion to provide a channel for a carrier, so as to implement a forward conduction voltage drop of a bypass anode diode, reduce a conductance modulation effect from an anode region to a drift region, thereby reducing the forward conduction voltage drop during a dynamic switching process of the device, and improve a trade-off relationship between the forward conduction voltage drop and a turn-off loss.

The technical scheme of the invention is as follows:

in one aspect, the present invention provides an IGBT device with a MOS controlled anode, which is actually a lateral bipolar power semiconductor device consisting of a BJT (bipolar transistor) and a MOS (insulated gate field effect transistor).

The first technical scheme is as follows:

a bipolar semiconductor power device with an MOS control anode comprises an anode structure, a drift region structure, a cathode structure and a control gate structure, wherein the anode structure, the drift region structure, the cathode structure and the control gate structure are positioned above a first conduction type semiconductor doping substrate 116; wherein: the drift region structure is positioned on the upper surface of the first conductive type semiconductor doped substrate 116, and comprises a second conductive type semiconductor doped drift region 107; the anode structure is positioned on one side of the top layer of the second conductive type semiconductor doping drift region 107, and comprises a second conductive type semiconductor doping buffer layer 108, a first conductive type semiconductor anode region 109 positioned on the top layer of the second conductive type semiconductor doping buffer layer 108, and an anode metal 118 led out from the first conductive type semiconductor anode region 109; the cathode structure is positioned on the other side of the top layer of the second conductive type semiconductor doping drift region 107, and the cathode structure comprises a first conductive type semiconductor body region 106, a first conductive type semiconductor doping emission region 105, a second conductive type semiconductor doping emission region 104 and a cathode metal 101; the first conductive type semiconductor body region 106 is positioned on the top layer of the second conductive type semiconductor doping drift region 107, the second conductive type semiconductor doping emitter region 104 is positioned on one side, close to the anode structure, of the top layer of the first conductive type semiconductor body region 106, the first conductive type semiconductor doping emitter region 105 is positioned on one side, far away from the anode structure, of the top layer of the first conductive type semiconductor body region 106, and the first conductive type semiconductor doping emitter region 105 and the second conductive type semiconductor doping emitter region 104 are in contact with each other and the upper surface of the first conductive type semiconductor doping emitter region 105 and the upper surface of the second conductive type semiconductor doping emitter region 104; the control gate structure is positioned on the uppermost layer of the device and comprises a control gate electrode 102 and a control gate dielectric layer 103, and the control gate electrode 102 is contacted with the second conductive type semiconductor doping emission region 104 and the first conductive type semiconductor body region 106 through the control gate dielectric layer 103; the method is characterized in that:

the anode structure further comprises a second conductivity type semiconductor doped source region 112 and an anode trench gate structure; the anode structure has a trench therein extending into the second conductivity type semiconductor doped drift region layer 107 in the vertical direction of the device, the second conductivity type semiconductor doped source region 112 being located between the trench and the first conductivity type semiconductor anode region 109; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode 115, a first anode trench gate dielectric layer 113 and a second anode trench gate dielectric layer 114, wherein the first anode trench gate dielectric layer 113 and the second anode trench gate dielectric layer 114 are positioned on the inner wall of a trench, the first anode trench gate dielectric layer 113 is in contact with a second conductive type semiconductor doping source region 112 and a second conductive type semiconductor doping buffer layer 108, and the anode trench gate electrode 115 is positioned in the trench.

Further, the bipolar semiconductor power device of the MOS control anode of the present invention further includes a first conductive type semiconductor doping base region 111, where the first conductive type semiconductor doping base region 111 is located between the anode trench gate structure and the first conductive type semiconductor anode region 109, and is in contact with the upper surface and the side surface of the second conductive type semiconductor doping source region 112; the doping concentration of the first conductivity type semiconductor doped base region 111 is smaller than that of the first conductivity type semiconductor anode region 109.

Based on the scheme, the first conductive type semiconductor doping base region 111 is introduced, when the device is conducted in the forward direction, strong drift region conductance modulation is obtained through the large minority carrier injection efficiency provided by the high-concentration first conductive type semiconductor anode region 109, the conduction voltage drop is reduced, the performance of the device is not affected, the threshold voltage of the control gate structure is reduced by the low-concentration first conductive type semiconductor doping base region 111, the driving loss of the control gate structure is reduced, the switching speed of the control gate structure is improved, the resistance of a control gate structure channel is reduced, the conduction voltage drop of the device is further reduced, and a better bypass effect is achieved.

Further, the depth of the anode trench gate structure in the present invention may be greater than the junction depth of the second conductive type semiconductor doping buffer layer 108, and may also be less than the junction depth of the second conductive type semiconductor doping buffer layer 108, and may also be equal to the junction depth of the second conductive type semiconductor doping buffer layer 108.

Further, in the present invention, the thickness of the second anode trench gate dielectric layer 114 is greater than or equal to the thickness of the first anode trench gate dielectric layer 113.

Furthermore, the drift region structure of the invention can be an NPT structure or an FS structure.

Further, the thickness of the control gate dielectric layer 103 is greater than the thickness of the anode trench gate

dielectric layers

113 and 114 in the present invention.

Further, the width of the control gate electrode 102 is larger than the width of the anode trench gate electrode 115 in the present invention.

Further, the device of the present invention may be a semiconductor-based product, and may also be based on an SOI layer.

Furthermore, the bipolar semiconductor power device of the MOS control anode is made of semiconductor materials of Si, SiC, GaAs or GaN.

The second technical scheme is as follows:

a bipolar semiconductor power device with an MOS control anode comprises an anode structure, a drift region structure, a cathode structure and a control gate structure, wherein the anode structure, the drift region structure, the cathode structure and the control gate structure are positioned above a first conduction type semiconductor doping substrate 116; wherein, the drift region structure is located on the upper surface of the first conductive type semiconductor doped substrate 116, and the drift region structure comprises the second conductive type semiconductor doped drift region 107; the anode structure is positioned on one side of the top layer of the second conductive type semiconductor doping drift region 107, and comprises a second conductive type semiconductor doping buffer layer 108, a first conductive type semiconductor anode region 109 positioned on the top layer of the second conductive type semiconductor doping buffer layer 108, and an anode metal 118 led out from the first conductive type semiconductor anode region 109; the cathode structure is positioned on the other side of the top layer of the second conductive type semiconductor doping drift region 107, and the cathode structure comprises a first conductive type semiconductor body region 106, a first conductive type semiconductor doping emission region 105, a second conductive type semiconductor doping emission region 104 and a cathode metal 101; the first conductive type semiconductor body region 106 is positioned on the top layer of the second conductive type semiconductor doping drift region 107, the second conductive type semiconductor doping emitter region 104 is positioned on one side, close to the anode structure, of the top layer of the first conductive type semiconductor body region 106, the first conductive type semiconductor doping emitter region 105 is positioned on one side, far away from the anode structure, of the top layer of the first conductive type semiconductor body region 106, and the first conductive type semiconductor doping emitter region 105 and the second conductive type semiconductor doping emitter region 104 are in contact with each other and the upper surface of the first conductive type semiconductor doping emitter region 105 and the upper surface of the second conductive type semiconductor doping emitter region 104; the control gate structure is positioned on the uppermost layer of the device and comprises a control gate electrode 102 and a control gate dielectric layer 103, and the control gate electrode 102 is contacted with the second conductive type semiconductor doping emission region 104 and the first conductive type semiconductor body region 106 through the control gate dielectric layer 103; the method is characterized in that:

the bipolar semiconductor power device of the MOS control anode further comprises a first conductive type semiconductor doping base region 111 and an anode trench gate structure, wherein the first conductive type semiconductor doping base region 111 and the anode metal 110 form Schottky contact; the anode structure is internally provided with a groove extending into the second conductive type semiconductor doping drift region layer 107 along the vertical direction of the device, and the first conductive type semiconductor doping base region 111 is positioned between the groove and the first conductive type semiconductor anode region 109; the doping concentration of the first conductive type semiconductor doping base region 111 is smaller than that of the first conductive type semiconductor anode region 109; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode 115, a first anode trench gate dielectric layer 113 and a second anode trench gate dielectric layer 114, wherein the first anode trench gate dielectric layer 113 and the second anode trench gate dielectric layer 114 are positioned on the inner wall of a trench, the first anode trench gate dielectric layer 113 is in contact with a first conductive type semiconductor doping base region 111 and a second conductive type semiconductor doping buffer layer 108, and the anode trench gate electrode 115 is positioned in the trench.

In the technical scheme, the doping concentration of the first conductive type semiconductor doping base region 111 is adjusted to form Schottky contact with the anode metal 110, and the first conductive type semiconductor anode region 109 forms ohmic contact with the anode metal 110. When the device works, a Schottky junction formed by the anode metal 110 and the first conductive type semiconductor doping base region 111 is reversely biased, and when a conductive channel is formed by the control gate structure, current carriers passing through the channel of the control gate structure are quickly extracted to the anode metal 110 under the action of an electric field of the Schottky junction reverse bias depletion layer.

dielectric layers

113 and 114 in the present invention.

On the other hand, the invention provides an MCT device for controlling an anode by MOS, and the IGBT device is actually a lateral bipolar power semiconductor device composed of a thyristor (four-layer three-terminal device) and an MOS (insulated gate field effect transistor):

the first technical scheme is as follows:

a bipolar semiconductor power device with an MOS control anode comprises an anode structure, a drift region structure, a cathode structure and a control gate structure, wherein the anode structure, the drift region structure, the cathode structure and the control gate structure are positioned above a first conduction type semiconductor doping substrate 116; wherein the drift region structure is located on the upper surface of the first conductive type semiconductor doped substrate 216, and the drift region structure comprises a second conductive type semiconductor doped drift region 207; the anode structure is positioned on one side of the top layer of the second conductive type semiconductor doping drift region 207, and comprises a second conductive type semiconductor doping buffer layer 208, a first conductive type semiconductor anode region 209 positioned on the top layer of the second conductive type semiconductor doping buffer layer 208, and an anode metal 218 led out from the first conductive type semiconductor anode region 209; the cathode structure is positioned on the other side of the top layer of the second conductive type semiconductor doping drift region 207, and comprises a first conductive type semiconductor body region 206, a second conductive type semiconductor base region 217, a first conductive type semiconductor doping emitter region 205, a second conductive type semiconductor doping emitter region 204 and a cathode metal 201; the second conductive type semiconductor doped emitter region 204 and the second conductive type semiconductor doped base region 217 are respectively positioned at two ends of the top layer of the first conductive type semiconductor body region 206, the first conductive type semiconductor doped emitter region 205 is positioned between the second conductive type semiconductor doped emitter region 204 and the second conductive type semiconductor doped base region 217 at two ends, and the upper surfaces of the first conductive type semiconductor doped emitter region 205 and part of the second conductive type semiconductor doped emitter region 204 are contacted with the cathode metal 201; the control gate structure is positioned on the uppermost layer of the device and comprises a control gate electrode 202 and a control gate dielectric layer 203, the control gate dielectric layer 203 is positioned in a first conductive type semiconductor body region 206, a second conductive type semiconductor base region 217, a first conductive type semiconductor doping emission region 205 and a second conductive type semiconductor doping drift region 207; the control gate electrode 202 is located on the upper surface of the control gate dielectric layer 203 and contacts the second conductive type semiconductor doped emitter region 204, the first conductive type semiconductor body region 206 and the second conductive type semiconductor doped drift region 207 through the control gate dielectric layer 203; the method is characterized in that:

the anode structure further includes a second conductivity type semiconductor doped source region 212 and an anode trench gate structure; the anode structure is internally provided with a groove extending into the second conductive type semiconductor doping drift region layer 207 along the vertical direction of the device, and the second conductive type semiconductor doping source region 212 is positioned between the groove and the first conductive type semiconductor anode region 209; the anode trench gate structure includes: the first anode trench gate dielectric layer 213 and the second anode trench gate dielectric layer 214 are positioned on the inner wall of the trench, the first anode trench gate dielectric layer 213 is in contact with the second conductive type semiconductor doping source region 212 and the second conductive type semiconductor doping buffer layer 208, and the anode trench gate electrode 215 is positioned in the trench.

Further, the bipolar semiconductor power device with the MOS controlled anode of the present invention further includes a first conductive type semiconductor doping base region 211, where the first conductive type semiconductor doping base region 211 is located between the anode trench gate structure and the first conductive type semiconductor anode region 209, and is in contact with the upper surface and the side surface of the second conductive type semiconductor doping source region 212. The doping concentration of the first conductivity type semiconductor doped base region 211 is less than that of the first conductivity type semiconductor anode region 209.

Based on the scheme, the first conductive type semiconductor doping base region 211 is introduced, when the device is conducted in the forward direction, strong drift region conductance modulation is obtained through the large minority carrier injection efficiency provided by the high-concentration first conductive type semiconductor anode region 209, the conduction voltage drop is reduced, the performance of the device is not affected, the threshold voltage of the control gate structure is reduced by the low-concentration first conductive type semiconductor doping base region 211, the driving loss of the control gate structure is reduced, the switching speed of the control gate structure is improved, the resistance of a control gate structure channel is reduced, the conduction voltage drop of the device is further reduced, and a better bypass effect is achieved.

Further, the depth of the anode trench gate structure in the present invention may be greater than the junction depth of the second conductive type semiconductor doping buffer layer 208, and may also be less than the junction depth of the second conductive type semiconductor doping buffer layer 208, and may also be equal to the junction depth of the second conductive type semiconductor doping buffer layer 108.

Further, in the present invention, the thickness of the second anode trench gate dielectric layer 214 is greater than or equal to the thickness of the first anode trench gate dielectric layer 213.

Further, the thickness of the control gate dielectric layer 203 is greater than the thickness of the anode trench gate

dielectric layers

213 and 214.

Further, the width of the control gate electrode 202 is larger than the width of the anode trench gate electrode 215 in the present invention.

The second technical scheme is as follows:

the anode structure further comprises a first conductive type semiconductor doped base region 211 forming a schottky contact with the anode metal 220 and an anode trench gate structure; the anode structure is internally provided with a groove extending into the second conductive type semiconductor doping drift region layer 207 along the vertical direction of the device, and the first conductive type semiconductor doping base region 211 is positioned between the groove and the first conductive type semiconductor anode region 209; the doping concentration of the first conductive type semiconductor doping base region 211 is smaller than that of the first conductive type semiconductor anode region 209; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode 215, a first anode trench gate dielectric layer 213 and a second anode trench gate dielectric layer 214, wherein the first anode trench gate dielectric layer 213 and the second anode trench gate dielectric layer 214 are positioned on the inner wall of a trench, the first anode trench gate dielectric layer 213 is in contact with a first conductive type semiconductor doping base region 211 and a second conductive type semiconductor doping buffer layer 208, and the anode trench gate electrode 215 is positioned in the trench.

In the technical scheme, the doping concentration of the first conductive type semiconductor doping base region 211 is adjusted to form Schottky contact with the anode metal 110, and the first conductive type semiconductor anode region 209 forms ohmic contact with the anode metal 210. When the device works, a Schottky junction formed by the anode metal 210 and the first conductive type semiconductor doping base region 211 is reversely biased, and when a conductive channel is formed by the control gate structure, current carriers passing through the control gate structure channel are quickly extracted to the anode metal 210 under the action of an electric field of the Schottky junction reverse bias depletion layer.

Further, the depth of the anode trench gate structure in the present invention may be greater than the junction depth of the second conductive type semiconductor doping buffer layer 208, and may also be less than the junction depth of the second conductive type semiconductor doping buffer layer 208, and may also be equal to the junction depth of the second conductive type semiconductor doping buffer layer 108. Further, in the present invention, the thickness of the second anode trench gate dielectric layer 214 is greater than or equal to the thickness of the first anode trench gate dielectric layer 213.

dielectric layers

213 and 214.

In addition to the above two aspects, the present invention provides a method for manufacturing a bipolar semiconductor power device with a MOS controlled anode, comprising the following steps:

the first step is as follows: preparing a first conductive type semiconductor doping substrate, epitaxially growing a second conductive type semiconductor doping drift region on the first conductive type semiconductor doping substrate, and manufacturing a terminal structure of a device on the front surface of a semiconductor substrate through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;

the second step is that: manufacturing a cathode structure on the top layer on one side of the semiconductor substrate, and forming a first conductive type semiconductor body region, a second conductive type semiconductor doping base region, a first conductive type semiconductor doping emitter region and a second conductive type semiconductor doping emitter region on the top layer of the semiconductor substrate through an ion implantation process and an annealing process, or the first conductive type semiconductor body region, the second conductive type semiconductor doping base region, the first conductive type semiconductor doping emitter region and the second conductive type semiconductor doping emitter region;

the third step: forming a second conductive type semiconductor doping buffer layer of the device on the top layer on the other side of the semiconductor substrate through ion implantation of second conductive type impurities and an annealing process;

the fourth step: manufacturing a first conductive type semiconductor doping anode region of the device on the top layer of the second conductive type semiconductor doping buffer layer through ion implantation of first conductive type impurities and an annealing process;

the fifth step: etching a window on the surface of the first conductive type semiconductor doped anode region, and then etching a groove, wherein the depth of the etched groove is greater than the junction depth of the first conductive type semiconductor doped anode region;

and a sixth step: forming a dielectric layer on the side wall of the groove, and depositing and filling polycrystalline silicon in the groove;

the seventh step: etching the dielectric layer and the polysilicon formed in the trench in the ninth step by a photoetching process to obtain an anode trench gate electrode and an anode trench gate dielectric layer;

eighth step: manufacturing a first conductive type semiconductor doping base region between the first conductive type semiconductor doping anode region and the anode groove gate structure through an ion implantation and annealing process;

the ninth step: manufacturing a control gate dielectric layer on the upper surfaces of the first conductive type semiconductor body region, the second conductive type semiconductor base region, the first conductive type semiconductor doping emitter region and the second conductive type semiconductor doping drift region through deposition and etching processes;

the tenth step: manufacturing cathode metal on the upper surfaces of the first conductive type semiconductor doping emission region and the second conductive type semiconductor doping emission region; manufacturing a control gate electrode on the upper surface of the control gate dielectric layer above the second conductive type semiconductor doping emitter region, the first conductive type semiconductor body region and the second conductive type semiconductor doping drift region; and manufacturing anode metal on the upper surfaces of the first conductive type semiconductor anode region and the first conductive type semiconductor doping base region. Furthermore, the doping concentration of the first conductive type semiconductor doping base region is controlled to form Schottky contact with the anode metal, and the first conductive type semiconductor doping anode region forms ohmic contact with the anode metal.

Furthermore, the manufacturing step of the first conductive type semiconductor doping base region can be omitted, the first conductive type semiconductor doping base region is replaced by a second conductive type impurity through ion implantation, and a second conductive type semiconductor doping source region which is contacted with the anode groove gate structure is formed on the top layer of the first conductive type semiconductor doping anode region.

Further, on the basis of the above technical solution, the present invention may form the second conductive type semiconductor doped source region by continuing to implant the second conductive type impurity through the ion implantation after the first conductive type semiconductor doped base region is prepared in the eighth step.

The working principle of the invention is as follows:

on the premise of keeping the cathode structure of the traditional lateral bipolar power semiconductor device unchanged, as shown in fig. 2 and 3, the invention introduces an anode trench gate structure and a source region and/or a base region in the anode region of the device, under the condition of not influencing the normal operation and opening of the device:

1) by controlling the anode trench gate structure, the forward conduction voltage drop of the bypass anode diode is reduced, so that the effect of reducing the forward conduction voltage drop of the power semiconductor device is achieved.

When the device is conducted, the anode diode is bypassed by opening the anode MOS structure, and the forward conduction voltage drop of the device is reduced. When the forward voltage drop of the device is increased due to the disappearance of the conductance modulation effect, the anode MOS channel can be closed so that holes can be injected into the drift region again for conductance modulation. Therefore, the dynamic switching process of the anode MOS can enable the device to have a lower average value of forward conduction voltage drop than that of the device with the traditional structure.

2) After the anode diode is bypassed, minority carrier injection from the anode region to the drift region is reduced, so that the time of a reverse recovery process of the device during turn-off is shortened, and the turn-off speed of the device is improved.

When the device is turned off, the anode MOS channel is turned on in advance when the device is turned off or before the device is turned off, so that minority carriers of the anode are reduced to be holes when the N channel device is turned on, and electrons are injected when the P channel device is turned on, and therefore, the excessive minority carriers in a drift region before the semiconductor power device is turned off can be reduced, the minority carrier extraction time required by the device when the device is turned off is further reduced, and the effect of improving the turn-off speed of the device is finally achieved. By the working mode, the average forward conduction voltage drop in the dynamic switching process of the device can be smaller, and the compromise between the forward conduction voltage drop and the turn-off loss can be further improved.

However, during bypassing of the anode diode, the injection of minority carriers may be reduced and thus the conductance modulation effect may be reduced. The reduction in forward conduction voltage drop caused by the anode diode bypass is then gradually increased due to the reduced conductance modulation. Therefore, in practical use, a pulse voltage needs to be applied to the gate electrode of the anode trench to ensure that the forward on voltage of the device is maintained at a lower value than that of the conventional device. In addition, the anode diode is bypassed before the device is turned off, so that the injection amount of minority carriers can be further reduced, and the turn-off time and the turn-off loss of the device are further reduced. Therefore, the structure of the invention greatly reduces the forward conduction voltage drop and the turn-off time of the device, improves the switching speed of the device and reduces the switching loss of the device. The invention adopts the anode trench gate structure to control the opening of the anode MOS channel, reduces the influence of parasitic capacitance introduced by the trench gate on the device as much as possible, and is beneficial to reducing the threshold voltage to improve the gate driving capability and improve the switching frequency of the anode trench gate structure. The invention can further improve and reduce the threshold voltage by increasing the thickness of the bottom dielectric layer of the trench gate and reducing the thickness of the side dielectric layer, and accelerate the switching speed of the anode MOS structure, so that the anode MOS structure is easier to control. The thickness of the bottom dielectric of the trench gate can be increased while the thickness of the side dielectric can be decreased. In addition, the manufacturing method of the MOS control anode semiconductor power device does not need to add extra process steps, and is compatible with the manufacturing method of the traditional device.

Compared with the prior art, the invention has the beneficial effects that: the switching speed of the device is improved, and the switching loss of the device is reduced; the forward conduction voltage drop and the turn-off loss of the device are reduced, the carrier concentration distribution of the whole N-type drift region is improved, and the compromise between the forward conduction voltage drop and the switching loss is improved; the manufacturing method of the MOS control anode power semiconductor device does not need to add extra process steps and is compatible with the manufacturing method of the traditional device.

Drawings

Fig. 1 is a schematic diagram of a cell structure of a conventional lateral power semiconductor device.

In fig. 1, 1 is an emitter metal, 2 is a control gate electrode, 3 is a control gate dielectric, 4 is an N + emitter region, 5 is a P + emitter region, 6 is a P-type body region, 7 is an N-type drift region, 8 is an N-type buffer layer, 9 is a P-type anode region, 10 is an anode metal, and 11 is a P-type substrate.

Fig. 2 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 1.

Fig. 3 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 2.

Fig. 4 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 3.

Fig. 5 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 4.

In fig. 2 to 5, 101 is a cathode metal, 102 is a control gate electrode, 103 is a control gate dielectric, 104 is an N + emitter region, 105 is a P + emitter region, 106 is a P-type body region, 107 is an N-type drift region, 108 is an N-type buffer layer, 109 is a P-type anode region, 110 is an anode metal, 111 is a P-base region, 112 is an N + source, 113 is a first anode trench gate dielectric layer, 114 is a second anode trench gate dielectric layer, 115 is an anode trench gate electrode, and 116 is a P-type substrate.

Fig. 6 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 5.

Fig. 7 is a schematic diagram of a cell structure of the MOS-controlled anode semiconductor power device of embodiment 6.

FIG. 8 is a schematic diagram showing a cell structure of a MOS-controlled anode semiconductor power device of example 7.

FIG. 9 is a schematic diagram of a cell structure of a MOS-controlled anode semiconductor power device of embodiment 8.

In fig. 6 to 9, 201 is an emitter metal, 202 is a control gate electrode, 203 is a control gate dielectric, 204 is an N + emitter region, 205 is a P + emitter region, 206 is a P-body region, 207 is an N-drift region, 208 is an N-buffer layer, 209 is a P-anode region, 210 is an anode metal, 211 is a P-base region, 212 is an N + source, 213 is a first anode trench gate dielectric layer, 214 is a second anode trench gate dielectric layer, 215 is an anode trench gate electrode, 216 is a P-type substrate, and 217 is an N-base region.

FIG. 10 is a schematic diagram of the device structure after the anode trench filling oxide layer and the polysilicon gate electrode are formed by etching in the manufacturing method of the present invention.

FIG. 11 is a schematic structural diagram of a device after a P-base region, an N-type buffer layer, and a P-base region are formed after ion implantation in the manufacturing method of the present invention.

Fig. 12 is a schematic structural diagram of a device after a P + emitter region, an N + emitter region, and an N + source region are formed after ion implantation in the manufacturing method of the present invention.

Fig. 13 is a schematic diagram of the theoretical forward conduction voltage drop of the lateral semiconductor power device with MOS controlled anode provided by the present invention.

Detailed Description

The present invention is described in detail below with reference to the drawings and specific embodiments, in order to realize and clarify the principle and characteristics of the present invention, which are expected to be realized by those skilled in the art:

example 1:

the present embodiment provides an IGBT device with a MOS-controlled anode, and a cell structure of the IGBT device is shown in fig. 2, and includes an anode structure, a drift region structure, a cathode structure, and a control gate structure, which are located above a P + substrate 116; the drift region structure is located on the upper surface of the P + substrate 116, and the drift region structure includes an N-type drift region 107; the anode structure is positioned on one side of the top layer of the N-type drift region 107, and comprises an N-type buffer layer 108, a P-type anode region 109 positioned on the top layer of the N-type buffer layer 108, and an anode metal 118 led out from the P-type anode region 109; the cathode structure is positioned on the other side of the top layer of the N-type drift region 107, and comprises a P-type body region 106, a P + emission region 105, an N + emission region 104 and cathode metal 101; the P type body region 106 is positioned on the top layer of the N type drift region 107, the N + emission region 104 is positioned on one side, close to the anode structure, of the top layer of the P type body region 106, the P + emission region 105 is positioned on one side, far away from the anode structure, of the top layer of the P type body region 106, and the P + emission region 105 and the N + emission region 104 are in contact with each other and the upper surface of the P + emission region 105 and the upper surface of the N + emission region; the control gate structure is arranged on the uppermost layer of the device and comprises a control gate electrode 102 and a control gate dielectric layer 103, the control gate electrode 102 is in contact with an N + emitting region 104 and a P-type body region 106 through the control gate dielectric layer 103, and the thickness of the control field oxide layer 103 is about

The method is characterized in that:

the anode structure further comprises a P-base region 111, an N + source region 112 and an anode trench gate structure; the inside of the anode structure is provided with a groove extending into the N-type drift region 107 along the vertical direction of the device, and the lower surface of the groove is positioned below the lower surface of the N-type buffer layer 108; the P-base region 111 is positioned between the anode trench gate structure and the P-type anode region 109, and the doping concentration of the P-base region 111 is smaller than that of the P-type anode region 209; the N + source region 112 is positioned at the top layer of the P-base region 111 and is in contact with the anode trench gate structure; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode 115, a first anode trench gate dielectric layer 113 and a second anode trench gate dielectric layer 114, wherein the first anode trench gate dielectric layer 113 is located on the side wall of a trench, the second anode trench gate dielectric layer 114 is located on the bottom wall of the trench, the first anode trench gate dielectric layer 113 is in contact with an N + source region 112 and an N-type buffer layer 108, and the second anode trench gate dielectric layer 114 and the anode trench gate electrode 115 are located in the trench.

Example 2:

in this embodiment, a cell structure of an IGBT device with a MOS controlled anode is shown in fig. 3, and unlike embodiment 1, a thickness of the second anode trench gate dielectric layer 114 in the anode trench gate structure is greater than a thickness of the first anode trench gate dielectric layer 113, specifically, the thickness of the first anode trench gate dielectric layer 113 is about the same

The thickness of the second anode trench gate dielectric layer 114 is about

The purpose of this design is: the starting voltage of the anode trench gate is controlled, and meanwhile, the parasitic capacitance of the anode trench gate electrode is reduced, so that the adverse effect of the parasitic parameters of the anode MOS structure on the parameters of the IGBT device is reduced.

Example 3:

the present embodiment provides an IGBT device with a MOS-controlled anode, and the cell structure of the IGBT device is as shown in fig. 4, which is different from embodiment 1 in that: the N + source region 112 in the anode MOS structure is removed and changed to the P-base region 111. Because the concentration of the P-base region 111 is lower than that of the P-type anode region 109, when the device works, the channel inversion of the side surface of the anode trench gate is controlled, so that the effect of bypassing the anode diode is achieved, at this time, the P-type anode region 109 and the anode metal 110 form ohmic contact, and the P-base region 111 and the anode metal 110 form schottky contact.

When the device works, a Schottky junction formed by the anode metal 110 and the P-base region 111 is reversely biased, and when a control gate structure forms a conductive channel, carriers passing through the control gate structure channel are rapidly extracted to the anode metal 110 under the action of an electric field of the Schottky junction reverse bias depletion layer. This embodiment can achieve the same effects as embodiment 1, but the process and structure are simpler.

Example 4:

the present embodiment provides an IGBT device with a MOS-controlled anode, and the cell structure of the IGBT device is as shown in fig. 5, which is different from embodiment 1 in that: the lower surface of the anode trench gate structure is located above the lower surface of the N-type buffer layer 108. The purpose of the design is to prevent the depletion layer of the junction formed by the P-type substrate 116/the N-type drift region 107 from expanding to the bottom of the trench gate when the device is subjected to reverse voltage resistance, so that the oxide layer at the bottom of the trench gate is broken down, and the voltage resistance of the device is reduced.

Example 5:

the embodiment provides an MCT device with MOS controlled anode, whose cell structure is shown in fig. 6, and includes an anode structure, a drift region structure, a cathode structure, and a control gate structure over a P + substrate 116; the drift region structure is located on the upper surface of the P + substrate 216, and the drift region structure comprises an N-type drift region 207; the anode structure is positioned on one side of the top layer of the N-type drift region 207 and comprises an N + buffer layer 208, a P-type anode region 209 positioned on the top layer of the N + buffer layer 208 and an anode metal 218 led out from the P-type anode region 209; the cathode structure is positioned on the other side of the top layer of the N-type drift region 207 and comprises a P-type body region 206, an N-base region 217, a P + emitter region 205, an N + emitter region 204 and cathode metal 201; a P-type body region 206 is located on the top layer of the N-type drift region 207; n-base region 217 is located on top of P-type body region 206; the top layer of the N-base region 217 is provided with a P + emitter region 205 and an N + emitter region 204 which are independent from each other, wherein the P + emitter region 205 is close to one side of the anode structure; the upper surfaces of the P + emitter region 205 and the N + emitter region 204 have a cathode metal; the control gate structure is positioned on the uppermost layer of the device and comprises a control gate electrode 202 and a control gate dielectric layer 203, wherein the control gate dielectric layer 203 is positioned in a P-type body region 206, an N-base region 217, a P + emitter region 205 and an N-type drift region 207; the control gate electrode 202 is positioned on the upper surface of the control gate dielectric layer 203 and is in contact with the N + emitter region 204, the P-type body region 206 and the N-type drift region 207 through the control gate dielectric layer 203; the method is characterized in that:

the anode structure further comprises a P-base region 211, an N + source region 212 and an anode trench gate structure; the inside of the anode structure is provided with a groove extending into the N-type drift region 207 along the vertical direction of the device, and the lower surface of the groove is positioned below the lower surface of the N + buffer layer 208; the P-base region 211 is located between the anode trench gate structure and the P-type anode region 209, and the doping concentration of the P-base region 211 is smaller than that of the P-type anode region 209; the N + source region 212 is positioned at the top layer of the P-base region 211 and is in contact with the anode trench gate structure; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode 215, a first anode trench gate dielectric layer 213 and a second anode trench gate dielectric layer 214, wherein the first anode trench gate dielectric layer 213 is positioned on the side wall of the trench, the second anode trench gate dielectric layer 214 is positioned on the bottom wall of the trench, the first anode trench gate dielectric layer 213 is in contact with an N + source region 212 and an N + buffer layer 208, and the second anode trench gate dielectric layer 214 and the anode trench gate electrode 215 are positioned in the trench.

Example 6:

the present embodiment provides an IGBT device with a MOS-controlled anode, and the unit cell structure of the IGBT device is as shown in fig. 7, and unlike embodiment 5, the thickness of the second anode trench gate dielectric layer 214 in the anode trench gate structure is greater than the thickness of the first anode trench gate dielectric layer 213. The purpose of this design is: the starting voltage of the anode trench gate is controlled, and meanwhile, the parasitic capacitance of the anode trench gate electrode is reduced, so that the adverse effect of the parasitic parameters of the anode MOS structure on the parameters of the IGBT device is reduced.

Example 7:

the present embodiment provides an IGBT device with a MOS-controlled anode, and the cell structure thereof is as shown in fig. 8, which is different from embodiment 5 in that: the N + source region 212 in the anode MOS structure is removed and changed to a P-base region 211. Because the concentration of the P-base region 211 is lower than that of the P-type anode region 209, when the device works, the channel inversion of the side surface of the anode trench gate is controlled, so that the effect of bypassing the anode diode is achieved, at this time, the P-type anode region 209 forms ohmic contact with the anode metal 220, and the P-base region 211 forms schottky contact with the anode metal 220.

When the device works, a Schottky junction formed by the anode metal 210 and the P-base region 211 is reversely biased, and when a control gate structure forms a conductive channel, carriers passing through the control gate structure channel are rapidly extracted to the anode metal 210 under the action of an electric field of the Schottky junction reverse bias depletion layer. This embodiment can achieve the same effects as embodiment 5, but the process and structure are simpler.

Example 8:

the present embodiment provides an IGBT device with a MOS-controlled anode, and the cell structure thereof is as shown in fig. 9, which is different from embodiment 1 in that: the lower surface of the anode trench gate structure is located above the lower surface of the N-type buffer layer 208. The purpose of the design is to prevent the depletion layer of the junction formed by the P-type substrate 216/the N-type drift region 207 from expanding to the bottom of the trench gate when the device is under reverse voltage resistance, so that the oxide layer at the bottom of the trench gate is broken down, and the voltage resistance of the device is reduced.

Example 9:

the specific implementation of the preparation method provided in this example is illustrated by taking an IGBT device with a voltage class of 600V as an example, and fig. 10 to 12 show schematic diagrams of key process steps, and the specific preparation method is as follows:

the first step is as follows: selecting a P-type heavily-doped monocrystalline silicon wafer as a P-type substrate of the device, wherein the thickness of the selected silicon wafer is 100-200 mu m;

the second step is that: epitaxially growing an N-type semiconductor layer as an N-type drift region 9 on a P-type substrate at a temperature of 1100 ℃, the thickness of the grown semiconductor layer being about 100 μm;

the third step: a terminal structure of a device is manufactured on the front surface of the silicon wafer through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the N-type drift region 9;

the fourth step: the N-type buffer layer of the device is manufactured by ion implantation of N-type impurities and annealing, the thickness of the formed N-type buffer layer is 15-30 mu m, wherein the ion implantation energy is 1500 keV-2000 keV, and the implantation dosage is 10 keV¹³～10¹⁴Per cm²The annealing temperature is 1200-1250 ℃, and the annealing time is 300-600 minutes;

the fifth step: forming a P-type anode region 5 by ion implantation of P-type impurities, wherein the P-type anode region 5 is positioned on the lower surface of the N-type electric field stop layer 7, the implantation energy is 40-60 keV, and the implantation dosage is 10 keV¹²～10¹³Performing back annealing at 2/cm in a mixed atmosphere of H2 and N2 at 400-450 ℃ for 20-30 minutes;

and a sixth step: depositing a TEOS layer with the thickness of 700-1000 nm on the surface of a silicon wafer, performing trench silicon etching after photoetching a window, and etching a trench, wherein the depth of the trench exceeds that of the N-type buffer layer; after the groove etching is finished, rinsing TEOS on the surface through HF solution;

the seventh step: forming an oxide layer on the side wall of the trench at 1050-1150 ℃ under the atmosphere of O2; then depositing and filling polycrystalline silicon in the groove at 750-950 ℃;

eighth step: etching the oxide layer and the polysilicon formed in the trench in the seventh step by adopting a photoetching process to obtain an anode trench gate electrode and an anode trench gate dielectric layer;

the ninth step: photoetching, namely manufacturing an N + source region and an N + emitter region of a device by implanting N-type impurities into ions, wherein the energy of the ion implantation is 30-60 keV, and the implantation dosage is 10¹⁵～10¹⁶Pieces/cm 2; the N + source region is positioned in the P-base region and is in contact with the anode trench gate;

the tenth step: photoetching, implanting P-type impurities by ions, and annealing to prepare a P + emission region of the device, wherein the energy of the ion implantation is 60-80 keV, and the implantation dosage is 10¹⁵～10¹⁶2 pieces/cm, the annealing temperature is 900 ℃, and the time is 20-30 minutes; the P + emission region and the N + emission region are arranged on the top layer of the P-type body region in parallel;

the eleventh step: forming a control gate dielectric layer on the upper surfaces of the P-type body region, the N-base region, the P + emitter region and the N-type drift region through deposition and etching processes;

the twelfth step: through metal deposition, photoetching and etching, emitter metal is formed on the upper surfaces of the N + emitter region and the P + emitter region, anode metal is formed on the upper surfaces of the P-type anode region and the P-base region, and a control gate electrode is formed on the upper surfaces of the control gate dielectric layers above the N + emitter region, the P-type body region and the N-type drift region.

Further, on the basis of the embodiment, the manufacturing step of the P-base region can be omitted; the manufacturing step of the N + source region can be omitted, and the first conductive type semiconductor doping base region is adjusted in doping concentration to form Schottky contact with the anode metal.

It should be noted that the bipolar semiconductor power device of the MOS control anode of the present invention can be made of not only Si, but also SiC, GaAs, or GaN semiconductor materials.

FIG. 13 is a schematic diagram of the theoretical forward conduction voltage drop of the MOS control anode trench gate charge storage type IGBT provided by the present invention, where t₁The IGBT conducting state in the time period is the same as the traditional structure, t₂And the back anode trench gate of the IGBT is conducted in the time period. As can be seen from the figure, through the voltage control of the anode trench gate, the influence of the back PN junction on the device conduction characteristic can be shielded in the time period t2 when the back anode trench gate is conducted, so that the average forward conduction voltage drop of the device is lower than that of the conventional structure.

While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A bipolar semiconductor power device with a transverse MOS control anode comprises an anode structure, a drift region structure, a cathode structure and a control gate structure, wherein the anode structure, the drift region structure, the cathode structure and the control gate structure are positioned above a first conductive type semiconductor doping substrate; wherein: the drift region structure is positioned on the upper surface of the first conduction type semiconductor doped substrate and comprises a second conduction type semiconductor doped drift region; the anode structure is positioned on one side of the top layer of the second conductive type semiconductor doping drift region and comprises a second conductive type semiconductor doping buffer layer, a first conductive type semiconductor anode region positioned on the top layer of the second conductive type semiconductor doping buffer layer and anode metal led out from the first conductive type semiconductor anode region; the cathode structure is positioned on the other side of the top layer of the second conductive type semiconductor doping drift region; the control grid structure is positioned on the uppermost layer of the device and comprises a control grid electrode and a control grid dielectric layer, the control grid dielectric layer is positioned on the cathode structure and the upper surface of the second conductive type semiconductor doping drift region, and the control grid electrode is positioned on the upper surface of the control grid dielectric layer above the cathode structure; the method is characterized in that:

the anode structure further comprises a second conductive type semiconductor doped source region and an anode trench gate structure; the anode structure is internally provided with a groove which extends into the second conductive type semiconductor doping drift region layer along the vertical direction of the device, and the second conductive type semiconductor doping source region is positioned between the groove and the first conductive type semiconductor anode region; the anode trench gate structure includes: the first anode trench gate dielectric layer and the second anode trench gate dielectric layer are positioned on the inner wall of the trench, the first anode trench gate dielectric layer is contacted with the second conductive type semiconductor doped source electrode region and the second conductive type semiconductor doped buffer layer, and the anode trench gate electrode is positioned in the trench;

the thickness of the control gate dielectric layer is greater than that of the anode trench gate dielectric layer, and the thickness of the second anode trench gate dielectric layer is greater than or equal to that of the first anode trench gate dielectric layer.

2. The bipolar semiconductor power device with lateral MOS controlled anode of claim 1 wherein: the bipolar semiconductor power device of the MOS control anode further comprises a first conductive type semiconductor doping base region, wherein the first conductive type semiconductor doping base region is located between the groove and the first conductive type semiconductor anode region and is in contact with the upper surface and the side face of the second conductive type semiconductor doping source region.

3. A bipolar semiconductor power device with a transverse MOS control anode comprises an anode structure, a drift region structure, a cathode structure and a control gate structure, wherein the anode structure, the drift region structure, the cathode structure and the control gate structure are positioned above a first conductive type semiconductor doping substrate; wherein: the drift region structure is positioned on the upper surface of the first conduction type semiconductor doped substrate and comprises a second conduction type semiconductor doped drift region; the anode structure is positioned on one side of the top layer of the second conductive type semiconductor doping drift region and comprises a second conductive type semiconductor doping buffer layer, a first conductive type semiconductor anode region positioned on the top layer of the second conductive type semiconductor doping buffer layer and anode metal led out from the first conductive type semiconductor anode region; the cathode structure is positioned on the other side of the top layer of the second conductive type semiconductor doping drift region; the control grid structure is positioned on the uppermost layer of the device and comprises a control grid electrode and a control grid dielectric layer, the control grid dielectric layer is positioned on the cathode structure and the upper surface of the second conductive type semiconductor doping drift region, and the control grid electrode is positioned on the upper surface of the control grid dielectric layer above the cathode structure; the method is characterized in that:

the bipolar semiconductor power device of the MOS control anode further comprises a first conductive type semiconductor doping base region and an anode trench gate structure which form Schottky contact with anode metal; the anode structure is internally provided with a groove extending into the second conductive type semiconductor doping drift region layer along the vertical direction of the device, and the first conductive type semiconductor doping base region is positioned between the groove and the first conductive type semiconductor anode region; the doping concentration of the first conductive type semiconductor doping base region is smaller than that of the first conductive type semiconductor anode region; the anode trench gate structure includes: the trench gate structure comprises an anode trench gate electrode, a first anode trench gate dielectric layer and a second anode trench gate dielectric layer, wherein the first anode trench gate dielectric layer and the second anode trench gate dielectric layer are positioned on the inner wall of a trench, the first anode trench gate dielectric layer is contacted with a first conductive type semiconductor doping base region and a second conductive type semiconductor doping buffer layer, and the anode trench gate electrode is positioned in the trench;

4. A lateral MOS controlled anode bipolar semiconductor power device according to any of claims 1-3, wherein: the cathode structure is a first conductive type semiconductor body region (106), a first conductive type semiconductor doped emitter region (105), a second conductive type semiconductor doped emitter region (104) and a cathode metal (101); the first conduction type semiconductor doping emission region (105) and the second conduction type semiconductor doping emission region (104) are independent from each other and are positioned on the top layer of the first conduction type semiconductor body region (106), wherein the second conduction type semiconductor doping emission region (104) is close to one side of the anode structure; the upper surfaces of the first conductive type semiconductor doping emission region (105) and the second conductive type semiconductor doping emission region (104) are contacted with the cathode metal (101) to form the IGBT device.

5. A lateral MOS controlled anode bipolar semiconductor power device according to any of claims 1-3, wherein: the cathode structure comprises a first conductive type semiconductor body (206), a second conductive type semiconductor doping base region (217), a first conductive type semiconductor doping emitter region (205), a second conductive type semiconductor doping emitter region (204) and cathode metal (201); the second conductive type semiconductor doped emitter region (204) and the second conductive type semiconductor doped base region (217) are respectively located at two ends of the top layer of the first conductive type semiconductor body region (206), the first conductive type semiconductor doped emitter region (205) is located between the second conductive type semiconductor doped emitter region (204) and the second conductive type semiconductor doped base region (217) at two ends, and the upper surfaces of the first conductive type semiconductor doped emitter region (205) and a part of the second conductive type semiconductor doped emitter region (204) are in contact with the cathode metal (201) to form the MCT device.

6. A lateral MOS controlled anode bipolar semiconductor power device according to any of claims 1-3, wherein: the bipolar semiconductor power device of the MOS control anode is made of semiconductor materials of Si, SiC, GaAs or GaN.

7. A lateral MOS controlled anode bipolar semiconductor power device according to any of claims 1-3, wherein: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor.

8. A preparation method of a bipolar semiconductor power device with a transverse MOS control anode is characterized by comprising the following steps:

the second step is that: manufacturing a cathode structure on the top layer of one side of the semiconductor substrate, forming a first conductive type semiconductor body region, a second conductive type semiconductor doping base region, a first conductive type semiconductor doping emitter region and a second conductive type semiconductor doping emitter region on the top layer of the semiconductor substrate through an ion implantation process and an annealing process;

the tenth step: manufacturing cathode metal on the upper surfaces of the first conductive type semiconductor doping emission region and the second conductive type semiconductor doping emission region; manufacturing a control gate electrode on the upper surface of the control gate dielectric layer above the second conductive type semiconductor doping emitter region, the first conductive type semiconductor body region and the second conductive type semiconductor doping drift region; and manufacturing anode metal on the upper surfaces of the first conductive type semiconductor anode region and the first conductive type semiconductor doping base region.

9. The method of claim 8, wherein the method comprises the steps of: omitting the manufacturing step of the first conductive type semiconductor doping base region, replacing the first conductive type semiconductor doping base region with a second conductive type impurity through ion implantation, and forming a second conductive type semiconductor doping source electrode region which is contacted with the anode groove grid structure on the top layer of the first conductive type semiconductor doping anode region; or after the first conductive type semiconductor doping base region is manufactured in the eighth step, second conductive type impurities are continuously injected through ions to form a second conductive type semiconductor doping source region.