CN117334740A - SiC SGT MOSFET with reverse freewheel channel and preparation method - Google Patents
SiC SGT MOSFET with reverse freewheel channel and preparation method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention provides a SiC SGT MOSFET with a reverse freewheel channel and a preparation method, wherein the SiC SGT MOSFET comprises: the first P+ region, the second P+ region, the first N+ region and the P-type region; the first P+ region, the first N+ region and the P-type region are positioned below the first split gate and are sequentially adjacent; the second P+ region is positioned below the first P+ region, the first N+ region and the P-type region and is adjacent to the first P+ region, the first N+ region and the P-type region. When the source electrode is connected with high potential, the split gate S induces an inversion layer in the P-type region, a conductive channel from the N-drift layer to the first N+ region and then to the source electrode is formed, so that the current-following effect is achieved, the path has smaller starting voltage during the reverse conduction period, and the reliability of the SiC SGT MOSFET is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC SGT MOSFET with a reverse freewheel channel and a preparation method thereof.
Background
Compared with the first generation semiconductor material represented by silicon and the second generation semiconductor material represented by gallium arsenide, the third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturated electron migration rate, stable physicochemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. SiC MOSFETs are silicon carbide devices that have long been fully commercialized. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. Silicon carbide is more conveniently formed into silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. Therefore, the silicon carbide is considered as an important development direction of a new generation of high-efficiency power electronic devices, and has wide application prospect in the fields of new energy automobiles, rail transit, locomotive traction, smart grids and the like.
Compared with a planar power device, a Trench MOSFET (Trench metal oxide semiconductor field effect transistor) has a gate formed in a vertical Trench, so that more integrated units can be obtained per unit area, more channels are provided, the on-resistance of the device can be greatly reduced, the body junction depth is reduced by reducing the body junction depth to reduce the channel length, the body junction depth is reduced by reducing the channel length, the reverse leakage performance of the device is affected, the turn-off loss of the device is increased by increasing the reverse leakage, and the reliability of the device is affected.
In practical application, the SiCTrench MOSFET is usually integrated with the SBD or JFET in anti-parallel, so that the reverse freewheeling effect can be achieved, but the manufacturing process is more complex, the reliability problem is easy to be caused, the chip area is increased, and the current industrial requirements cannot be met. In order to reduce the size of transistor devices, reduce on-resistance, reduce dynamic loss, improve the power saving characteristics and improve the cost performance of transistors, a new structure of SiC SGT MOSFET is currently needed to accommodate the new demands on transistor devices in the market.
Disclosure of Invention
The invention aims to provide a SiC SGT MOSFET with a reverse freewheeling channel and a preparation method, wherein the SiC SGT MOSFET is provided with the reverse freewheeling channel positioned below a trench gate, when a source electrode is connected with high potential, a split gate S induces an inversion layer in a P-type region, a conductive channel from an N-drift layer to a first N+ region to the source electrode is formed, the freewheeling function is achieved, the path has smaller starting voltage during reverse conduction, and the reliability of the SiC SGT MOSFET is improved.
A SiC SGT MOSFET having a reverse freewheel channel, comprising: the first P+ region, the second P+ region, the first N+ region and the P-type region;
the first P+ region, the first N+ region and the P-type region are positioned below the first split gate and are sequentially adjacent;
the second P+ region is positioned below the first P+ region, the first N+ region and the P-type region and is adjacent to the first P+ region, the first N+ region and the P-type region.
Preferably, the first P+ region has a doping concentration in the range of 10 18 -10 19 cm -3 。
Preferably, the doping concentration of the P-type region is 10 17 cm -3 。
Preferably, the first N+ region has a doping concentration in the range of 10 19 cm -3 。
Preferably, the thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall.
Preferably, the doping concentration of the second p+ region is smaller than the doping concentration of the first p+ region.
Preferably, the doping concentration of the second p+ region is greater than the doping concentration of the P-type region.
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a third P+ region, a second N+ region and a P-well layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the third P+ region and the second N+ region;
the third p+ region and the second n+ region are located under the source electrode;
the gate and the split gate are located in a trench.
Preferably, the method further comprises: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a p+ layer;
the second split gate is coated by the second oxide layer;
the second oxide layer is coated by the P+ layer;
the P+ layer is adjacent to the second N+ region, the P-well layer, and the N-drift layer.
A method of fabricating a SiC SGT MOSFET having a reverse freewheel channel, comprising:
doping the upper layer of the N-drift layer to form a first P+ region, a second P+ region, a first N+ region and a P-type region;
forming a P-well layer, a third P+ region and a second N+ region in an epitaxial manner above the N-drift layer, the first P+ region, the first N+ region and the P-type region;
a through hole is formed in the P-well layer region and the second N+ region, a groove is formed in the upper layer of the N-drift layer, and the through hole is connected with the groove;
depositing split gates in the trenches and then filling oxide;
depositing a gate over the oxide, refilling the oxide;
and depositing a source electrode and a drain electrode.
According to the invention, the reverse freewheeling channel is arranged below the trench gate, the opening of the reverse freewheeling channel is controlled through the split gate, when the source electrode is connected with zero potential or negative potential, a conductive electron channel is not formed in the region below the source split gate S, the high-resistance characteristic is realized, when the source electrode is connected with positive potential in a reverse conduction mode, the source split gate S induces an inversion layer in a P-type region, a conductive channel from an N-drift layer to a first N+ region and then from the split gate short-circuited with the source electrode to the source electrode is formed, the reverse freewheeling effect is realized, and the path has smaller opening voltage in the reverse conduction period, so that the reverse freewheeling capability of the SiC VDMOS is improved, and compared with the prior art, the method of antiparallel integration of the SiC MOSFET and the SBD or JFET, the method has the advantages of small chip area, high reliability, low manufacturing cost and small turn-off loss.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a SiC SGT MOSFET structure of the present invention;
FIG. 2 is a schematic diagram of a process flow for manufacturing a SiC SGT MOSFET of the present invention;
FIG. 3 is a schematic diagram of a process flow structure for manufacturing a SiC SGT MOSFET of the present invention;
fig. 4 is a schematic diagram of DT structure of the SiC SGT MOSFET of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
As a switching device, a reverse freewheeling diode is often required in a circuit due to oscillations or voltage spikes, avoiding degradation of the device. There are now mainly the following approaches for using freewheeling diodes: diodes are connected in parallel in the circuit, but this can lead to the circuit adding additional switched capacitance and gate charge degradation, increasing the energy loss of the whole circuit; and when the device is packaged, the freewheeling diode and the MOSFET are made into a set of facilities, so that the area utilization rate of the chip is reduced, and meanwhile, the use reliability of the device is reduced due to extra current leakage of the device caused by integration of a plurality of systems. The parasitic body diode of the switching element is utilized as a freewheeling diode when the reverse voltage is applied, but for the traditional SiC MOSFET, the use of the body diode brings about some characteristics: firstly, the threshold voltage of the self diode of the SiC MOSFET is higher and is about 3V, so that the extra energy consumption of the circuit is improved, and the energy utilization rate is reduced; secondly, the conduction of the body diode can lead to bipolar degradation of the device, and the bipolar degradation is caused by the fact that the defects in the SiC material are increased due to the recombination of electron hole pairs, the doped region drifts, so that various leakage current amounts of the permanent MOSFET are increased, and permanent damage failure is finally formed. In addition, in the process of applying charges to the grid electrode to turn on the power MOSFET device, the grid-drain capacitance (Miller capacitance) between the input and the output exists, the capacitor is charged firstly in the driving process of the grid electrode, and then the device is turned on, so that the device has a long-time platform voltage in the turning-on process, the switching energy loss of the device is increased, and the use of the device is influenced very negatively.
According to the invention, the opening of the reverse freewheeling channel is controlled through the first split grid electrode under the trench grid, when the source electrode is connected with zero potential or negative potential, a conductive electron channel is not formed in the area under the first split grid electrode S, the reverse freewheeling channel has high resistance, when the source electrode is connected with positive potential and is reversely conducted, the first split grid electrode S induces a reverse layer in a P-type area, a conductive channel from an N-drift layer to a first N+ area and then from the split grid electrode which is in short circuit with the source electrode to the source electrode is formed, the reverse freewheeling function is achieved, and the path has smaller opening voltage in the reverse conduction period, so that the reverse freewheeling capability of the SiC VDMOS is improved, and compared with the prior art, the method of antiparallel integration of the SiC MOSFET and the SBD or JFET, the reverse freewheeling channel has the advantages of small chip area, high reliability, low manufacturing cost and small turn-off loss.
Example 1
A SiC SGT MOSFET with reverse freewheel channel, referring to fig. 1, comprising: the first P+ region, the second P+ region, the first N+ region and the P-type region;
the first P+ region, the first N+ region and the P-type region are positioned below the split gate and are sequentially adjacent;
MOSFETs are widely used as an important component in integrated circuits in a variety of applications including power supplies, load driving, and the like. The neck region resistance of a conventional planar MOSFET is present, so that the channel resistance is a relatively large proportion. The VDMOSFET adopting the trench gate structure can increase the channel density of the device and reduce the specific on-resistance of the device, but the electric performance of the device is affected because a large gate-drain overlap capacitance exists between the gate region in the trench and the drain on the back of the substrate. The invention provides a groove type split gate structure, which is designed along the vertical direction, and the grid-drain capacitance between the grid electrode and the drain electrode is shielded by the shielding grid positioned below the control grid, so that the grid-drain overlap capacitance is effectively reduced.
The first P+ region and the second P+ region play a role in shielding an electric field when being taken as a whole, and because electric field aggregation easily occurs at the corner below the groove, the electric field intensity at the corner below the groove is higher, and the position of the grid oxide layer at the corner below the groove can be protected from breakdown by arranging the first P+ region and the second P+ region, so that the reliability of the SiC SGT MOSFET is improved. When the source electrode is connected with high potential, the split grid electrode S can induce an inversion layer near the P-type region, a conductive channel is formed from the N-drift layer to the first N+ region and then from the split grid electrode short-circuited with the source electrode to the source electrode, and the reverse freewheeling effect is achieved.
The second P+ region is positioned below the first P+ region, the first N+ region and the P-type region and is adjacent to the first P+ region, the first N+ region and the P-type region.
In the embodiment of the invention, the doping concentration of the P-type region can influence the starting voltage of the reverse freewheeling channel, when the doping concentration of the P-type region is increased, the starting voltage of the reverse freewheeling channel can be increased, when the doping concentration of the P-type region is reduced, the starting voltage of the reverse freewheeling channel can be reduced, the reliability of the gate oxide layer can be reduced, and the breakdown problem of one side of the gate oxide layer can be easily caused, so the invention has the advantages that the first P+ region, the first N+ region and the P-type region are positioned below the first split gate and are sequentially adjacent; the second P+ region is positioned below the first P+ region, the first N+ region and the P-type region and is adjacent to the first P+ region, the first N+ region and the P-type region, and the doping concentrations of the first P+ region, the second P+ region, the P-type region and the first N+ region are adjusted, so that the reliability of the SiC SGT MOSFET can be improved, the reverse freewheeling capacity of the SiC SGT MOSFET can be enhanced, the chip area can be reduced, the manufacturing cost can be reduced, and the turn-off loss can be reduced.
Preferably, the first P+ region has a doping concentration in the range of 10 18 -10 19 cm -3 。
The first P+ region is heavily doped with ion concentration of 10 18 -10 19 cm -3 Because electric field concentration is easy to occur at the corner below the groove, the field intensity is increased, and the problem that gate oxidation is broken down is easy to occur, the first P+ region is arranged, and can be effectively exhausted with the N-Drift layer to reduce the electric field peak value, so that the effect of protecting the gate oxide layer is achieved. Too low a concentration of the first p+ region results in insufficient depletion effect on the N-drift layer and failure to protect the gate oxide layer, too high a concentration of the first p+ region increases parasitic resistance and increases power loss of the device, so the doping concentration range of the first p+ region is set to 10 18 -10 19 cm -3 . As a preferred embodiment, the doping concentration range of the first P+ region is set to 10 19 cm -3 It is possible to have reduced parasitic resistance while protecting the gate oxide layer.
Preferably, the doping concentration of the P-type region is 10 17 cm -3 。
The P-type region is lightly doped, the ion concentration of the doping is similar to that of the P-well layer, if the doping concentration of the P-type region is too high, the first split gate can cause more difficulty in inducing an inversion layer, the starting voltage of the reverse freewheeling channel is increased, so that the doping concentration of the P-type region needs to be lightly doped, and if the doping concentration of the P-type region is too low, the gate oxide layer cannot be protected from breakdown, therefore, as a preferred embodiment, the invention sets the doping concentration of the P-type region to 10 17 cm -3 Therefore, when the SiC SGT MOSFET is reversely conducted, the first split gate can more easily induce an inversion layer in the P-type region to form a conducting channel from the N-drift layer to the first N+ region and then from the split gate short-circuited with the source electrode to the source electrode, the conducting channel can be ensured to have smaller starting voltage in a reverse conducting device, the reverse follow current capability of the SiC SGT MOSFET is improved, the voltage withstand capability of a gate oxide layer can be improved, the gate oxide layer is protected from being broken down, the reliability of the SiC SGT MOSFET is improved, and compared with a method for integrating the SiC SGT MOSFET and the SBD or JFET in an anti-parallel mode in the prior art, the SiC SGT MOSFET has the advantages of small chip area and low manufacturing cost.
Preferably, the first N+ region has a doping concentration in the range of 10 19 cm -3 。
The first N+ region is heavily doped, N-type doped with VA group element, and is formed by nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and neodymium (Mc), and As a preferred embodiment, the doping concentration range of the first N+ region is set to 10 19 cm -3 . The N-type heavy doping can improve the reverse voltage withstand capability.
Preferably, the thickness of the first oxide layer between the split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall.
The thickness of the first oxide layer between the first split gate and the trench wall affects the ease of forming an inversion layer on the P-type layer on the side of the first split gate. An inversion layer is a layer of semiconductor material that under certain conditions, the type of majority carriers changes under certain conditions. In a typical MOS device, the inversion layer forms a conductive channel, which is responsible for the conduction of the device. Because the source electrode and the first split gate electrode are connected together, when the source electrode is connected with high potential, a thin layer, namely an inversion layer, is formed on the P-type layer near the wall surface of the groove where the first split gate electrode is close under the action of positive source electrode voltage. The inversion layer may form a conductive channel such that current may flow from the source to the first n+ region, from the first n+ region to the N-drift layer, from the N-drift layer to the N-type substrate, and finally to the drain.
The larger the thickness of the first oxide layer between the first split gate and the trench wall surface is, the higher the turn-on voltage of the reverse freewheeling channel is, because the thickness of the first oxide layer between the first split gate and the trench wall surface is increased, the more difficult the inversion layer is induced in the P-type layer, the smaller the thickness of the first oxide layer between the first split gate and the trench wall surface is, although the turn-on voltage of the reverse freewheeling channel is reduced, the strength of the electric field borne by the first oxide layer on one side of the first split gate is correspondingly increased, the problem of breakdown of the gate oxide layer is caused, and therefore the thickness of the first oxide layer between the first split gate and the trench wall surface is set to be 15-25nm. In order to balance the turn-on voltage of the reverse freewheel channel of the SiC SGT MOSFET and the withstand voltage performance of the gate oxide, the thickness of the first oxide layer between the first split gate and the trench wall is set to 20nm as a preferred embodiment of the present invention.
Preferably, the doping concentration of the second p+ region is smaller than the doping concentration of the first p+ region.
Preferably, the doping concentration of the second p+ region is greater than the doping concentration of the P-type region.
The doping concentration of the second P+ region is set to be smaller than the doping concentration of the first P+ region and larger than the doping concentration of the P-type region, and the doping concentration of the second P+ region can be set to be equal to the doping concentration of the first P+ region. And during chip manufacturing, forming a second P+ region by ion implantation at the upper layer of the N-drift layer, and then forming a first P+ region, a first N+ region and a P-type region by ion implantation above the second P+ region.
The concentration and the thickness of the second P+ region are smaller, the on-resistance is smaller, the doping concentration of the second P+ region is smaller than that of the first P+ region, the power loss of the device can be reduced, and the doping concentration of the second P+ region is larger than that of the P-type region, so that the leakage of the device can be prevented.
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a third P+ region, a second N+ region and a P-well layer;
the drain electrode is positioned below the N-type substrate;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
The N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the third P+ region and the second N+ region;
the third P+ region and the second N+ region are positioned below the source electrode;
the gate and split gate are located in the trench.
The source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
Preferably, the method further comprises: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a p+ layer;
the second split gate is coated by a second oxide layer;
the second oxide layer is coated by the P+ layer;
the P+ layer is adjacent to the second N+ region, the P-well layer, and the N-drift layer.
Unlike fig. 1, in the SiC SGT MOSFET of the DT structure, in the present structure, a plurality of second split gates are present, and since the second split gates are connected to the source, the effect thereof is equivalent to that of the source, and can function as a modulation gate voltage, better control of the MOSFET can be achieved.
Example 2
A method of fabricating a SiC SGT MOSFET having a reverse freewheel channel, as shown in fig. 2,3, comprising:
s100, doping the upper layer of the N-drift layer to form a first P+ region, a second P+ region, a first N+ region and a P-type region;
the invention adopts an ion implantation mode to dope the upper layer of the N-drift layer to form a first P+ region, a second P+ region, a first N+ region and a P-type region. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). Various ion implantation beam line designs include a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S200, epitaxially forming a P-well layer, a third P+ region and a second N+ region above the N-drift layer, the first P+ region, the first N+ region and the P-type region;
the specific step of S200 is divided into two steps, wherein in the first step, an N-drift layer is formed above the N-drift layer, the first P+ region, the first N+ region and the P-type region in an epitaxial manner, and in the second step, a P-well layer, a third P+ region and a second N+ region are formed on the N-drift layer by ion implantation.
Epitaxy is one of the semiconductor processes, which refers to a process of growing a fully aligned single crystal layer on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. The epitaxial growth modes can be classified into solid phase epitaxy, liquid phase epitaxy and vapor phase epitaxy according to the different phases of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During the implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, and amorphization occurs to form a surface amorphous silicon layer; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S300, forming through holes in the P-well layer region and the second N+ region, forming grooves in the upper layer of the N-drift layer, and connecting the through holes with the grooves;
etching is a technique that uses chemical reactions or physical impact to remove portions of material. Etching techniques can be classified into wet etching and dry etching. After exposure plate making and development, the protective film of the area to be etched is removed, and the protective film is contacted with a chemical solution during etching, so that the effect of dissolution and corrosion is achieved, and the effects of concave-convex or hollowed-out molding are formed.
The method comprises the following specific steps: exposure method: the engineering is to open the size of the prepared material according to the graph, prepare the material, clean the material, dry the material, paste the film or coat, dry the film, expose the light, develop, dry the film, etch and take off the film.
Screen printing method: cutting, cleaning a plate (stainless steel or other metal material), screen printing, etching and demoulding.
Etching: the anti-corrosion ink is printed on the surface of the material by adopting an ink-jet printing technology, and then the anti-corrosion layer can be obtained after curing (generally photo-curing and also useful thermal curing) and then the next chemical corrosion or electric corrosion can be carried out.
S400, depositing split gates in the trenches and then filling oxide;
the wet oxidation method is adopted to generate an oxide layer, the thickness of the generated oxide layer is precisely controlled, and even if the thickness of the generated oxide layer is about 20nm, the wet oxidation is carried out under the conditions of high temperature (120-320 ℃) and high pressure (0.5-20 MPa), gaseous oxygen (usually air) is used as an oxidant, so that organic matters in water are oxidized into small molecular organic matters or inorganic matters. The high temperature can improve the solubility of O2 in the liquid phase, and the purpose of the high pressure is to inhibit the evaporation of water to maintain the liquid phase, while the water in the liquid phase can act as a catalyst to allow the oxidation reaction to proceed at a lower temperature.
Polysilicon deposition is the formation of gate electrodes and local interconnects on a silicide stack on a first layer of polysilicon (Poly 1) and a second layer of polysilicon (Poly 2) forms contact plugs between source/drain and cell interconnects. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) that can be performed in situ by directly introducing a dopant gas of arsenic trioxide (AH 3), phosphorus trioxide (PH 3) or diborane (B2H 6) into a silicon material gas of silane or DCS in a reaction chamber (i.e., in a furnace tube)A deposited (LPCVD) polysilicon doping process. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes areBetween/min, mainly determined by the temperature at the time of deposition.
S500, depositing a grid electrode on the oxide, and refilling the oxide;
s600, depositing a source electrode and a drain electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
According to the invention, the reverse freewheeling channel is arranged below the trench gate, the opening of the reverse freewheeling channel is controlled through the split gate, when the source electrode is connected with zero potential or negative potential, a conductive electron channel is not formed in the region below the source split gate S, the high-resistance characteristic is realized, when the source electrode is connected with positive potential in a reverse conduction mode, the source split gate S induces an inversion layer in the P-type layer, a conductive channel from the N-drift layer to the first N+ region and then from the split gate short-circuited with the source electrode to the source electrode is formed, the reverse freewheeling effect is realized, and the path has smaller opening voltage in the reverse conduction period, so that the reverse freewheeling capability of the SiC VDMOS is improved, and compared with the prior art, the method of antiparallel integration of the SiC MOSFET and the SBD or JFET has the advantages of small chip area, high reliability, low manufacturing cost and small turn-off loss.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A SiC SGT MOSFET having a reverse freewheel channel, comprising: the first P+ region, the second P+ region, the first N+ region and the P-type region;
the first P+ region, the first N+ region and the P-type region are positioned below the first split gate and are sequentially adjacent;
the second P+ region is positioned below the first P+ region, the first N+ region and the P-type region and is adjacent to the first P+ region, the first N+ region and the P-type region.
2. A SiC SGT MOSFET with reverse freewheel channel according to claim 1,characterized in that the doping concentration range of the first P+ region is 10 18 -10 19 cm -3 。
3. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized in that the doping concentration of said P-type region is 10 17 cm -3 。
4. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized in that the doping concentration of said first n+ region is in the range of 10 19 cm -3 。
5. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized in that the thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of said first oxide layer between the gate and the trench wall.
6. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized in that the doping concentration of said second p+ region is smaller than the doping concentration of said first p+ region.
7. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized in that the doping concentration of said second p+ region is larger than the doping concentration of the P-type region.
8. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized by further comprising: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a third P+ region, a second N+ region and a P-well layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the third P+ region and the second N+ region;
the third p+ region and the second n+ region are located under the source electrode;
the gate and the split gate are located in a trench.
9. A SiC SGT MOSFET having a reverse freewheel channel according to claim 1 characterized by further comprising: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a p+ layer;
the second split gate is coated by the second oxide layer;
the second oxide layer is coated by the P+ layer;
the P+ layer is adjacent to the second N+ region, the P-well layer, and the N-drift layer.
10. A method of fabricating a SiC SGT MOSFET having a reverse freewheel channel, comprising:
doping the upper layer of the N-drift layer to form a first P+ region, a second P+ region, a first N+ region and a P-type region;
forming a P-well layer, a third P+ region and a second N+ region in an epitaxial manner above the N-drift layer, the first P+ region, the first N+ region and the P-type region;
a through hole is formed in the P-well layer and the second N+ region, a groove is formed in the upper layer of the N-drift layer, and the through hole is connected with the groove;
depositing split gates in the trenches and then filling oxide;
depositing a gate over the oxide, refilling the oxide;
and depositing a source electrode and a drain electrode.
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