CN117080252A - Horizontal split gate SiC VMOS with different gate oxidation thicknesses and preparation method - Google Patents

Horizontal split gate SiC VMOS with different gate oxidation thicknesses and preparation method Download PDF

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CN117080252A
CN117080252A CN202311015851.9A CN202311015851A CN117080252A CN 117080252 A CN117080252 A CN 117080252A CN 202311015851 A CN202311015851 A CN 202311015851A CN 117080252 A CN117080252 A CN 117080252A
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oxide
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split gate
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乔凯
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention provides a horizontal split gate SiC VMOS with different gate oxidation thicknesses and a preparation method thereof, wherein the SiC VMOS comprises the following components: a first oxide layer, a gate electrode and a first split gate electrode; the first oxide layer wraps the grid electrode and the first split grid electrode; the first N+ layer and the P-well layer are provided with through holes; forming a groove on the upper layer of the N-drift layer; the groove is connected with the through hole; the gate and the first split gate are located in the trench; the thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall. The trench gate in the invention is composed of a common gate G for controlling the opening of a channel and a split gate S for controlling a reverse freewheeling channel, when the source electrode is connected with positive potential and is conducted reversely, the split gate S of the source electrode induces an inversion layer in the P-well layer to form a conductive channel, thereby improving the reverse freewheeling capacity of the device.

Description

Horizontal split gate SiC VMOS with different gate oxidation thicknesses and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a horizontal split gate SiC VMOS with different gate oxidation thicknesses and a preparation method thereof.
Background
Compared with the first generation semiconductor material represented by silicon and the second generation semiconductor material represented by gallium arsenide, the third generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, high saturated electron migration rate, stable physicochemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. SiC MOSFETs are silicon carbide devices that have long been fully commercialized. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. Silicon carbide is more conveniently formed into silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. Therefore, the silicon carbide is considered as an important development direction of a new generation of high-efficiency power electronic devices, and has wide application prospect in the fields of new energy automobiles, rail transit, locomotive traction, smart grids and the like.
Trench MOSFETs (Trench MOSFETs) were developed based on VDMOS (vertical double-diffused metal oxide semiconductor field effect transistors). Compared with a planar power device, a Trench MOSFET is formed in a vertical groove, so that more integrated units can be obtained in unit area, more channels are provided, the on-resistance of the device can be greatly reduced, the body junction depth is reduced by reducing the channel length, the reverse leakage performance of the device is affected, the turn-off loss of the device is increased when the reverse leakage is increased, and the reliability of the device is affected.
In practical application, the SiCTrench MOSFET is usually integrated with the SBD or JFET in anti-parallel, so that the reverse freewheeling effect can be achieved, but the manufacturing process is more complex, the reliability problem is easy to be caused, the chip area is increased, and the current industrial requirements cannot be met. In order to reduce the size of the transistor device, reduce on-resistance, reduce dynamic loss, improve the power saving characteristics and improve the cost performance of the transistor, a novel structure of VDMOS is needed to adapt to the new requirements of the transistor device in the market.
Disclosure of Invention
The invention aims to provide a horizontal split gate SiC VMOS with different gate oxidation thicknesses and a preparation method thereof, wherein a trench gate in the SiC VMOS consists of a common gate G for controlling the opening of a channel and a split gate S for controlling a reverse freewheeling channel, when a source electrode is connected with 0 potential or negative potential, pwell at one side of the source split gate S does not form a channel, the silicon nitride semiconductor device has high resistance, and when the source electrode is connected with positive potential and is reversely conducted, the source split gate S induces an inversion layer in a P-well layer to form a conductive channel, so that the reverse freewheeling capacity of the device is improved.
A horizontal split gate SiC VMOS having different gate oxide thicknesses, comprising: a first oxide layer, a gate electrode and a first split gate electrode;
the first oxide layer wraps the grid electrode and the first split grid electrode;
the first N+ layer and the P-well layer are provided with through holes;
forming a groove on the upper layer of the N-drift layer;
the groove is connected with the through hole;
the gate and the first split gate are located in the trench;
the thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall.
Preferably, the thickness of the first oxide layer between the first split gate and the trench wall is 15-25nm.
Preferably, the thickness of the first oxide layer between the gate electrode and the trench wall is 45-55nm.
Preferably, the method further comprises: a source electrode, a drain electrode, an N-type substrate and a first P+ layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well;
the P-well layer is positioned below the first P+ layer and the first N+ layer;
the first P+ layer and the first N+ layer are located below the source electrode;
the source electrode is connected with the split gate electrode.
Preferably, the method further comprises: a P+ shielding layer;
the P+ shielding layer is located below the groove.
Preferably, the method further comprises: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a second p+ layer;
the second split gate is coated by the second oxide layer;
the second oxide layer is coated by the second P+ layer;
the second P+ layer is adjacent to the first N+ layer, the P-well layer, and the N-drift layer.
Preferably, the method further comprises: a third p+ layer, a fourth p+ layer, a second n+ layer, and a third n+ layer;
the third p+ layer includes a first end with the second n+ layer sidewall, a second end between the trench and the N-drift layer, and a body between the second n+ layer and the N-drift layer;
the fourth P+ layer is adjacent to the third N+ layer, the P-well layer and the N-drift layer;
the second n+ layer is located between the first split gate and a first end of the third p+ layer;
the third n+ layer is located between the gate and the fourth p+ layer.
A preparation method of a horizontal split gate SiC VMOS with different gate oxidation thicknesses comprises the following steps:
doping the upper layer of the N-drift layer to form a P-well layer, a first P+ layer and a first N+ layer;
etching a through hole on the P-well layer and the first N+ layer, and etching a groove on the upper layer of the N-drift layer, wherein the groove is connected with the through hole;
depositing oxide and polysilicon in the trench;
etching the polysilicon and backfilling the oxide in the trench;
and secondarily depositing the polysilicon, and depositing a source electrode and a drain electrode.
Preferably, depositing oxide and polysilicon in the trench comprises: a gate oxide having a thickness of 15-25nm is deposited in the trench.
Preferably, backfilling the oxide in the trench comprises: and backfilling the oxide with the thickness of 20-40nm in the groove.
According to the invention, the thickness of the first oxide layer between the first split gate and the groove wall surface is designed to be smaller than that of the first oxide layer between the gate and the groove wall surface, so that when the source electrode of the SiC VDMOS is connected with zero potential or negative potential and the drain electrode is connected with high potential, the P-well layer on one side of the split gate S connected with the source electrode does not form a channel, the P-well layer has high resistance, when the source electrode of the SiC VDMOS is connected with positive potential and the drain electrode is connected with zero potential or negative potential in reverse conduction, the split gate S connected with the source electrode can induce an inversion layer on the P-well layer, a conducting channel from the N-drift layer to the first N+ layer to the source electrode is formed, the conducting channel has a smaller starting voltage during reverse conduction, and therefore the reverse freewheeling capability of the SiC VDMOS is improved, and compared with the prior art, the method of integrating the SiC MOSFET with the SBD or the JFET in reverse parallel connection, the SiC MOSFET has the advantages of small chip area, high reliability, low manufacturing cost and small turn-off loss.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of the SiC VMOS structure of the present invention;
FIG. 2 is a schematic diagram of a process flow of SiC VMOS preparation of the present invention;
FIG. 3 is a schematic diagram of a preparation flow structure of the SiC VMOS of the present invention;
FIG. 4 is a schematic diagram of a SiC VMOS structure with a P+ shield layer of the present invention;
FIG. 5 is a schematic DT structure of the SiC VMOS of the present invention;
fig. 6 is a schematic diagram of a half-packet structure of the SiC VMOS of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
As a switching device, a reverse freewheeling diode is often required in a circuit due to oscillations or voltage spikes, avoiding degradation of the device. There are now mainly the following approaches for using freewheeling diodes: diodes are connected in parallel in the circuit, but this can lead to the circuit adding additional switched capacitance and gate charge degradation, increasing the energy loss of the whole circuit; and when the device is packaged, the freewheeling diode and the MOSFET are made into a set of facilities, so that the area utilization rate of the chip is reduced, and meanwhile, the use reliability of the device is reduced due to extra current leakage of the device caused by integration of a plurality of systems. The parasitic body diode of the switching element is utilized as a freewheeling diode when the reverse voltage is applied, but for the traditional SiC MOSFET, the use of the body diode brings about some characteristics: firstly, the threshold voltage of the self diode of the SiC MOSFET is higher and is about 3V, so that the extra energy consumption of the circuit is improved, and the energy utilization rate is reduced; secondly, the conduction of the body diode can lead to bipolar degradation of the device, and the bipolar degradation is caused by the fact that the defects in the SiC material are increased due to the recombination of electron hole pairs, the doped region drifts, so that various leakage current amounts of the permanent MOSFET are increased, and permanent damage failure is finally formed. In addition, in the process of applying charges to the grid electrode to turn on the power MOSFET device, the grid-drain capacitance (Miller capacitance) between the input and the output exists, the capacitor is charged firstly in the driving process of the grid electrode, and then the device is turned on, so that the device has a long-time platform voltage in the turning-on process, the switching energy loss of the device is increased, and the use of the device is affected very adversely.
According to the invention, the thickness of the first oxide layer between the first split gate and the groove wall surface is designed to be smaller than that of the first oxide layer between the gate and the groove wall surface, so that when the source electrode of the SiC VDMOS is connected with zero potential or negative potential and the drain electrode is connected with high potential, the P-well layer on one side of the split gate S connected with the source electrode does not form a channel, the P-well layer has high resistance, when the source electrode of the SiC VDMOS is connected with positive potential and the drain electrode is connected with zero potential or negative potential in reverse conduction, the split gate S connected with the source electrode can induce an inversion layer on the P-well layer, a conducting channel from the N-drift layer to the first N+ layer to the source electrode is formed, the conducting channel has a smaller starting voltage during reverse conduction, and therefore the reverse freewheeling capability of the SiC VDMOS is improved, and compared with the prior art, the method of integrating the SiC MOSFET with the SBD or the JFET in reverse parallel connection, the SiC MOSFET has the advantages of small chip area, high reliability, low manufacturing cost and small turn-off loss.
Example 1
A horizontal split gate SiC VMOS having different gate oxide thicknesses, referring to fig. 1, comprising: a first oxide layer, a gate electrode and a first split gate electrode;
MOSFET devices are widely used as an important component in integrated circuits in a variety of applications such as power supplies, load driving, and the like. Conventional planar VDMOSFETs (vertical double diffused metal oxide semiconductor field effect transistors) have a neck region resistance, which results in a large proportion of the channel resistance. The VDMOSFET adopting the trench gate structure can increase the channel density of the device and reduce the specific on-resistance of the device, but the electric performance of the device is affected because a large gate-drain overlap capacitance exists between the gate region in the trench and the drain on the back of the substrate. The invention provides a groove type split gate structure, which is designed along the horizontal direction, and the grid-drain capacitance between the grid electrode and the drain electrode is shielded by the shielding grid positioned on the right side of the control grid, so that the grid-drain overlap capacitance is effectively reduced.
The first oxide layer wraps the grid electrode and the first split grid electrode;
as shown in fig. 1, the dielectric between the gate and the first split gate is an oxide layer, and both the gate and the first split gate are surrounded by an oxide layer.
The first N+ layer and the P-well layer are provided with through holes;
forming a groove on the upper layer of the N-drift layer;
the groove is connected with the through hole;
the grid electrode and the first split grid electrode are positioned in the groove;
after the N+ layer and the P-well layer are formed, a through hole is formed in the N+ layer and the P-well layer, the N+ layer and the P-well layer are disconnected by the through hole and are divided into a left part and a right part, after the through hole is formed, a groove is formed in the upper layer of the N-drift layer, the through hole in the N+ layer and the P-well layer is connected with the groove, the width of the through hole is equal to that of the groove, in the manufacturing process, the groove is etched in the N+ layer and continuously etched downwards until the upper layer of the N-drift layer is etched, finally, the through hole is formed in the N+ layer and the P-well layer, the groove is formed in the upper layer of the N-drift layer, and the through hole is connected with the groove.
The thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall.
In the embodiment of the invention, the thickness of the first oxide layer between the first split gate and the groove wall surface is set smaller than that of the oxide layer between the split gate and the groove wall surface in the prior art, so that when the MOSFET SOURCE electrode is connected with high potential, an inversion layer is induced in the P-well layer, a conductive channel from N-drift to N+ SOURCE is formed, the follow current function is realized, and the path has smaller starting voltage during the reverse conduction.
Preferably, the thickness of the first oxide layer between the first split gate and the trench wall is 15-25nm.
Thickness t of first oxide layer between first split gate and trench wall sox The ease of forming an inversion layer on the P-well on the side of the split gate is affected. An inversion layer is a layer of semiconductor material that under certain conditions, the type of majority carriers changes under certain conditions. In a typical MOS device, the inversion layer forms a conductive channel, which is responsible for the conduction of the device. Because the source electrode and the split gate electrode are connected together, when the source electrode is connected with high potential, a thin layer, namely an inversion layer, is formed on the P-well layer near the wall surface of the groove where the first split gate electrode is close to under the action of positive source electrode voltage. The inversion layer may form a conductive channel, so that current can flow from the source to the first n+ layer, then from the first n+ layer to the N-drift layer, and finally to the drain after flowing from the N-drift layer to the N-type substrate.
Thickness t of first oxide layer between first split gate and trench wall sox The larger the turn-on voltage of the reverse freewheel channelThe higher is the thickness t of the first oxide layer between the first split gate and the trench wall sox The thickness t of the first oxide layer between the first split gate and the trench wall surface is increased to make it more difficult to induce an inversion layer in the P-well layer sox The smaller the opening voltage of the reverse freewheeling channel is, the higher the electric field intensity born by the first oxide layer at the side of the second split gate is, the reliability of the device is affected, and the breakdown of the gate oxide layer is caused, so the thickness of the first oxide layer between the first split gate and the wall surface of the trench is set to 15-25nm. In order to balance the turn-on voltage of the reverse freewheel channel of the SiC VDMOS and the withstand voltage performance of the gate oxide, as a preferred embodiment, the present invention sets the thickness of the first oxide layer between the first split gate and the trench wall to 20nm.
Preferably, the thickness of the first oxide layer between the gate and the trench wall is 45-55nm.
The gate oxide is a dielectric layer separating the gate terminal of the MOSFET from the underlying source and drain terminals and the conductive channels connecting the source and drain when the transistor is on. The gate oxide layer is a thin silicon dioxide insulating layer formed by thermally oxidizing the silicon of the channel. The insulating silicon dioxide layer is formed by a self-limiting oxidation process followed by deposition of a conductive gate material over the gate oxide to form the transistor. The gate oxide acts as a dielectric layer so the gate can withstand a lateral electric field of up to 1 to 5MV/cm to modulate the conductance of the channel.
The performance of SiC VDMOS depends on the thickness of the gate oxide. The reduction of the thickness of the gate oxide layer enhances the current driving capability of the SiC VDMOS and improves the speed and power characteristics. Thus, reducing the gate oxide thickness in process shrink may effectively improve transistor performance, however, thin oxide layers exacerbate the current tunneling effect and reduce oxide reliability. The thickness of the first oxide layer between the gate and the trench wall is set to 45-55nm in order to balance the current drive capability of the SiC VDMOS and the reliability of the oxide layer. As a preferred embodiment, the present invention sets the thickness of the first oxide layer located between the gate electrode and the trench wall to 50nm, which can improve the stability of the device while improving the operation efficiency of the SiC VDMOS.
Preferably, the method further comprises: a source electrode, a drain electrode, an N-type substrate and a first P+ layer;
the drain electrode is positioned below the N-type substrate;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
The N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well;
the P-well layer is positioned below the first P+ layer and the first N+ layer;
the first P+ layer and the first N+ layer are positioned below the source electrode;
the source is connected to the split gate.
The source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
Preferably, referring to fig. 4, further comprising: a P+ shielding layer;
the P+ shielding layer is located below the trench.
Because the electric field intensity at the corner below the VMOS groove is far higher than that at other positions, the problem that the oxide layer breaks down in advance easily occurs, so that a P+ shielding layer is introduced below the groove and can be effectively exhausted with the N-Drift layer to reduce the electric field peak value, thereby protecting the oxide layer from breakdown.
Preferably, referring to fig. 5, further comprising: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a second p+ layer;
the second split gate is coated by a second oxide layer;
the second oxide layer is coated by a second P+ layer;
the second P+ layer is adjacent to the first N+ layer, the P-well layer, and the N-drift layer.
Fig. 5 shows a SiC VMOS of a DT structure, unlike fig. 1, in which a plurality of second split gates are present, and since the second split gates are connected to the source, the effect thereof corresponds to the effect of the source, and the effect of modulating the gate voltage can be achieved, and the control of the MOSFET can be better achieved.
Preferably, referring to fig. 6, further comprising: a third p+ layer, a fourth p+ layer, a second n+ layer, and a third n+ layer;
the third P+ layer comprises a first end part which is connected with the side wall of the second N+ layer, a second end part which is positioned between the groove and the N-drift layer, and a body which is positioned between the second N+ layer and the N-drift layer;
the fourth P+ layer is adjacent to the third N+ layer, the P-well layer and the N-drift layer;
the second N+ layer is positioned between the first split gate and the first end part of the third P+ layer;
the third n+ layer is located between the gate and the fourth p+ layer.
Fig. 6 shows a SiC VMOS with a half-package structure, and the third p+ layer is used to cover the oxide layer on the first split gate and the trench wall, so that the thinner oxide layer can be better protected from breakdown, and the reliability of the SiC VMOS is improved while the reverse freewheel channel is generated.
Example 2
A method of fabricating a horizontal split gate SiC VMOS having different gate oxide thicknesses, referring to fig. 2,3, comprising:
s100, doping the upper layer of the N-drift layer to form a P-well layer, a first P+ layer and a first N+ layer;
the invention adopts an ion implantation mode to dope the upper layer of the N-drift layer to form a P-well layer, a first P+ layer and a first N+ layer. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material to form an N-BAL layer (N-type bottom auxiliary layer). Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). Various ion implantation beam line designs include a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for a p-type dopant and an electron may be created for an n-type dopant. The conductivity of the semiconductor near the doped region is changed, often to adjust the threshold of the diode.
S200, etching through holes on the P-well layer and the first N+ layer, etching grooves on the upper layer of the N-drift layer, and connecting the grooves with the through holes;
etching is a technique that uses chemical reactions or physical impact to remove portions of material. Etching techniques can be classified into wet etching and dry etching. After exposure plate making and development, the protective film of the area to be etched is removed, and the protective film is contacted with a chemical solution during etching, so that the effect of dissolution and corrosion is achieved, and the effects of concave-convex or hollowed-out molding are formed.
The method comprises the following specific steps: exposure method: the engineering is to open the size of the prepared material according to the graph, prepare the material, clean the material, dry the material, paste the film or coat, dry the film, expose the light, develop, dry the film, etch and take off the film.
Screen printing method: cutting, cleaning a plate (stainless steel or other metal material), screen printing, etching and demoulding.
Etching: the anti-corrosion ink is printed on the surface of the material by adopting an ink-jet printing technology, and then the anti-corrosion layer can be obtained after curing (generally photo-curing and also useful thermal curing) and then the next chemical corrosion or electric corrosion can be carried out.
S300, depositing oxide and polysilicon in the groove;
the wet oxidation method is adopted to generate an oxide layer, the thickness of the generated oxide layer is precisely controlled, and even if the thickness of the generated oxide layer is about 20nm, the wet oxidation is carried out under the conditions of high temperature (120-320 ℃) and high pressure (0.5-20 MPa), gaseous oxygen (usually air) is used as an oxidant, so that organic matters in water are oxidized into small molecular organic matters or inorganic matters. The high temperature can improve the solubility of O2 in the liquid phase, and the purpose of the high pressure is to inhibit the evaporation of water to maintain the liquid phase, while the water in the liquid phase can act as a catalyst to allow the oxidation reaction to proceed at a lower temperature.
Polysilicon deposition is the formation of gate electrodes and local interconnects on a silicide stack on a first layer of polysilicon (Poly 1) and a second layer of polysilicon (Poly 2) forms contact plugs between source/drain and cell interconnects. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing onThe doping gas of arsine (AH 3), phosphorus hydride (PH 3) or diborane (B2H 6) is directly input into the silicon material gas of silane or DCS in the reaction chamber (namely in a furnace tube), so that the polysilicon doping process of in-situ low-pressure chemical vapor deposition (LPCVD) can be carried out. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes areIs mainly determined by the temperature during deposition.
S400, etching the polysilicon, and backfilling oxide in the groove;
etching is a technique that uses chemical reactions or physical impact to remove portions of material. Etching techniques can be classified into wet etching and dry etching. After exposure plate making and development, the protective film of the area to be etched is removed, and the protective film is contacted with a chemical solution during etching, so that the effect of dissolution and corrosion is achieved, and the effects of concave-convex or hollowed-out molding are formed.
After the polysilicon is etched, the second wet oxidation is carried out to form an oxide layer between the grid electrode and the split grid electrode and also form an oxide layer between the grid electrode and the wall surface of the groove, and the oxidation rate of the oxide layer between the grid electrode and the split grid electrode is higher than that of the oxide layer between the grid electrode and the wall surface of the groove because the oxidation rate of the oxide layer on the surface of the polysilicon is higher than that of the oxide layer on the surface of SiC, and the thickness of the oxide layer generated by the second wet oxidation is strictly controlled, namely, the thickness of the oxide layer between the grid electrode and the wall surface of the groove is controlled to be about 50 nm.
S500, polysilicon is deposited secondarily, and a source electrode and a drain electrode are deposited.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
Preferably, depositing oxide and polysilicon in the trench comprises: a gate oxide is deposited in the trench to a thickness of 15-25nm.
Preferably, backfilling the oxide in the trench comprises: and backfilling oxide with the thickness of 20-40nm in the groove.
Wet oxidation has two main steps: mass transfer of oxygen in air from the gas phase to the liquid phase; chemical reaction between dissolved oxygen and the substrate. If the mass transfer process affects the overall reaction rate, it can be eliminated by enhancing agitation. In the embodiment of the invention, the rate of forming the oxide layer by wet oxygen oxidation can be controlled by controlling the temperature, the pressure and the concentration of the reaction gas during the wet oxygen oxidation, thereby achieving the purpose of controlling the thickness of the oxide layer. In the practical production process, the reaction temperature is easiest to control, and as a preferable embodiment, in the invention, the reaction rate of the wet oxygen oxidation is reduced by reducing the temperature of the wet oxygen oxidation reaction, so that the production rate of the oxide layer is slowed down, and the thickness of the oxide layer can be better observed at the moment, thereby achieving the aim of accurately controlling the thickness of the oxide layer. A thin oxide layer (about 20 nm) is firstly generated on the wall surface of the groove, then polysilicon is deposited, then polysilicon is etched, at the moment, a first split gate is formed, then secondary wet oxygen oxidation is carried out, the thickness of the oxide layer between the control gate and the wall surface of the groove is about 50nm, the gate is deposited after the oxide layer is formed, and the structure that the thickness of the first oxide layer between the first split gate and the wall surface of the groove is smaller than that between the gate and the wall surface of the groove is achieved, so that when the SiC MOSFET is conducted reversely, a conductive channel can be induced by the P-well layer near the first split gate, and a reverse follow current loop is formed.
According to the invention, the thickness of the first oxide layer between the first split gate and the groove wall is designed to be smaller than that of the first oxide layer between the gate and the groove wall, so that when the source electrode of the SiC VDMOS is connected with zero potential or negative potential and the drain electrode is connected with high potential, a P-well layer at one side of the split gate S connected with the source electrode does not form a channel, the split gate S connected with the source electrode has high resistance, when the source electrode of the SiC VDMOS is connected with positive potential and the drain electrode is connected with zero potential or negative potential in reverse conduction, the split gate S connected with the source electrode can induce an inversion layer in the P-well layer, a conductive channel from the N-drift layer to the first N+ layer to the source electrode is formed, the reverse freewheeling effect is achieved, and the conductive channel has smaller starting voltage during the reverse conduction period, so that the reverse freewheeling capacity of the SiC VDMOS is improved, and compared with the prior art, the method of reversely integrating the SiC MOSFET with the SBD or the JFET in parallel, the reverse freewheeling effect is small in chip area, the reliability, low manufacturing cost and small turn-off loss.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A horizontal split gate SiC VMOS having different gate oxide thicknesses, comprising: a first oxide layer, a gate electrode and a first split gate electrode;
the first oxide layer wraps the grid electrode and the first split grid electrode;
the first N+ layer and the P-well layer are provided with through holes;
forming a groove on the upper layer of the N-drift layer;
the groove is connected with the through hole;
the gate and the first split gate are located in the trench;
the thickness of the first oxide layer between the first split gate and the trench wall is smaller than the thickness of the first oxide layer between the gate and the trench wall.
2. A horizontal split gate SiC VMOS having different gate oxide thicknesses as claimed in claim 1, wherein the thickness of the first oxide layer between the first split gate and the trench wall is 15-25nm.
3. A horizontal split gate SiC VMOS having different gate oxide thicknesses as in claim 1, wherein the thickness of the first oxide layer between the gate and trench walls is 45-55nm.
4. A horizontal split gate SiC VMOS having different gate oxide thicknesses as recited in claim 1, further comprising: a source electrode, a drain electrode, an N-type substrate and a first P+ layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well;
the P-well layer is positioned below the first P+ layer and the first N+ layer;
the first P+ layer and the first N+ layer are located below the source electrode;
the source electrode is connected with the split gate electrode.
5. A horizontal split gate SiC VMOS having different gate oxide thicknesses as recited in claim 1, further comprising: a P+ shielding layer;
the P+ shielding layer is located below the groove.
6. A horizontal split gate SiC VMOS having different gate oxide thicknesses as recited in claim 1, further comprising: a plurality of second split gates extending from the source to the N-drift layer, a second oxide layer, and a second p+ layer;
the second split gate is coated by the second oxide layer;
the second oxide layer is coated by the second P+ layer;
the second P+ layer is adjacent to the first N+ layer, the P-well layer, and the N-drift layer.
7. A horizontal split gate SiC VMOS having different gate oxide thicknesses as recited in claim 1, further comprising: a third p+ layer, a fourth p+ layer, a second n+ layer, and a third n+ layer;
the third p+ layer includes a first end with the second n+ layer sidewall, a second end between the trench and the N-drift layer, and a body between the second n+ layer and the N-drift layer;
the fourth P+ layer is adjacent to the third N+ layer, the P-well layer and the N-drift layer;
the second n+ layer is located between the first split gate and a first end of the third p+ layer;
the third n+ layer is located between the gate and the fourth p+ layer.
8. The preparation method of the horizontal split gate SiC VMOS with different gate oxidation thicknesses is characterized by comprising the following steps:
doping the upper layer of the N-drift layer to form a P-well layer, a first P+ layer and a first N+ layer;
etching a through hole on the P-well layer and the first N+ layer, and etching a groove on the upper layer of the N-drift layer, wherein the groove is connected with the through hole;
depositing oxide and polysilicon in the trench;
etching the polysilicon and backfilling the oxide in the trench;
and secondarily depositing the polysilicon, and depositing a source electrode and a drain electrode.
9. The method of preparing a horizontal split gate SiC VMOS having different gate oxide thicknesses of claim 8, wherein depositing oxide and polysilicon in the trench comprises: a gate oxide having a thickness of 15-25nm is deposited in the trench.
10. The method of preparing a horizontal split gate SiC VMOS having different gate oxide thicknesses of claim 8, wherein backfilling the oxide in the trench comprises: and backfilling the oxide with the thickness of 20-40nm in the groove.
CN202311015851.9A 2023-08-11 2023-08-11 Horizontal split gate SiC VMOS with different gate oxidation thicknesses and preparation method Pending CN117080252A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118571942A (en) * 2024-07-31 2024-08-30 珠海格力电子元器件有限公司 Trench MOSFET device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118571942A (en) * 2024-07-31 2024-08-30 珠海格力电子元器件有限公司 Trench MOSFET device and preparation method thereof

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