CN116779681A - SIC MOSFET with unipolar electronic channel and preparation method - Google Patents

SIC MOSFET with unipolar electronic channel and preparation method Download PDF

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CN116779681A
CN116779681A CN202310603787.XA CN202310603787A CN116779681A CN 116779681 A CN116779681 A CN 116779681A CN 202310603787 A CN202310603787 A CN 202310603787A CN 116779681 A CN116779681 A CN 116779681A
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layer
sic mosfet
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乔凯
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

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Abstract

The invention provides a SIC MOSFET with a unipolar electronic channel and a preparation method, wherein the SIC MOSFET comprises the following components: an N-layer region; the N-Drift layer is etched with a groove; the side wall of the groove is doped with an N-layer region; the N-Drift layer is doped with a P-well region, the first P-well region is located on the side of the N-layer region, and the P-well region is connected with the N-layer region. The invention can reduce the complexity of circuit design, realizes reverse follow current by designing a simple monopole electronic channel, and reduces the production cost.

Description

SIC MOSFET with unipolar electronic channel and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SIC MOSFET with a unipolar electronic channel and a preparation method thereof.
Background
The SiC material is a typical representation of a third generation wide bandgap semiconductor material, and can meet the requirements of next generation power electronic equipment on higher power, smaller volume and more severe operation of power devices due to the advantages of higher critical breakdown electric field intensity, higher carrier saturation drift speed, higher heat conductivity, high operating frequency, stable operation under high temperature conditions and the like, and is gradually applied to the fields of power electronic systems of electric automobiles, solar power generation, train traction equipment and high-voltage direct current transmission equipment. Compared with the traditional silicon power device, the power consumption of the SiC power module which is practically used at present can be reduced by more than 50%, so that a cooling system is reduced or even cancelled, the volume and the weight of the system are greatly reduced, and therefore, the SiC power device is also known as a green energy device for driving the new energy revolution. .
But there is still much room for improvement in power devices of SiC materials. Taking a SiC MOSFET as an example, the magnitude of the MOSFET gate-drain capacitance Cgd influences the advantages and disadvantages of the dynamic performance of the MOSFET, and reducing Cgd can well optimize the switching performance and reduce the dynamic loss. The reliability of the body diode of the MOSFET is lower, the parasitic body diode is usually prevented from being conducted by connecting the diode in series with the drain electrode of the MOSFET in engineering, then a new freewheel path is provided by additionally connecting the Schottky diode in anti-parallel with the two ends of the drain electrode and the source electrode, and the reverse freewheel effect is achieved, but the process is complex, the reliability problem is easy to cause, the area of a chip is increased, and obviously, the complexity and the cost of the circuit design are greatly increased by the method.
Disclosure of Invention
The invention aims to provide a SIC MOSFET with a monopole electronic channel and a preparation method thereof, wherein the method can reduce the complexity of circuit design, realize reverse freewheeling by designing a simple monopole electronic channel and reduce the production cost.
A SIC MOSFET with unipolar electronic channels, comprising: an N-layer region;
the N-Drift layer is etched with a groove;
the side wall of the groove is doped with an N-layer region;
the N-Drift layer is doped with a P-well region, the first P-well region is located on the side of the N-layer region, and the P-well region is connected with the N-layer region.
Preferably, the method further comprises: a source electrode, a first grid electrode, a second grid electrode, a drain electrode and a first N+ region;
the first grid electrode and the second grid electrode are embedded in the groove;
the first grid electrode is connected with the source electrode;
the first N+ region is doped on the N-Drift upper layer and connected with the drain electrode.
Preferably, the method further comprises: a second P-well region, a first P+ region, a second N+ region, and a third N+ region;
the second N+ region and the third N+ region are positioned on the upper layer of the N-Drift layer;
the first P+ region and the second P+ region are positioned on the upper layer of the N-Drift layer;
the first P+ region is connected with the second N+ region and is positioned below the source electrode;
the second P+ region is connected with the third N+ region and is positioned below the source electrode;
the second P-well region is located below the second P+ region and the third N+ region.
Preferably, the method further comprises: the drain is disposed below the N-substrate.
Preferably, the N-layer region has a thickness of less than 20nm.
Preferably, the first P+ region and the second N+ region form ohmic contact with the source electrode;
the second P+ region and the third N+ region form ohmic contact with the source electrode;
the first n+ region forms an ohmic contact with the drain electrode.
A method of fabricating a SIC MOSFET with unipolar electronic channels, comprising:
doping a P-RESURF region, a P-well region and an N-layer region in the N-Drift layer;
doping a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region in the N-Drift layer;
etching the trench;
depositing a grid;
and depositing a source electrode and a drain electrode.
Preferably, P/N ion implantation doping is adopted to form a P-RESURF region, a P-well region and an N-layer region;
and forming a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region by adopting P+/N+ ion implantation doping.
Preferably, depositing the gate includes:
forming a first grid electrode and a second grid electrode by adopting a polysilicon deposition method;
the first gate is connected to the source.
Preferably, the thickness of the N-layer region is set to less than 20nm.
According to the invention, a very thin N-layer region is embedded beside the groove, the turn-on voltage is smaller than PN junction when SIC MOSFET is conducted reversely, so that a low potential barrier electronic channel is formed, the source electrode and the drain electrode are conducted, the follow current effect is achieved, the damage to the power device caused by self-induced potential generated when the circuit is powered off is prevented, the power device is prevented from being broken down by reverse voltage, the reverse follow current effect can be achieved without integrating SBD or JFET in reverse parallel, the production cost is greatly reduced, and the process preparation time is shortened.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a SIC MOSFET of the present invention;
FIG. 2 is a flow chart of the method of the present invention;
FIG. 3 is a schematic illustration of the preparation process of the present invention;
fig. 4 is a schematic view of a vertical structure device according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
SIC MOSFETs can generate reverse potential when turned off, the reverse potential is too high to break down the SIC MOSFETs, although the inherent PN junction body diode of the SIC MOSFETs can be used for reverse freewheeling, the freewheeling can only be realized in a zero-voltage switching mode, in some hard switching converters such as half-bridge, full-bridge and LLC power systems, the freewheeling diode in the SIC MOSFETs needs to finish freewheeling in a non-zero-voltage mode, the parasitic body diode in the traditional SIC MOSFETs has poor reverse recovery characteristics, large current spikes and turn-off surge voltages can be generated, and semiconductor devices can be damaged, so that the electrical performance of the power devices is greatly affected. Traditionally, a series diode is usually adopted in the SIC MOSFET drain to prevent the parasitic body diode from conducting, and then an anti-parallel fast recovery diode is additionally connected at two ends of the drain and source to provide a new freewheel path, and obviously, this method greatly increases the complexity and cost of circuit design.
According to the invention, a very thin N-layer region is embedded beside the groove, the turn-on voltage is smaller than PN junction when SIC MOSFET is conducted reversely, so that a low potential barrier electronic channel is formed, the source electrode and the drain electrode are conducted, the follow current effect is achieved, the damage to the power device caused by self-induced potential generated when the circuit is powered off is prevented, the power device is prevented from being broken down by reverse voltage, the reverse follow current effect can be achieved without integrating SBD or JFET in reverse parallel, the production cost is greatly reduced, and the process preparation time is shortened.
Example 1
A SIC MOSFET with unipolar electronic channels, as in fig. 1, comprising: an N-layer region;
the N-Drift layer is etched with a groove;
the width of the N-layer is controlled by the width of the groove and can be controlled by an ion implanter, but the width of the groove is controlled more simply and conveniently, the production cost is lower, the control process flow of the ion implanter is complex, and the production efficiency is low.
The side wall of the groove is doped with an N-layer region;
the N-Drift layer is doped with a P-well region, the first P-well region is located on the side of the N-layer region, and the P-well region is connected with the N-layer region.
SiC-MOSFETs are the most interesting devices in silicon carbide power electronics research. Silicon carbide (SiC) is a compound semiconductor material composed of Si (silicon) and C (carbon). Not only is the dielectric breakdown field strength 10 times that of Si, but also the band gap 3 times that of Si, and the necessary p-type and n-type can be controlled in a wider range during device manufacture, so that the dielectric breakdown field strength is considered as a power device material exceeding the limit of Si. Since SiC has an insulation breakdown field strength 10 times that of Si, a high withstand voltage power device of 600V to several thousand V can be made with a drift layer having a higher impurity concentration and a thinner thickness than Si devices.
As the Si material is a higher voltage-resistant device, the on-resistance per unit area is also larger (the ratio of the voltage-resistant value increases to about 2 to 2.5 times), and thus IGBTs (insulated gate bipolar transistors) are mainly used for voltages of 600V or more. The IGBT injects holes as minority carriers into the drift layer by conductivity modulation, and thus has an on-resistance smaller than that of the MOSFET, but at the same time, a tail current is generated at Turn-off due to accumulation of minority carriers, thereby causing a great switching loss. The SiC device drift layer has lower resistance than the Si device, and can achieve high withstand voltage and low resistance with MOSFETs without conductivity modulation. Further, since the MOSFET does not generate tail current in principle, when the SiC-MOSFET is used instead of the IGBT, switching loss can be remarkably reduced, and miniaturization of the heat dissipation member can be realized. In addition, siC-MOSFETs can be driven under high frequency conditions where IGBTs cannot operate, so that miniaturization of passive devices can also be achieved. Compared with a Si-MOSFET of 600V-900V, the SiC-MOSFET has the advantages of small chip area and capability of realizing small-sized packaging.
SiC-MOSFETs do not have an on-voltage, so low conduction losses can be achieved over a wide current range from small currents to large currents. The Si-MOSFET has an on-resistance at 150 ℃ which is 2 times or more higher than that at room temperature, and unlike Si-MOSFET, the SiC-MOSFET has a relatively low rise rate, and therefore is easy to thermally design and has a very low on-resistance at high temperature. The method is mainly applied to an inverter or a converter of an industrial machine power supply and a high-efficiency power regulator.
The N-Drift layer is a Drift layer, so that the voltage withstand capability of the SIC MOSFET can be improved, N-represents low concentration doping, and a depletion region is formed by N-when the MOSFET is turned off, so that the MOSFET is guaranteed to have a nominal voltage withstand capability.
P-well is a retrograde well where ions are implanted at high energy and high dose to the desired depth and at low energy and low dose. The ion concentration is not the highest, the lateral diffusion is smaller. The impurities are injected into the bottom of the trap by high-energy ion implantation, and the trap is called a retrograde trap because the concentration of the surface of the trap is not the highest, the concentration of the bottom of the trap is the lowest, and the reverse is the opposite. The ion concentration below the well is very high, and the retrograde well can effectively improve the latch-up and punch-through resistance of the MOS device.
The N-layer is an N-type layer, and 5-valent impurity elements are often doped to form the N-type layer. When the SIC MOSFET is connected with forward voltage, namely the drain electrode is at a high level, the N-layer is exhausted by a first P-well region beside, electrons cannot pass through the N-layer region, so that when the SIC MOSFET is connected with forward voltage, the direction of current is as follows: drain D-first n+ region-N-Drift layer-second P-well region-third n+ region-source. When the SIC MOSFET is connected with reverse voltage, namely the SOURCE electrode is at a high level, a split grid electrode S (a first grid electrode) induces a low potential barrier electron channel on one side of the N-type layer, a conducting channel from N-drift to N+ SOURCE is formed, the follow current is realized, and the current direction is as follows: the current path has smaller starting voltage than the current from the source S-second N+ region-first P-well region-N-Drift layer-first N+ region-drain D during reverse conduction, and can play a role of reverse freewheeling and better protect a power device.
Preferably, the method further comprises: a source electrode, a first grid electrode, a second grid electrode, a drain electrode and a first N+ region;
the first grid electrode and the second grid electrode are embedded in the groove;
the second grid electrode is embedded in the groove for opening the channel, the first grid electrode is embedded in the groove for inducing a low barrier electron channel to form reverse current, and the coupling of the source electrode and the drain electrode can be shielded, so that Qgd and turn-off loss are reduced.
The first grid electrode is connected with the source electrode;
when the source electrode is connected with the voltage, the first grid electrode correspondingly has the voltage, and the first grid electrode acts as the source electrode.
The first N+ region is doped on the N-Drift upper layer and connected with the drain electrode.
The first grid is a split grid S, the second grid is G, the first grid is connected with the source, the effect is equivalent to that of the source, the source and the first grid are conducted, the second grid is used for controlling the channel to be opened, when the SIC MOSFET is connected with forward voltage, the channel is opened below the second grid to allow current to pass, the size and the position of the second grid can influence the size of forward current, in a certain range, the larger the second grid is, the closer the position is to the lower part of the N-Drift, the larger the formed channel is, the more electrons can pass, the larger the forward current is, and the purpose of the first grid is to control the switching of an N-layer electron channel and reduce the Miller effect to reduce the turn-off loss. In a certain range, the position and the size of the first grid electrode can influence the formation of an N-type layer electron channel, and the larger the first grid electrode is, the closer the first grid electrode is to an N-layer region, the lower potential barrier channel can be more easily induced in the N-layer region, and the reverse current is increased.
The miller effect of the MOS tube can prolong the switching frequency, increase the power consumption and reduce the system stability in the high-frequency switching circuit. Cgs is called GS parasitic capacitance, cgd is called GD parasitic capacitance, input capacitance ciss=cgs+cgd, output capacitance coss=cgd+cds, reverse transmission capacitance crss=cgd, also called miller capacitance.
The miller effect refers to the effect that the distributed capacitance Cgd between the input and output of the miller effect is amplified by the inverse amplification effect, so that the equivalent input capacitance value is amplified, and the miller effect forms a miller platform. The three stages of the change of the grid voltage and the current are respectively as follows:
stage 1: the gate voltage increases from 0V to the MOS transistor turn-on process. During this process, the Miller capacitance is not active, which is the process of charging Cgs by the drive voltage through the gate resistance;
stage 2: the MOS tube is conducted, so that the voltage of the drain electrode of the MOS tube is reduced, a grid charging current is absorbed to the drain electrode through a Miller capacitor, cgs charging is reduced, and a voltage platform is formed;
stage 3: the Miller capacitance is full and the gate current is charged to Cgs, cgd until the charge is completed.
Under inductive loading, the switching process of the MOSFET is significantly elongated due to the Miller effect. The turn-on of the MOSFET is a process from scratch, the longer the drain and source overlap of the MOSFET, the greater the conduction loss of the MOSFET. Because of the miller capacitance and the miller platform, the on time of the MOSFET is prolonged, and the conduction loss of the MOSFET is necessarily increased.
The MOSFET has two working states, namely an off state and an on state. In the off state, the current flowing through the switch is 0, and the voltage across the switch is not 0, but p=ui=0, so that no power is consumed. In the on state, a current flows through the switch, but the voltage across the switch is 0, and similarly p=ui=0. In practice, there is always a transition state when the switching device is switched, which leads to switching losses. And the switching loss is proportional to the switching frequency
The switching loss includes on loss and off loss. The conduction loss is caused by the fact that the voltage of the switching device cannot be immediately reduced to 0 at the moment of conduction, and the current is increased from 0, so that voltage-current alternation phenomenon is generated on the switching tube, the loss voltage cannot be immediately reduced to 0 due to parasitic capacitance on the switching device, and the voltage on the capacitance cannot be suddenly changed, namely cannot be immediately reduced to 0, so that power loss is generated. During conduction, the stored energy of the parasitic capacitance is lost through the switching device. The turn-off loss is caused by the fact that the switching device current cannot drop to 0 immediately at the turn-off instant, but the voltage has risen from 0, and the voltage-current alternation phenomenon is generated on the switching device. The reason that the current cannot be immediately 0 is that there is parasitic inductance in the circuit connected to the switching device, which hinders the current change. And the transformer in the inverter circuit is an inductance element, when the switch is suddenly turned off, the current of the inductance element cannot be suddenly changed, and a large flyback voltage can be generated to prevent current change, and a relatively large loss is generated when the circuit is added on the switching tube. Increasing the switching speed does not eliminate losses, but rather causes the flyback voltage to be greater and the losses to be greater.
Typically, the turn-off loss is much larger than the turn-on loss. When the power tube is turned on and turned off, when the high current of the power tube suddenly drops to 0, a larger flyback voltage is generated, so that the power loss of the switch tube is larger. Reducing switching losses, critical is reducing turn-off losses
Because the MOS transistor manufacturing process necessarily generates Cgd, that is, the miller capacitance necessarily exists, the miller effect is unavoidable. But the effect of the Miller effect can be reduced by reducing the gate-drain charge Qgd. According to the invention, the source electrode S is inserted between the grid electrode G and the drain electrode D, so that the coupling between the grid electrode and the drain electrode is effectively shielded, the Miller effect is reduced, and the turn-off loss is reduced.
Preferably, the method further comprises: a second P-well region, a first P+ region, a second N+ region, and a third N+ region;
the second N+ region and the third N+ region are positioned on the upper layer of the N-Drift layer;
the n+ region and the p+ region are provided on the upper layer of the N-Drift layer so as to be in contact with the source electrode and the drain electrode, thereby forming a loop.
The first P+ region and the second P+ region are positioned on the upper layer of the N-Drift layer;
the positions of the first P+ region and the second N+ region can be interchanged, and the positions of the second P+ region and the third N+ region can be interchanged. The invention has no requirement on the range and the concentration of the P+ region and the N+ region, and can be adjusted according to actual conditions.
The first P+ region is connected with the second N+ region and is positioned below the source electrode;
the second P+ region is connected with the third N+ region and is positioned below the source electrode;
the second P-well region is located below the second P+ region and the third N+ region.
The structure improved for improving the reverse freewheeling of the SIC MOSFET in the prior art is mainly characterized in that a Schottky junction is integrated for the reverse freewheeling, and a P-type protection area and Schottky metal are connected with a source electrode. When the MOSFET is turned on in the forward direction, the Schottky junction is in a reverse bias state, and forward current completely flows through the channel; during reverse freewheeling, the turn-on voltage of the schottky diode is smaller than that of a PN junction (P-Body/N-Drfit junction) diode, so that the integrated schottky diode is conducted before the Body diode, and current flows through the schottky junction, so that freewheeling loss and reverse recovery loss are greatly reduced.
However, the technological process required by the method is more complex than that of the method, the technological parameters are more difficult to control, the area of the manufactured chip is larger, only one electronic channel is required to be arranged, when the SIC MOSFET is connected with reverse voltage, the opening voltage of the electronic channel is smaller than that of a PN junction (P-well/N-Drift junction), the electronic channel is conducted before the PN junction, when reverse electromotive force occurs during power failure, the electronic channel can be released through the circuit, the protection element is not broken down or burnt out by induced voltage, and the stability and the safety of the circuit can be effectively protected. Compared with the prior art, the parallel Schottky diode has the advantages of lower on-voltage, faster speed, smaller reverse recovery time, low loss, high switching efficiency, reduced packaging cost and improved reference for more efficient use of the chip manufacturing process in factories.
Preferably, the method further comprises: the drain is disposed below the N-substrate.
The drain arrangement of the conventional SIC MOSFET is not fixed, and the drain D may be arranged in a horizontal structure as shown in fig. 1; the drain D may also be arranged in a vertical structure as shown in fig. 4. The two structures are equivalent, the current directions are the same, when the SIC MOSFET is connected with forward voltage, namely the drain electrode D is connected with high level, the split grid electrode induces a low barrier electron channel on one side of the N type layer, a conductive channel from N-drift to N+ SOURCE is formed, the follow current effect is achieved, and the current directions are as follows: drain D-N-Sub-N-Drift-P-well-N+ region-source S; when the SIC MOSFET is connected with reverse voltage, namely the source electrode is connected with high level, the current direction is as follows: source S-n+ region-N-layer region-N-Drift layer-N-Sub layer-drain D.
Preferably, the N-layer region has a thickness of less than 20nm.
In the PN junction, holes and electrons move to the N region and the P region with low doping concentration respectively by diffusion due to the gradient of carrier concentration. Minority carriers generated by diffusion create an intrinsic electric field. The electric field causes drift movement of the carriers, which is exactly opposite to the direction of diffusion, and the carriers and the diffusion are in dynamic balance. The result of both effects is a depletion layer with very few electrons and holes formed at the PN junction. Because the depletion layer has few carriers, it is characterized as a capacitance, which is also referred to as junction capacitance. The ability of the P region to deplete the N region is limited, and if the thickness of the N-layer region is too wide, the P region cannot fully deplete the N region, forming a breakdown path, and the SIC MOSFET will leak electricity, resulting in a decrease in reverse withstand voltage capability of the SIC MOSFET. Therefore, the thickness of the N-layer region is set to be a thickness which can enable the P region to be depleted when the P region is connected with the forward voltage, and electrons can pass through the N-layer region when the SIC MOSFET is connected with the reverse voltage, so that a reverse freewheel path is formed, and the SIC MOSFET is protected from being broken down by the reverse potential.
Preferably, the first P+ region and the second N+ region form ohmic contact with the source electrode;
the second P+ region and the third N+ region form ohmic contact with the source electrode;
the ohmic contact is adopted to reduce contact resistance, reduce power damage and heat, and prolong the service life of the SIC MOSFET. The ohmic contact of the source metal and the P+/N+ region of the semiconductor can improve the working performance of the SIC MOSFET.
The first n+ region forms an ohmic contact with the drain electrode.
The ohmic contact of drain metal and the P+/N+ region of the semiconductor can improve the working performance of the SIC MOSFET,
when the semiconductor is in contact with metal, a barrier layer is formed, but when the semiconductor is highly doped, electrons can tunnel through the barrier, thereby forming an ohmic contact with a low resistance. Ohmic contact is very important for semiconductor devices, and good ohmic contact is formed, so that current input and output are facilitated, and alloys with different formulations are often selected for different semiconductor materials to be used as ohmic contact materials. The source electrode and the drain electrode provided by the invention are made of copper, aluminum, silver, nickel, zinc or alloy, so that the basic electrical parameters of the MOSFET can be better, the working frequency and the efficiency of the SIC MOSFET can be improved due to the low ohmic contact resistance, and the energy loss is reduced.
Example 2
A method of fabricating a SIC MOSFET with unipolar electronic channels, as in fig. 3, comprising:
s100, doping a P-RESURF region, a P-well region and an N-layer region in the N-Drift layer;
specifically, the lowest doping concentration of the substrate is 3×10 14 -1×10 15 cm -3 The doping concentration of the P-well trap region is required to be 5-10 times higher than that of the well region, and the ion concentration of the N-layer region is 1 multiplied by 10 16 -1×10 17 cm -3 。
S200, doping a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region in the N-Drift layer;
specifically, for doping of the source drain regions, the ion concentration of N+/P+ is as high as 10 20 cm -3 。
S300, etching a groove;
specifically, the first side of the etched groove can dig all the N-layer region, so that calculation is reduced, production cost is reduced, the first side of the groove can slightly exceed the width of the N-layer region during etching, accurate calculation and accurate operation are avoided, operation difficulty is reduced, the width of the second side of the etched groove can be adjusted according to practical conditions, the range is between 0nm and 20nm, accurate control of the width of the groove is not needed, and only the width of the N-layer region is enough to be used up by the P-well region.
S400, depositing a grid electrode;
specifically, the widths of the first gate and the second gate may be set according to actual conditions, the second gate is set according to the opening requirement of the channel, and the first gate is set according to the degree of shielding the source and the drain.
S500 deposits source and drain electrodes.
The source electrode is deposited above the P+ and the N+ and is contacted with the first grid electrode, the second grid electrode is not contacted with the source electrode, the first grid electrode plays a role of the source electrode, the first grid electrode is deposited in the groove, the coupling of the source electrode and the drain electrode can be shielded, the turn-off loss is reduced, and the drain electrode can be arranged to be in a parallel structure and a vertical structure.
The invention can also etch the groove first and then dope the P-RESURF region, the P-well region N-layer region, the first N+ region, the second N+ region, the third N+ region, the first P+ region and the second P+ region in the N-Drift layer, but obviously the manufacturing process is troublesome, the width of the N-layer region is difficult to control, and the complexity and the production cost of the technological process are greatly improved. The doping is sequentially carried out according to the stacking sequence of the doping regions, then the width of the N-layer region is controlled by etching the grooves, because the width of the grooves determines the width of the N-layer region, the wider the grooves are, the smaller the width of the N-layer region is, the narrower the grooves are, the larger the width of the N-layer region is, and the width of the N-layer region is controlled by etching the grooves according to actual conditions. The P-RESURF region is used for improving the voltage resistance, and the RESURF is a node which is formed by continuously burying a layer of P-Buried in the N-drift, so that the space charge region in the N-drift is distributed more greatly, and meanwhile, the electric field distribution is modulated, and reverse breakdown is changed.
The specific steps of doping include:
1. pre-cleaning and etching.
2. And (5) furnace tube deposition.
3. And (5) stripping glaze.
Pre-cleaning and etching: the wafer before deposition is subjected to a pre-cleaning process to remove particles and contaminants. The chemicals and process used are the same as the cleaning before oxidation. After the pre-clean, the wafer is chemically etched with HF or a solution with water to remove oxides that may grow on the exposed surface of the wafer. Exposure of the wafer to air or chemical pre-cleaning may form oxides on the wafer surface. Oxide removal is necessary to prevent impurities from entering the wafer surface. The etching time and concentration must be well balanced to avoid the mask oxide layer being removed or becoming too thin.
And (3) furnace tube deposition: the deposition process, like the oxidation process, requires a minimum of three cycles. The first cycle is the feed cycle and the process is carried out in a nitrogen atmosphere. The second cycle is a deposition doping cycle. The third cycle is a blanking cycle, which is also performed in a nitrogen atmosphere.
The wafers are placed vertically on the boat or parallel to the axis of the furnace tube. Vertical placement can achieve maximum placement density, but can lead to uniformity problems due to the wafer impeding gas flow. For uniform doping, the gases must be mixed uniformly between the wafers. The parallel arrangement provides uniformity advantages due to the unimpeded flow of gas between wafers, which has the disadvantages of dense die packing and low die count. In both placement modes, dummy wafers are placed at the front and rear ends of the boat to ensure uniform doping of the intermediate device wafers.
Preferably, P/N ion implantation doping is adopted to form a P-RESURF region, a P-well region and an N-layer region;
and forming a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region by adopting P+/N+ ion implantation doping.
Ion implantation method: ions of trivalent elements are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. The ion energy of the ion implantation process ranges from 0.1keV low energy in the ultra-shallow junction to 1MeV high energy implanted in the well region, and the energetic ions gradually lose energy through collisions with substrate atoms after passing through the target and finally stay in the substrate.
The ion implantation has the advantages of accurately controlling the total dosage, depth distribution and surface uniformity of impurities, being a low-temperature process (preventing the re-diffusion of the original impurities, etc.), and realizing self-alignment technology (reducing capacitance effect).
In the process flow, the next step of photolithography is etching or ion implantation. When ion implantation is performed, the ion beam cannot penetrate the photoresist in the place with photoresist protection; the ion beam can be implanted into the substrate where there is no photoresist to effect doping. Therefore, the photoresist used for the ion implantation process must be capable of effectively blocking the ion beam.
A process following many of the previous processes for integrated circuits is ion implantation (ion implantation), which are known as ion implantation lithography. After ion implantation is completed, the photoresist on the wafer surface must be removed, which is a difficulty in the photolithography process. The requirements for the cleaning process include:
cleanly and thoroughly removing the photoresist on the substrate;
avoiding damage to the surface of the substrate, particularly in the ion implantation region (i.e., the region without photoresist);
avoiding damage to devices such as the metal of the gate electrode as much as possible.
The dominant diversity of high energy ion implantation: in principle any element can be used as the implanted ion; the formed structure may be free from the limitation of thermodynamic parameters (diffusion, solubility, etc.); no change is made: the original size, roughness and the like of the workpiece are not changed; the method is suitable for the last procedure of various precision parts production; fastness: the implanted ions are directly combined with atoms or molecules on the surface of the material to form a modified layer, the modified layer and the substrate material have no clear interface, the combination is firm, and the falling phenomenon does not exist; without limitation: the injection process can be performed at material temperatures below zero and as high as several hundred thousand degrees; the surface strengthening can be carried out on materials which cannot be treated by the common method, such as plastics, steel materials with low tempering temperature and the like.
Preferably, depositing the gate includes:
forming a first grid electrode and a second grid electrode by adopting a polysilicon deposition method;
the first gate is connected to the source.
Chemical vapor deposition is an additive process that deposits a thin film layer on the wafer surface. High temperature Chemical Vapor Deposition (CVD) processes include epitaxial silicon deposition, selective epitaxial processes, polysilicon deposition, and Low Pressure Chemical Vapor (LPCVD) silicon nitride deposition. Polysilicon is used as a gate material and is also widely used for capacitor electrodes of DRAM chips. The silicide stack forms a gate electrode and a local connection line on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms a contact plug between the source/drain and the cell connection line. Silicide stack on third layer polysilicon (Poly 3) to form singleThe interconnect, the fourth layer of polysilicon (Poly 4) and the fifth layer of polysilicon (Poly 5), form the two electrodes of the storage capacitor, sandwiching a high dielectric coefficient dielectric. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) and is typically performed in a furnace tube of a vacuum system. Polysilicon deposition typically employs a silane (SiH 4) chemical reaction. The silane will decompose at high temperature and form silicon deposit on the heated surface, and the polysilicon doping process of in-situ Low Pressure Chemical Vapor Deposition (LPCVD) can be performed by directly inputting the doping gas of arsine (AH 3), phosphorus hydride (PH 3) or diborane (B2H 6) into the silicon material gas of silane or DCS in the reaction chamber (i.e. in the furnace tube). Typically, polysilicon deposition is performed at a low pressure of 0.2-1.0 Torr and a deposition temperature between 600 and 650 ℃, either with pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes areIs mainly determined by the temperature during deposition. Film thickness non-uniformity within the wafer is less than 4%.
The polysilicon deposition process is as follows: injecting and blowing out purified nitrogen when the system is idle; injecting process nitrogen when the system is idle; injecting process nitrogen and loading the wafer; injecting process nitrogen and lowering the reaction furnace tube (bell-shaped glass cover); turning off the nitrogen, and vacuumizing to reduce the pressure of the reaction chamber to a basic pressure (less than 2 mTorr); injecting nitrogen, stabilizing the temperature of the wafer and checking air leakage; turning off the nitrogen, and vacuumizing to enable the air pressure to rise back to the basic air pressure (less than 2 mTorr); nitrogen is injected and the pressure required for the process is set (about 250 mTorr); starting Si ratio gas flow, turning off nitrogen, and starting deposition; turning off the silane gas flow, opening a grid piston, and vacuumizing to enable the gas pressure to rise to the basic gas pressure; closing the grid piston, injecting nitrogen and increasing the air pressure to one atmosphere pressure; nitrogen is injected to reduce the temperature of the wafer, and then the bell-shaped glass cover is lifted; injecting process nitrogen and unloading the wafer; injecting and blowing out purified nitrogen when the system is idle. The resistivity of polysilicon films is largely dependent on the temperature at which they are deposited, dopant concentration, and annealing temperature, which in turn affects the grain size. Increasing the deposition temperature will cause a decrease in resistivity, increasing the dopant concentration will decrease the resistivity, and higher annealing temperatures will form larger sized grains and a consequent decrease in resistivity. The larger the grain size of the polysilicon, the more difficult the etching process is, since large grain sizes will result in rough polysilicon sidewalls, so polysilicon deposition must be performed at low temperatures to achieve smaller grain sizes, polysilicon etching and photoresist stripping, followed by high temperature annealing to form larger grain sizes and lower resistivity. In some cases, amorphous silicon is deposited at about 450 c and then patterned, etched and annealed to form a polysilicon with a larger, more uniform grain size.
Preferably, the thickness of the N-layer region is set to less than 20nm.
The ability of the P region to deplete the N region is limited, and if the thickness of the N-layer region is too wide, the P region cannot fully deplete the N region, forming a breakdown path, and the SIC MOSFET will leak electricity, resulting in a decrease in reverse withstand voltage capability of the SIC MOSFET. Therefore, the thickness of the N-layer region is set to be a thickness which can enable the P region to be depleted when the P region is connected with the forward voltage, and electrons can pass through the N-layer region when the SIC MOSFET is connected with the reverse voltage, so that a reverse freewheel path is formed, and the SIC MOSFET is protected from being broken down by the reverse potential.
In the specific preparation process, the width of the N-layer region is determined by the width of an etched groove, in the groove etching process, as shown in fig. 1, the N-layer region at the first end is completely removed, the N-layer region at the second end is reserved, and the width is smaller than 20nm.
According to the invention, a very thin N-layer region is embedded beside the groove, the turn-on voltage is smaller than PN junction when SIC MOSFET is conducted reversely, so that a low potential barrier electronic channel is formed, the source electrode and the drain electrode are conducted, the follow current function is realized, the damage to the power device caused by self-induced potential generated when the circuit is powered off is prevented, the power device is protected from being broken down by reverse voltage, the SBD or JFET is not required to be connected in an anti-parallel mode, the packaging cost is reduced, and the process preparation time is shortened.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A SIC MOSFET with unipolar electronic channels, comprising: an N-layer region;
the N-Drift layer is etched with a groove;
the side wall of the groove is doped with the N-layer region;
the N-Drift layer is doped with a first P-well region, the first P-well region is located on the side of the N-layer region, and the first P-well region is connected with the N-layer region.
2. The SIC MOSFET with unipolar electronic channels of claim 1, further comprising: a source electrode, a first grid electrode, a second grid electrode, a drain electrode and a first N+ region;
the first grid electrode and the second grid electrode are embedded in the groove;
the first grid electrode is connected with the source electrode;
the first N+ region is doped on the N-Drift upper layer and connected with the drain electrode.
3. The SIC MOSFET with unipolar electronic channels of claim 2, further comprising: a second P-well region, a first P+ region, a second N+ region, and a third N+ region;
the second N+ region and the third N+ region are positioned on the upper layer of the N-Drift layer;
the first P+ region and the second P+ region are positioned on the upper layer of the N-Drift layer;
the first P+ region is connected with the second N+ region and is positioned below the source electrode;
the second P+ region is connected with the third N+ region and is positioned below the source electrode;
the second P-well region is located below the second P+ region and the third N+ region.
4. The SIC MOSFET with unipolar electronic channels of claim 2, further comprising: the drain is disposed below the N-substrate.
5. The SIC MOSFET with unipolar electron channel of claim 1, wherein the N-layer region has a thickness less than 20nm.
6. The SIC MOSFET with unipolar electron channel of claim 2, wherein the first p+ region, the second n+ region form ohmic contacts with the source;
the second P+ region and the third N+ region form ohmic contact with the source electrode;
the first n+ region forms an ohmic contact with the drain electrode.
7. A method for fabricating a SIC MOSFET with unipolar electronic channels, comprising:
doping a P-RESURF region, a P-well region and an N-layer region in the N-Drift layer;
doping a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region in the N-Drift layer;
etching the trench;
depositing a grid;
and depositing a source electrode and a drain electrode.
8. The method for preparing the SIC MOSFET with the unipolar electron channel according to claim 7, wherein the P-RESURF region, the P-well region and the N-layer region are formed by P/N ion implantation doping;
and forming a first N+ region, a second N+ region, a third N+ region, a first P+ region and a second P+ region by adopting P+/N+ ion implantation doping.
9. The method of fabricating a SIC MOSFET with unipolar electron channels of claim 7, wherein the depositing the gate comprises:
forming a first grid electrode and a second grid electrode by adopting a polysilicon deposition method;
the first gate is connected to the source.
10. The method for manufacturing a SIC MOSFET with unipolar electron channel of claim 7, wherein the thickness of said N-layer region is set to less than 20nm.
CN202310603787.XA 2023-05-26 2023-05-26 SIC MOSFET with unipolar electronic channel and preparation method Pending CN116779681A (en)

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