CN117497601B - Structure, manufacturing method and electronic equipment of planar silicon carbide transistor - Google Patents
Structure, manufacturing method and electronic equipment of planar silicon carbide transistor Download PDFInfo
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- CN117497601B CN117497601B CN202311835796.8A CN202311835796A CN117497601B CN 117497601 B CN117497601 B CN 117497601B CN 202311835796 A CN202311835796 A CN 202311835796A CN 117497601 B CN117497601 B CN 117497601B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 89
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000002146 bilateral effect Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 16
- 238000003860 storage Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Electrodes Of Semiconductors (AREA)
Abstract
A planar silicon carbide transistor structure, a manufacturing method and electronic equipment belong to the technical field of semiconductors, and comprise two grid source structures which are symmetrical left and right, a substrate, a drift layer, a first active region and a plurality of second active regions, wherein the tangential planes which are symmetrical left and right are sagittal planes; the drift layer is arranged on the upper surface of the substrate; the two gate source structures and the first active region are both positioned on the upper surface of the drift layer and are arranged at intervals; the gate-source structure comprises a first well, a first active layer and a gate structure; the first well is arranged on the upper surface of the drift layer; the first trap is arranged at a preset distance from the sagittal plane; the first active layer is arranged in the first well and is positioned on the upper surface of the first well; the grid structure covers the top of the first well; the plurality of second active layers are arranged between the two grid structures; the substrate, the second active layer and the first well are of a first type; the drift layer, the first active region and the first active layer are of a second type; the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a structure, a manufacturing method and electronic equipment of a planar silicon carbide transistor.
Background
Silicon carbide (SiC) power metal-oxide-semiconductor field effect transistors (MOSFETs) have become a powerful competitor to silicon Insulated Gate Bipolar Transistors (IGBTs) in high power applications such as electric vehicles and photovoltaic inverters due to their faster switching speeds, lower switching losses and higher operating temperature ranges. In practical applications, the MOSFET needs an antiparallel diode to handle reverse current, and the silicon-based MOSFET usually adopts a body diode to reduce parasitic inductance, which plays a role of freewheeling, but for the SiC MOSFET, the material bandgap is wider, the body diode turn-on voltage (about 2.7V) is much higher than that of the silicon-based MOSFET (about 1.5V), and the conduction loss is larger.
The anti-parallel integration of the SiC MOSFET and the SBD or JFET by the related silicon carbide transistor can play a role of reverse freewheeling, but is usually connected in parallel on a plane, so that the chip area is increased; there is also a related structure in which a silicon carbide transistor controls the opening of a freewheel channel by a split gate in the reverse direction, but it has problems of gate reliability, complicated process, and low current density.
Therefore, the related silicon carbide transistor has the defects of large conduction loss, large chip area, poor reliability, complex process and low current density.
Disclosure of Invention
The application aims to provide a structure, a manufacturing method and electronic equipment of a planar silicon carbide transistor, and aims to solve the problems of large conduction loss, large chip area, poor reliability, complex process and low current density of a related gallium nitride power device.
The embodiment of the application provides a structure of a planar silicon carbide transistor, which comprises two grid source structures which are symmetrical left and right, a substrate, a drift layer and a first active region, wherein the tangential plane which is symmetrical left and right is a sagittal plane;
the drift layer is arranged on the upper surface of the substrate;
The two gate-source structures and the first active region are both positioned on the upper surface of the drift layer and are arranged at intervals;
The gate-source structure comprises:
A first well provided on an upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane;
the first active layer is arranged in the first well and positioned on the upper surface of the first well;
a gate structure covering a top of the first well;
The structure of the planar silicon carbide transistor further comprises:
a plurality of second active layers disposed between two of the gate structures;
wherein the substrate, the second active layer and the first well are of a first type; the drift layer, the first active region, and the first active layer are of a second type.
In one embodiment, the structure of the planar silicon carbide transistor further comprises:
Two second active regions disposed on a side of the first well away from the sagittal plane.
In one embodiment, the planar silicon carbide transistor structure comprises:
and a third active region located between the second active region and the first active region and on the upper surface of the drift layer.
In one embodiment, the planar silicon carbide transistor structure comprises:
A charge storage region disposed between two of the first wells.
In one embodiment, the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
In one embodiment, the method further comprises:
A first metal layer covering the first active layer and the second active layer;
a second metal layer located on the upper surface of the first active region;
A third metal layer connected to the gate structure;
The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor.
In one embodiment, the gate structure material includes silicon dioxide and polysilicon; the material of the second active layer includes polysilicon; the materials of the drift layer, the first active region, the first active layer, and the first well include silicon carbide.
The embodiment of the application also provides a manufacturing method of the planar silicon carbide transistor, which comprises the following steps:
forming a drift layer on the upper surface of the substrate;
Forming two first wells which are bilaterally symmetrical on the upper surface of the first side of the drift layer; the tangential plane which is bilaterally symmetrical is a sagittal plane, and a preset distance is arranged between the first trap and the sagittal plane;
forming two first active layers in the two first wells and on the upper surfaces of the first wells respectively, and forming a first active region on the upper surface of the second side of the drift layer;
forming two gate structures on top of the two first wells respectively;
a plurality of second active layers are formed between the two gate structures.
In one embodiment, after forming the two first wells symmetrical to each other on the upper surface of the drift layer, the method further includes:
two second active regions are respectively formed on the sides of the two first wells far away from the sagittal plane.
In one embodiment, after the two first wells are respectively formed on the sides far from the sagittal plane, the method further includes:
a third active region is formed between the second active region and the first active region and on the upper surface of the drift layer.
In one embodiment, after forming the plurality of second active layers between the two gate structures, the method further includes:
Forming a first metal layer on the upper surface of the first active layer and the upper surface of the second active layer;
forming a second metal layer on the upper surface of the first active region;
And forming a third metal layer connected with the grid structure.
The embodiment of the application also provides electronic equipment, which comprises the structure of the planar silicon carbide transistor.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: since the first active region serves as a drain electrode, the first well serves as a gate electrode, and the first active layer serves as a source electrode. The second active layer and the drift layer form a heterojunction. When the planar silicon carbide transistor is applied with forward voltage, the drain electrode and the source electrode are conducted, the heterojunction is reversely biased, and a depletion layer of the heterojunction expands to pinch off a freewheel channel; when the planar silicon carbide transistor is applied with reverse voltage, the drain electrode and the source electrode are turned off, the heterojunction is forward biased, and the depletion layer of the heterojunction expands and pinches off the flywheel to conduct, so that the reverse flywheel effect can be achieved without anti-parallel integration of the SiC MOSFET and a Schottky barrier diode (schottky barrier diode, SBD) or a junction field-effect transistor (JFET), the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of a freewheel channel in a planar silicon carbide transistor according to an embodiment of the present application;
FIG. 3 is a band diagram of a planar silicon carbide transistor structure according to one embodiment of the present application;
Fig. 4 is a schematic structural diagram of a planar silicon carbide transistor according to an embodiment of the present application;
fig. 5 is a schematic diagram of another structure of a planar silicon carbide transistor according to an embodiment of the present application;
FIG. 6 is another energy band diagram of a planar silicon carbide transistor structure according to an embodiment of the present application;
fig. 7 is a schematic diagram of another structure of a planar silicon carbide transistor according to an embodiment of the present application;
fig. 8 is a schematic diagram of another structure of a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 9 is a schematic diagram illustrating formation of a drift layer in a method for fabricating a planar silicon carbide transistor according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating a first well formed in a method for manufacturing a planar silicon carbide transistor according to an embodiment of the present application;
fig. 11 is a schematic diagram illustrating formation of a first active layer and a first active region in a method for manufacturing a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 12 is a schematic diagram illustrating a gate structure formed in a method for fabricating a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 13 is a schematic diagram illustrating a second active layer formed in a method for manufacturing a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 14 is a schematic diagram illustrating formation of a second active region in a method for fabricating a planar silicon carbide transistor according to an embodiment of the present application;
Fig. 15 is a schematic diagram illustrating formation of a third active region in a method for fabricating a planar silicon carbide transistor according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 shows the structure of a planar silicon carbide transistor provided in an embodiment of the present invention, and for convenience of explanation, only the portions related to the embodiment of the present invention are shown in detail as follows:
The planar silicon carbide transistor structure comprises two gate source structures which are bilaterally symmetrical, a substrate 10, a drift layer 20, a first active region 90 and a plurality of second active layers 60, wherein the bilaterally symmetrical tangential plane is a sagittal plane 100.
The drift layer 20 is provided on the upper surface of the substrate 10.
Both the gate-source structures and the first active region 90 are located on the upper surface of the drift layer 20 and are spaced apart.
The gate-source structure includes a first well 30, a first active layer 40, and a gate structure 50.
The first well 30 is provided on the upper surface of the drift layer 20; wherein a predetermined distance is provided between the first well 30 and the sagittal plane 100.
The first active layer 40 is disposed in the first well 30 and located on the upper surface of the first well 30.
The gate structure 50 covers the top of the first well 30.
The plurality of second active layers 60 are disposed between the two gate structures 50.
Wherein the doping type of the substrate 10, the second active layer 60 and the first well 30 is a first type; the drift layer 20, the first active region 90 and the first active layer 40 are of the second type. The first type and the second type are different.
It should be noted that, the second active layer 60 is highly doped, the doping concentration is more than 1e19, the width is about 0.1 to 0.2 μm, and the freewheel channel width is 0.1 to 0.2 μm, and the structure can increase the freewheel channel with little increase of the cell area.
The number of the second active layers 60 is more than two, and the description of the present application uses 2 second active layers 60 to form the freewheel channels, and embodiments that simply increase the number of the second active layers 60 and the freewheel channels are also within the scope of the present application.
In an embodiment, the first active region 90 serves as a drain, the first well 30 serves as a gate, and the first active layer 40 serves as a source. The second active layer 60 forms a heterojunction with the drift layer 20. Taking the first type as P-type and the second type as N-type as an example, when the planar silicon carbide transistor applies a forward voltage, the source electrode is connected to a low potential, the drain electrode and the source electrode are conducted, the heterojunction is reversely biased, and the depletion layer of the heterojunction expands to pinch off the freewheel channel, as shown in the left half part of fig. 2. When the planar silicon carbide transistor is applied with reverse voltage, the source electrode is connected with high potential, the drain electrode and the source electrode are turned off, the heterojunction is forward biased, and the depletion layer of the heterojunction expands to pinch off and conduct the flywheel, as shown in the right half part of fig. 2, so that the reverse flywheel effect can be achieved without anti-parallel integration of the SiC MOSFET and the SBD or the junction field effect transistor JFET, the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
As shown in fig. 3, the heterojunction energy band diagram is that the difference of forbidden band width causes the contact of silicon and silicon carbide to form the potential barrier difference of conduction band, in order to prevent the influence on voltage resistance caused by overlarge forward electric leakage, the forward electron potential barrier E-forward should be large enough, and the forward electron potential barrier Ep-forward is about 0.7eV; to increase the forward electron barrier height, it is considered to form a schottky contact on the second active layer 60. Silicon and silicon carbide contact do not form a potential barrier difference in the valence band, so holes can pass freely.
As shown in fig. 4, the structure of the planar silicon carbide transistor further includes a second active region 70.
The second active region 70 is disposed on a side of the first well 30 remote from the sagittal plane 100.
It should be noted that the doping type of the second active region 70 is the first type. The second active region 70 is heavily doped. The material of the second active region 70 may be silicon carbide.
By providing the second active region 70, isolation is formed between adjacent planar silicon carbide transistors, enabling integration of the cells of the plurality of planar silicon carbide transistors.
As shown in fig. 5, the structure of the planar silicon carbide transistor further includes a third active region 03.
The third active region 03 is located between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20.
Note that the doping type of the third active region 03 is the first type. The third active region 03 is lightly doped. The material of the third active region 03 may be silicon carbide.
The third active region 03 and the drift layer 20 form a super junction structure, so that the voltage resistance is improved; in addition, for the super junction structure, a large-area semiconductor column exists in the drift region, so that a certain minority carrier storage effect exists, the switching characteristic is poor, a heterojunction has no hole barrier, holes can pass through freely, and therefore the effect of rapidly extracting holes is achieved, and the switching frequency is improved.
As shown in fig. 6, the structure of the planar silicon carbide transistor further includes a charge storage region 80 (charge storage layer, CSL).
The charge storage region 80 is disposed between the two first wells 30.
Note that the doping type of the charge storage region 80 is the second type. The doping concentration of the charge storage region 80 is greater than the doping concentration of the drift layer 20 and less than the doping concentration of the first active layer 40. The material of the charge storage region 80 is silicon carbide.
Note that the CSL concentration is not preferably higher than 1E17, and as shown in fig. 7, high concentration SiC makes the heterojunction barrier thin, and electron tunneling from the second active region 70 to the drift layer 20 is more likely to occur, so that the forward leakage current increases, and the voltage resistance is deteriorated.
By providing the charge storage region 80, the JFET effect between the first wells 30 is reduced, increasing the forward conduction current of the planar silicon carbide transistor.
By way of example and not limitation, the first type is P-type and the second type is N-type; or alternatively
The first type is N type and the second type is P type.
As shown in fig. 8, the structure of the planar silicon carbide transistor further includes a first metal layer 01, a second metal layer 02, and a third metal layer.
The first metal layer 01 covers the first active layer 40 and the second active layer 60.
The second metal layer 02 is located on the upper surface of the first active region 90.
The third metal layer is connected to the gate structure 50.
The first metal layer 01 is a source electrode of a planar silicon carbide transistor, the second metal layer 02 is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor.
By way of example and not limitation, the second active layer 60 and the first metal layer 01 are schottky contacts, thereby increasing the potential barrier and reducing leakage current when forward voltages are applied to the planar silicon carbide transistor.
In particular implementations, the material of gate structure 50 includes silicon dioxide and polysilicon; the material of the second active layer 60 includes polysilicon; the materials of the drift layer 20, the first active region 90, the first active layer 40, and the first well 30 include silicon carbide.
The invention also provides an embodiment of a method of manufacturing a planar silicon carbide transistor, corresponding to an embodiment of a planar silicon carbide transistor.
A method of fabricating a planar silicon carbide transistor, the method comprising steps 401 to 405.
In step 401, as shown in fig. 9, a drift layer 20 is formed on the upper surface of a substrate 10;
the drift layer 20 is formed on the upper surface of the substrate 10 by sputtering or vapor deposition.
In step 402, as shown in fig. 10, two first wells 30 are formed on the upper surface of the first side of the drift layer 20, which are bilaterally symmetrical; the tangential plane of bilateral symmetry is a sagittal plane 100, and a predetermined distance is set between the first well 30 and the sagittal plane 100.
Two first wells 30 are formed symmetrically left and right on the upper surface of the first side of the drift layer 20 by ion implantation.
In step 403, as shown in fig. 11, two first active layers 40 are formed in the two first wells 30 and on the upper surfaces of the first wells 30, respectively, and a first active region 90 is formed on the upper surface of the second side of the drift layer 20.
Two first active layers 40 are formed in the two first wells 30, respectively, by ion implantation at the upper surfaces of the first wells 30, and first active regions 90 are formed at the upper surfaces of the second sides of the drift layer 20.
In step 404, as shown in fig. 12, two gate structures 50 are formed on top of the two first wells 30, respectively.
Two gate structures 5050 are formed on top of the two first wells 30 by thermal oxygen oxidation and polysilicon deposition, respectively.
In step 405, as shown in fig. 13, a plurality of second active layers 60 are formed between two gate structures 50.
A plurality of second active layers 60 are formed between the two gate structures 50 by vapor deposition and ion implantation.
In particular, step 402 is followed by steps 402-2 and 403.
In step 402-2, two second active regions 70 are formed on the sides of the two first wells 30 away from the sagittal plane 100, respectively, as shown in fig. 14.
Two second active regions 70 are formed by ion implantation on the sides of the two first wells 30 remote from the sagittal plane 100, respectively.
In step 405-3, as shown in fig. 15, a third active region 03 is formed between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20.
A third active region 03 is formed between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20 by ion implantation.
In particular, step 405 is followed by steps 406 to 408.
In step 406, a first metal layer is formed on the upper surface of the first active layer and the upper surface of the second active layer.
In step 407, a second metal layer is formed on the upper surface of the first active region.
In step 408, a third metal layer is formed in connection with the gate structure.
It is emphasized that the first metal layer is the source electrode of the planar silicon carbide transistor, the second metal layer is the drain electrode of the planar silicon carbide transistor, and the third metal layer is the gate electrode of the planar silicon carbide transistor.
It is noted that the metal layer may be gold or palladium.
The embodiment of the invention comprises two grid source structures which are bilaterally symmetrical, a substrate, a drift layer, a first active region and a plurality of second active regions, wherein the bilaterally symmetrical tangential planes are sagittal planes; the drift layer is arranged on the upper surface of the substrate; the two gate source structures and the first active region are both positioned on the upper surface of the drift layer and are arranged at intervals; the gate-source structure comprises a first well, a first active layer and a gate structure; the first well is arranged on the upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane; the first active layer is arranged in the first well and is positioned on the upper surface of the first well; the grid structure covers the top of the first well; the plurality of second active layers are arranged between the two grid structures; the substrate, the second active layer and the first well are of a first type; the drift layer, the first active region and the first active layer are of a second type; the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (9)
1. The planar silicon carbide transistor structure is characterized by comprising two grid source structures which are symmetrical left and right, a substrate, a drift layer and a first active region, wherein the tangential plane which is symmetrical left and right is a sagittal plane;
the drift layer is arranged on the upper surface of the substrate;
The two gate-source structures and the first active region are both positioned on the upper surface of the drift layer and are arranged at intervals;
The gate-source structure comprises:
A first well provided on an upper surface of the drift layer; wherein a preset distance is arranged between the first trap and the sagittal plane;
the first active layer is arranged in the first well and positioned on the upper surface of the first well;
a gate structure covering a top of the first well;
The structure of the planar silicon carbide transistor further comprises:
a plurality of second active layers disposed between two of the gate structures;
Wherein the substrate, the second active layer and the first well are of a first type; the drift layer, the first active region and the first active layer are of a second type;
Further comprises:
a first metal layer covering the drift layer, the first active layer, and the second active layer;
a second metal layer located on the upper surface of the first active region;
A third metal layer connected to the gate structure;
The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor;
Exposing the upper surface of the drift layer between the second active layers, wherein the first metal layer is in direct contact with the exposed upper surface of the drift layer;
the material of the second active layer includes polysilicon; the material of the drift layer comprises silicon carbide;
and a heterojunction is formed between the second active layer and the drift layer.
2. The structure of the planar silicon carbide transistor of claim 1, wherein the structure of the planar silicon carbide transistor further comprises:
Two second active regions disposed on a side of the first well away from the sagittal plane.
3. The structure of the planar silicon carbide transistor as set forth in claim 2, wherein the structure of the planar silicon carbide transistor includes:
and a third active region located between the second active region and the first active region and on the upper surface of the drift layer.
4. The planar silicon carbide transistor structure of claim 1, wherein the first type is P-type and the second type is N-type; or alternatively
The first type is N-type, and the second type is P-type.
5. The structure of any of claims 1 to 4, wherein the gate structure material comprises silicon dioxide and polysilicon; the material of the first active region, the first active layer, and the first well comprises silicon carbide.
6. A method of manufacturing a planar silicon carbide transistor, the method comprising:
forming a drift layer on the upper surface of the substrate;
Forming two first wells which are bilaterally symmetrical on the upper surface of the first side of the drift layer; the tangential plane which is bilaterally symmetrical is a sagittal plane, and a preset distance is arranged between the first trap and the sagittal plane;
forming two first active layers in the two first wells and on the upper surfaces of the first wells respectively, and forming a first active region on the upper surface of the second side of the drift layer;
forming two gate structures on top of the two first wells respectively;
forming a plurality of second active layers between the two gate structures;
Forming a first metal layer on the upper surface of the drift layer, the upper surface of the first active layer, and the upper surface of the second active layer;
forming a second metal layer on the upper surface of the first active region;
Forming a third metal layer connected with the grid structure;
Exposing the upper surface of the drift layer between the second active layers, wherein the first metal layer is in direct contact with the exposed upper surface of the drift layer;
the material of the second active layer includes polysilicon; the material of the drift layer comprises silicon carbide;
The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor;
and a heterojunction is formed between the second active layer and the drift layer.
7. The method of manufacturing a planar silicon carbide transistor according to claim 6, further comprising, after forming the two first wells in bilateral symmetry on the upper surface of the drift layer:
two second active regions are respectively formed on the sides of the two first wells far away from the sagittal plane.
8. The method of manufacturing a planar silicon carbide transistor according to claim 6, further comprising, after forming two second active regions on sides of the two first wells away from the sagittal plane, respectively:
a third active region is formed between the second active region and the first active region and on the upper surface of the drift layer.
9. An electronic device comprising the structure of the planar silicon carbide transistor according to any one of claims 1 to 5.
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