CN106876471A - Double flute UMOSFET devices - Google Patents
Double flute UMOSFET devices Download PDFInfo
- Publication number
- CN106876471A CN106876471A CN201710208837.9A CN201710208837A CN106876471A CN 106876471 A CN106876471 A CN 106876471A CN 201710208837 A CN201710208837 A CN 201710208837A CN 106876471 A CN106876471 A CN 106876471A
- Authority
- CN
- China
- Prior art keywords
- source
- double flute
- layer
- grid
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 30
- 229910052757 nitrogen Inorganic materials 0.000 claims description 24
- -1 Nitrogen ion Chemical class 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 27
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 18
- 239000007789 gas Substances 0.000 description 18
- 238000002513 implantation Methods 0.000 description 18
- 238000004026 adhesive bonding Methods 0.000 description 15
- 238000001259 photo etching Methods 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 12
- 239000012159 carrier gas Substances 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229910000077 silane Inorganic materials 0.000 description 12
- 239000012535 impurity Substances 0.000 description 9
- 239000001294 propane Substances 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 238000005566 electron beam evaporation Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 230000013011 mating Effects 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 3
- 239000012300 argon atmosphere Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000013049 sediment Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013499 data model Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The present invention relates to a kind of double flute UMOSFET devices.The device includes substrate zone (1)；Drift region (2), epitaxial layer (3), source region (4), stack gradually in the upper surface of substrate zone (1)；Grid, is arranged at drift region (2), epitaxial layer (3) and source region (4) inside and is located at the middle position of double flute UMOSFET devices；Gate medium protection zone (5), is arranged in drift region (2) and is located at grid lower section；Source electrode (10), is arranged at drift region (2), epitaxial layer (3) and source region layer (4) inside and positioned at double flute UMOSFET devices at two side positions；Source slot turning protection zone (6), is arranged in drift region (2) and is located at source electrode (10) lower section；Drain electrode (11), is arranged at substrate zone (1) lower surface.The present invention forms Schottky contacts by the interface of source electrode and drift region and epitaxial layer, while " the be powered deterioration " problem for ensureing not causing body diode, extra Schottky diode is reduced, the reliability of device is improve and is reduced the complexity and cost of device design.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of double flute UMOSFET devices.
Background technology
Wide bandgap semiconductor materials SiC has larger energy gap, critical breakdown electric field higher, high heat conductance and height
The desirable physicals such as electronics saturation drift velocity and chemical characteristic, are adapted to make high temperature, high pressure, high-power, Flouride-resistani acid phesphatase semiconductor
Device.In field of power electronics, power MOSFET has been widely used, and it has raster data model simple, and switch time is short etc.
Feature.The UMOSFET of vertical stratification relative to transversary MOSFET, cellular size small advantage small with conducting resistance,
Have broad application prospects.
But in UMOSFET, the electric field concentration of Cao Shan corners easilys lead to oxide layer at this and is punctured in advance, for
This phenomenon is even more serious for SiC material.It is that P+ grid oxygens are protected by one layer of P+ type doped region of bottom design of grid groove
Area, makes the spike electric field of bottom land be transferred to from gate oxide on the PN junction that P+ grid oxygens protection zone is constituted with N- drift regions, enters
And alleviate the integrity problem that oxide field brings.And the UMOSFET of dual-slot structure, by source electrode cutting, the region
The depth for going deep into N- drift regions is greater than depth of the grid oxygen in N- drift regions, and using this point, the electric field at oxide layer is because source
The presence of groove and be transferred to source slot corner, further improve device breakdown characteristics.MOSFET conducts in current transformer simultaneously
Power switch, when its body diode flows continuously through forward current as freewheeling path, it may occur that " be powered deterioration " phenomenon, makes to lead
Be powered resistance and the forward conduction voltage drop increase of diode, and causes integrity problem.
Therefore in actual application, it is typically employed in a device source-drain electrode two ends cut-in voltage in parallel and is less than the pole of body two
The method of the Schottky diode of pipe provides freewheeling path.Obvious this method substantially increases the complexity of circuit design
And cost.
The content of the invention
Therefore, to solve technological deficiency and deficiency that prior art is present, the present invention proposes a kind of double flute UMOSFET devices
Part.
Specifically, a kind of double flute UMOSFET devices that one embodiment of the invention is proposed, including：
Substrate zone 1；
Drift region 2, epitaxial layer 3, source region 4, stack gradually in the upper surface of the substrate zone 1；
Grid, is arranged at the drift region 2, the epitaxial layer 3 and the inside of the source region 4 and is located at the double flute
The middle position of UMOSFET devices；
Gate medium protection zone 5, is arranged in the drift region 2 and is located at grid lower section；
Source electrode 10, is arranged at the drift region 2, the epitaxial layer 3 and the inside of the source region layer 4 and is located at the double flute
At close two side positions of UMOSFET devices；
Source slot turning protection zone 6, is arranged in the drift region 2 and is located at the lower section of the source electrode 10；
Drain electrode 11, is arranged at the lower surface of the substrate zone 1.
In one embodiment of the invention, the substrate zone 1 be N-type SiC material, its thickness be 200 μm~500 μm,
Doping concentration is 5 × 1018cm-3~1 × 1020cm-3, Doped ions be Nitrogen ion.
In one embodiment of the invention, the drift region 2 is N-type SiC material, and its thickness is 10 μm~20 μm, mixes
Miscellaneous concentration is 1 × 1015cm-3~6 × 1015cm-3, Doped ions be Nitrogen ion.
In one embodiment of the invention, the epitaxial layer 3 is p-type SiC material, and its thickness is 1 μm~1.5 μm, mixes
Miscellaneous concentration is 1 × 1017cm-3, Doped ions be aluminium ion.
In one embodiment of the invention, the source region 4 is N-type SiC material, and its thickness is 0.5 μm, doping concentration is
5×1018cm-3, Doped ions be Nitrogen ion.
In one embodiment of the invention, the grid includes gate dielectric layer 7 and grid layer 8；The gate dielectric layer 7 is
SiO2Material, its thickness is 100nm；The grid layer 8 is ploy-Si materials, and its thickness is 2.4 μm, and width is 1.3 μm.
In one embodiment of the invention, the gate medium protection zone 5 is p-type doping, and doping concentration is 3 × 1018cm-3, Doped ions are aluminium ion, and its thickness is 0.5 μm.
In one embodiment of the invention, the source electrode 10 be Ti, Ni or Au material, the drain electrode 11 be Ti, Ni or
Au materials.
In one embodiment of the invention, source slot turning protection zone 6 be p-type doping, doping concentration be 3 ×
1018cm-3, Doped ions are aluminium ion, and its thickness is 0.5 μm.
In one embodiment of the invention, the double flute UMOSFET devices also include gate electrode 9 and passivation layer；Wherein,
The passivation layer is arranged at the upper surface of the source region 4, and the gate electrode 9 is arranged at the connection grid in the passivation layer
Pole.
Above-described embodiment, Schottky contacts are formed by the interface of source electrode and drift region and epitaxial layer, are substituted external
Schottky diode while " the be powered deterioration " problem for ensureing not causing body diode, reduces volume as freewheeling path
Outer Schottky diode, improves the reliability of device and reduces the complexity and cost of device design.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground explanation structure described herein and flow.
Brief description of the drawings
Below in conjunction with accompanying drawing, specific embodiment of the invention is described in detail.
Fig. 1 is a kind of structural representation of double flute UMOSFET devices provided in an embodiment of the present invention；
Fig. 2 Fig. 2 a- Fig. 2 k are a kind of process schematic representation of double flute UMOSFET devices provided in an embodiment of the present invention.
Specific embodiment
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of double flute UMOSFET devices provided in an embodiment of the present invention.This hair
Bright double flute UMOSFET devices include：
Substrate zone 1；
Drift region 2, epitaxial layer 3, source region 4, stack gradually in the upper surface of the substrate zone 1；
Grid, is arranged at the drift region 2, the epitaxial layer 3 and the inside of the source region 4 and is located at the double flute
The middle position of UMOSFET devices；
Gate medium protection zone 5, is arranged in the drift region 2 and is located at grid lower section；
Source electrode 10, is arranged at the drift region 2, the epitaxial layer 3 and the inside of the source region layer 4 and is located at the double flute
At close two side positions of UMOSFET devices；
Source slot turning protection zone 6, is arranged in the drift region 2 and is located at the lower section of the source electrode 10；
Drain electrode 11, is arranged at the lower surface of the substrate zone 1.
Alternatively, the substrate zone 1 be N-type SiC material, its thickness be 200 μm~500 μm, doping concentration be 5 ×
1018cm-3~1 × 1020cm-3, Doped ions be Nitrogen ion.
Alternatively, the drift region 2 is N-type SiC material, and its thickness is 10 μm~20 μm, doping concentration is 1 × 1015cm-3~6 × 1015cm-3, Doped ions be Nitrogen ion.
Alternatively, the epitaxial layer 3 is p-type SiC material, and its thickness is 1 μm~1.5 μm, doping concentration is 1 × 1017cm-3, Doped ions be aluminium ion.
Alternatively, the source region 4 is N-type SiC material, and its thickness is 0.5 μm, doping concentration is 5 × 1018cm-3, doping
Ion is Nitrogen ion.
Alternatively, the grid includes gate dielectric layer 7 and grid layer 8；The gate dielectric layer 7 is SiO2Material, its thickness
It is 100nm；The grid layer 8 is ploy-Si materials, and its thickness is 2.4 μm, and width is 1.3 μm.
Alternatively, the gate medium protection zone 5 is p-type doping, and doping concentration is 3 × 1018cm-3, Doped ions be aluminium from
Son, and its thickness is 0.5 μm.
Alternatively, the source electrode 10 is Ti, Ni or Au material, and the drain electrode 11 is Ti, Ni or Au material.
Alternatively, source slot turning protection zone 6 is p-type doping, and doping concentration is 3 × 1018cm-3, Doped ions are aluminium
Ion, and its thickness is 0.5 μm.
Alternatively, the double flute UMOSFET devices also include gate electrode 9 and passivation layer；Wherein, the passivation layer is arranged at
The upper surface of the source region 4, and the gate electrode 9 is arranged at the connection grid in the passivation layer.
Preferably, the depth of source slot (i.e. source electrode) is more than the depth of grid groove (i.e. grid), and the width of source slot is equal to P+ sources
The width of groove turning protection zone 6；The width of grid groove is equal to the width of P+ grid oxygens protection zone 5, the source electrode 10 and drift region 2 and outward
Prolong the interface between layer 3 for Schottky contacts, remaining is Ohmic contact.
Alternatively, source slot depth is 3 μm, and grid groove depth is 2.5 μm, etches to be formed by ICP.Source slot and source slot turning are protected
The width for protecting area 6 is respectively 1 μm, and the width of grid groove and gate medium protection zone (for example, grid oxygen protection zone) 5 is respectively 1.5 μm.
Deposit field oxide or Si3N4Layer opens electrode hole as passivation layer, corrosion and passivation layer.Gate electrode 9, drain 11 Hes
Source electrode 10 and its Schottky contacts are formed by electron beam evaporation metal.
The embodiment of the present invention, the present invention introduces Schottky diode by source slot, substitutes external Schottky diode
As freewheeling path, while " the be powered deterioration " problem for ensureing not causing body diode, extra Schottky two is reduced
Pole pipe, improves the reliability of device and reduces the complexity and cost of device design.
Embodiment two
Refer to the work that Fig. 2 a- Fig. 2 k, Fig. 2 a- Fig. 2 k are a kind of double flute UMOSFET devices provided in an embodiment of the present invention
Skill schematic diagram, the preparation method comprises the following steps：
Step a, in the Epitaxial growth N- drift regions 2 of N-type SiC substrate 1, as shown in Figure 2 a.
It it is first 200 μm to thickness, Nitrogen ion doping concentration is 5 × 1018cm-3N-type SiC substrate to carry out RCA standards clear
Wash, be then 10 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 1 × 1015cm-3N- drift
Area 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 2 b.
It is 1 μm that a layer thickness is grown on N- drift regions 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers 3.
Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 2 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 2 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its technique bar
Part is：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 2 e institutes using the etch mask of grid groove in N- drift regions 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ grid oxygens protection zone 5, implantation temperature be 650 DEG C.
Step f, etching forms source slot, as shown in figure 2f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：
ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 2 g institutes using the etch mask of source slot in N- drift regions 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as shown in fig. 2h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in fig. 2i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in figure 2j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in Fig. 2 k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift regions 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift regions 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
Embodiment three
Referring again to Fig. 2 a- Fig. 2 k, the preparation method can also comprise the following steps：
Step a, in the Epitaxial growth N- drift regions 2 of N-type SiC substrate 1, as shown in Figure 2 a.
It it is first 500 μm to thickness, Nitrogen ion doping concentration is 1 × 1020cm-3N-type SiC substrate 1 to carry out RCA standards clear
Wash, be then 20 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 3 × 1015cm-3N- drift
Area 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 2 b.
It is 1.5 μm that a layer thickness is grown on N- drift regions 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers
3.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 2 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 2 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its technique bar
Part is：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 2 e institutes using the etch mask of grid groove in N- drift regions 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ grid oxygens protection zone 5, implantation temperature be 650 DEG C.
Step f, etching forms source slot, as shown in figure 2f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：
ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 2 g institutes using the etch mask of source slot in N- drift regions 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as shown in fig. 2h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in fig. 2i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in figure 2j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in Fig. 2 k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift regions 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift regions 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
Example IV
Referring again to Fig. 2 a- Fig. 2 k, the preparation method can also comprise the following steps：
Step a, in the Epitaxial growth N- drift regions 2 of N-type Si substrates 1, as shown in Figure 2 a.
It it is first 300 μm to thickness, Nitrogen ion doping concentration is 1 × 1019cm-3N-type SiC substrate to carry out RCA standards clear
Wash, be then 15 μm in the Epitaxial growth thickness of whole SiC substrate 1, Nitrogen ion doping concentration is 6 × 1015cm-3N- drift
Area 2.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure
Hydrogen, impurity source is liquid nitrogen.
Step b, epitaxial growth P- epitaxial layer 3, as shown in Figure 2 b.
It is 1.3 μm that a layer thickness is grown on N- drift regions 2, and Al ion dopings concentration is 1 × 1017cm-3P- epitaxial layers
3.Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is pure hydrogen
Gas, impurity source is three base first aluminium.
Step c, epitaxial growth N+ source region layer 4, as shown in Figure 2 c.
It is 0.5 μm that a layer thickness is grown on P- epitaxial layers 3, and Nitrogen ion doping concentration is 5 × 1018cm-3N+ source region layers
4。
Its process conditions is：Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas is silane and propane, carrier gas
It is pure hydrogen, impurity source is liquid nitrogen.
Step d, etching forms grid groove, as shown in Figure 2 d.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1.5 μm to etch the width of groove, and depth is 2.5 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its technique bar
Part is：ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step e, carries out multiple Al ions autoregistration and injects, such as Fig. 2 e institutes using the etch mask of grid groove in N- drift regions 2
Show.
Successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ grid oxygens protection zone 5, implantation temperature be 650 DEG C.
Step f, etching forms source slot, as shown in figure 2f.
One layer of magnetron sputtering firstTi films as ICP etch masks, then gluing photoetching carries out ICP quarters
Erosion, it is 1 μm to etch the width of groove, and depth is 3 μm, is finally removed photoresist, and goes etch mask, cleans into mating plate.Its process conditions is：
ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively 48sccm and 12sccm.
Step g, carries out multiple Al ions autoregistration and injects, such as Fig. 2 g institutes using the etch mask of source slot in N- drift regions 2
Show.
First successively using 450keV, 300keV, 200keV and 120keV Implantation Energy, by implantation dosage be 7.97 ×
1013cm-2、4.69×1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ions, be injected into four times N- drift
The injection region in area 2, it is 0.5 μm to form depth, and concentration is 3 × 1018cm-3P+ source slots turning protection zone 6, implantation temperature is 650
℃。
Surface of SiC is cleaned using RCA cleanings standard again, the protection of C films is made after drying, then 1700~1750
Ion-activated annealing 10min is carried out in DEG C argon atmosphere.
Step h, preparation vessel gate medium 7, material therefor is SiO2, as shown in fig. 2h.
SiO is prepared at 1150 DEG C using dry oxygen technique2Gate dielectric layer, thickness is 100nm, then at 1050 DEG C, NO atmosphere
Annealed under enclosing, reduced SiO2The roughness of film surface.
Step i, prepares poly Si grid, as shown in fig. 2i.
Grid groove is filled up using low pressure hot wall chemical vapor deposition method growth poly Si, deposition temperature is 600~650 DEG C, is formed sediment
It is by force 60~80Pa to overstock, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etches poly
Si layers, polysilicon gate is formed, finally removed photoresist, cleaned.
Step j, prepares passivation layer, as shown in figure 2j.
One layer of field oxygen or Si are deposited in device surface3N4Layer, then gluing photoetching, corrosion and passivation layer opens electrode contact hole,
Finally remove photoresist, clean.
Step k, prepares electrode, as shown in Fig. 2 k.
Grid first are made in front electron beam evaporation Ti/Ni/Au, source electrode, then gluing photoetching, corrosion metal forms grid,
Source electrode, removes photoresist, cleaning.
Overleaf electron beam evaporation Ti/Ni/Au makes drain electrode again, finally short annealing 3min, temperature in an ar atmosphere
It is 1050 DEG C.Because N- drift regions 2 and the doping concentration of P- epitaxial layers 3 are relatively low, in source electrode 10 and and N- drift regions 2 and P- epitaxial layers
3 interfaces form Schottky contacts, and other interfaces form Ohmic contact.
In sum, a kind of double flute that specific case used herein is provided invention embodiment
The implementation method of UMOSFET devices and preparation method thereof is set forth, and the explanation of above example is only intended to help and understands
The method of the present invention and its core concept；Simultaneously for those of ordinary skill in the art, according to thought of the invention, in tool
Be will change in body implementation method and range of application, in sum, this specification content should not be construed as to the present invention
Limitation, protection scope of the present invention should be defined by appended claim.
Claims (10)
1. a kind of double flute UMOSFET devices, it is characterised in that including：
Substrate zone (1)；
Drift region (2), epitaxial layer (3), source region (4), stack gradually in the upper surface of the substrate zone (1)；
Grid, is arranged at the drift region (2), the epitaxial layer (3) and the source region (4) inside and is located at the double flute
The middle position of UMOSFET devices；
Gate medium protection zone (5), is arranged in the drift region (2) and is located at grid lower section；
Source electrode (10), is arranged at the drift region (2), the epitaxial layer (3) and the source region layer (4) inside and is located at described double
At close two side positions of groove UMOSFET devices；
Source slot turning protection zone (6), is arranged in the drift region (2) and is located at the source electrode (10) lower section；
Drain electrode (11), is arranged at the substrate zone (1) lower surface.
2. double flute UMOSFET devices according to claim 1, it is characterised in that the substrate zone (1) is N-type SiC materials
Material, its thickness is 200 μm~500 μm, doping concentration is 5 × 1018cm-3~1 × 1020cm-3, Doped ions be Nitrogen ion.
3. double flute UMOSFET devices according to claim 1, it is characterised in that the drift region (2) is N-type SiC materials
Material, its thickness is 10 μm~20 μm, doping concentration is 1 × 1015cm-3~6 × 1015cm-3, Doped ions be Nitrogen ion.
4. double flute UMOSFET devices according to claim 1, it is characterised in that the epitaxial layer (3) is p-type SiC materials
Material, its thickness is 1 μm~1.5 μm, doping concentration is 1 × 1017cm-3, Doped ions be aluminium ion.
5. double flute UMOSFET devices according to claim 1, it is characterised in that the source region (4) is N-type SiC material,
Its thickness is 0.5 μm, doping concentration is 5 × 1018cm-3, Doped ions be Nitrogen ion.
6. double flute UMOSFET devices according to claim 1, it is characterised in that the grid include gate dielectric layer (7) and
Grid layer (8)；The gate dielectric layer (7) is SiO2Material, its thickness is 100nm；The grid layer (8) is ploy-Si materials,
Its thickness is 2.4 μm, and width is 1.3 μm.
7. double flute UMOSFET devices according to claim 6, it is characterised in that the gate medium protection zone (5) is p-type
Doping, doping concentration is 3 × 1018cm-3, Doped ions are aluminium ion, and its thickness is 0.5 μm.
8. double flute UMOSFET devices according to claim 1, it is characterised in that the source electrode (10) is Ti, Ni or Au material
Material, the drain electrode (11) is Ti, Ni or Au material.
9. double flute UMOSFET devices according to claim 1, it is characterised in that source slot turning protection zone (6) is P
Type adulterates, and doping concentration is 3 × 1018cm-3, Doped ions are aluminium ion, and its thickness is 0.5 μm.
10. double flute UMOSFET devices according to claim 1, it is characterised in that also including gate electrode (9) and passivation layer；
Wherein, the passivation layer is arranged at the upper surface of the source region (4), and the gate electrode (9) is arranged in the passivation layer simultaneously
Connect the grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710208837.9A CN106876471B (en) | 2017-03-31 | 2017-03-31 | Dual trench UMOSFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710208837.9A CN106876471B (en) | 2017-03-31 | 2017-03-31 | Dual trench UMOSFET device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106876471A true CN106876471A (en) | 2017-06-20 |
| CN106876471B CN106876471B (en) | 2019-12-17 |
Family
ID=59160661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710208837.9A Active CN106876471B (en) | 2017-03-31 | 2017-03-31 | Dual trench UMOSFET device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106876471B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019102814A (en) * | 2017-12-01 | 2019-06-24 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ | Silicon carbide semiconductor module including trench gate structure and shield region |
| CN113990919A (en) * | 2021-10-12 | 2022-01-28 | 松山湖材料实验室 | Silicon carbide semiconductor structure, device and preparation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614749A (en) * | 1995-01-26 | 1997-03-25 | Fuji Electric Co., Ltd. | Silicon carbide trench MOSFET |
| CN102403315A (en) * | 2010-09-07 | 2012-04-04 | 株式会社东芝 | Semiconductor device |
| WO2012105609A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor device |
| US20150340360A1 (en) * | 2012-02-13 | 2015-11-26 | Maxpower Semiconductor Inc. | Lateral transistors and methods with low-voltage-drop shunt to body diode |
-
2017
- 2017-03-31 CN CN201710208837.9A patent/CN106876471B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614749A (en) * | 1995-01-26 | 1997-03-25 | Fuji Electric Co., Ltd. | Silicon carbide trench MOSFET |
| CN102403315A (en) * | 2010-09-07 | 2012-04-04 | 株式会社东芝 | Semiconductor device |
| WO2012105609A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor device |
| US20150340360A1 (en) * | 2012-02-13 | 2015-11-26 | Maxpower Semiconductor Inc. | Lateral transistors and methods with low-voltage-drop shunt to body diode |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019102814A (en) * | 2017-12-01 | 2019-06-24 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ | Silicon carbide semiconductor module including trench gate structure and shield region |
| JP7283890B2 (en) | 2017-12-01 | 2023-05-30 | インフィニオン テクノロジーズ アクチエンゲゼルシャフト | Silicon carbide semiconductor module with trench gate structure and shield regions |
| US11855147B2 (en) | 2017-12-01 | 2023-12-26 | Infineon Technologies Ag | Method for producing a silicon carbide semiconductor component |
| CN113990919A (en) * | 2021-10-12 | 2022-01-28 | 松山湖材料实验室 | Silicon carbide semiconductor structure, device and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106876471B (en) | 2019-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110034186B (en) | III-nitride enhanced HEMT based on composite barrier layer structure and manufacturing method thereof | |
| CN106876485A (en) | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof | |
| CN104067384A (en) | Method and system for a gallium nitride vertical JFET with self-aligned source and gate | |
| CN106876256A (en) | SiC double flute UMOSFET devices and preparation method thereof | |
| CN106711207B (en) | SiC junction type gate bipolar transistor with longitudinal channel and preparation method thereof | |
| CN104701359B (en) | Vertical stratification AlGaN/GaN HEMT devices and preparation method thereof | |
| CN108417493A (en) | P-type grid enhancement transistor and preparation method thereof based on oxidation self-stopping technology technology | |
| CN109244130A (en) | Self aligning grid structure GaN MIS-HEMT device and preparation method thereof based on p-GaN and SiN layer | |
| CN107240605A (en) | A kind of GaN MIS raceway grooves HEMT device and preparation method | |
| CN105185831A (en) | Silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure having self-aligned channels and manufacturing method thereof | |
| CN103928524B (en) | Carborundum UMOSFET devices and preparation method with N-type drift layer table top | |
| CN113889531A (en) | Semiconductor device and application and manufacturing method thereof | |
| CN115000168A (en) | P-type nitride enhanced HEMT device and preparation method thereof | |
| CN106876471A (en) | Double flute UMOSFET devices | |
| CN103928345B (en) | Ion implanting forms the UMOSFET preparation method of N-type heavy doping drift layer table top | |
| CN206574721U (en) | A kind of double trench MOSFET devices of SiC of integrated schottky diode | |
| CN111785776B (en) | Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor | |
| CN103247538A (en) | Split-gate trench power MOS (Metal Oxide Semiconductor) device integrating schottky | |
| CN104517837A (en) | Method for manufacturing insulated gate bipolar transistor | |
| CN106684132B (en) | Silicon carbide bipolar transistor npn npn and preparation method thereof based on active area groove structure | |
| CN101556967B (en) | Power semiconductor and manufacturing method thereof | |
| CN207068860U (en) | A kind of GaN MIS raceway groove HEMT devices | |
| CN206672934U (en) | The SiCJFET devices of integrated schottky diode | |
| CN103681831B (en) | High-electron mobility transistor and manufacturing method for same | |
| CN104966732A (en) | GaAs-based pHEMT device and preparation method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |