CN207068860U - A kind of GaN MIS raceway groove HEMT devices - Google Patents
A kind of GaN MIS raceway groove HEMT devices Download PDFInfo
- Publication number
- CN207068860U CN207068860U CN201720738269.9U CN201720738269U CN207068860U CN 207068860 U CN207068860 U CN 207068860U CN 201720738269 U CN201720738269 U CN 201720738269U CN 207068860 U CN207068860 U CN 207068860U
- Authority
- CN
- China
- Prior art keywords
- gan
- layers
- aln
- mis
- raceway groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005036 potential barrier Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 22
- 238000005530 etching Methods 0.000 abstract description 19
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 6
- 238000002360 preparation method Methods 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000000407 epitaxy Methods 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002161 passivation Methods 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The utility model discloses a kind of GaN MIS raceway groove HEMT devices, the material structure of the HEMT device includes substrate and the AlN nucleating layers, GaN cushions, GaN channel layers, AlN insert layers, AlGaN potential barrier and the GaN cap that grow up successively.In addition, the invention also discloses the preparation method of the HEMT device.The utility model inserts AlN thin layers during GaN epitaxy on channel layer, both confinement is carried out to two-dimensional electron gas as barrier layer, again as the etching cushion in subsequent technique.Damage when reducing and eliminate plasma etching grid recess by AlN insert layers to GaN surfaces, the performance at GaN MIS interfaces is improved, so as to play a part of reducing channel resistance and total conducting resistance.
Description
Technical field
The utility model belongs to technical field of semiconductor device, and in particular to a kind of GaN MIS raceway groove HEMT devices.
Background technology
One of the Typical Representatives of GaN as third generation semiconductor material with wide forbidden band, with traditional semi-conducting material Si, GaAs
Compare, have that energy gap is wide, breakdown electric field is big, electronics saturation drift velocity is high, dielectric constant is small and good chemistry is steady
The features such as qualitative.AlGaN/GaN hetero-junctions HEMT (HEMT) structure for being based particularly on GaN material has
Higher electron mobility (is higher than 1800cm2V-1s-1) and two-dimensional electron gas (2DEG) surface density (about 1013cm-2) so that it is based on
GaN material device all has obviously advantage in RF application and field of power electronics.
As one kind of enhancement device, MIS raceway grooves HEMT (MIS-channel HEMT) combines MISFET characteristic
Advantage with HEMT is (when gate medium is SiO2When be MOS raceway groove HEMT), i.e., with excellent enhanced performance, i.e. MIS grid
Control performance, and can keep HEMT two-dimensional electron gas high-conductivity in most of region, turn into current study hotspot.But
It is common MIS raceway grooves HEMT device, because the etching of groove can introduce defect on GaN surfaces, brings the problem of very big, lead
Cause MIS grid interface state density high very low with channel mobility so that the resistance of MIS gate grooves turns into the main electricity of HEMT device
Resistance part point.The uniformity of etching also is difficult to control simultaneously, causes the uniformity of device performance poor.Therefore, design is on the one hand passed through
The length of MIS grid is reduced with technique, on the other hand improving process reduces damage of the recess etch to GaN surfaces, is to improve
The important method of current MIS raceway groove HEMT device Performance And Reliabilities.
Utility model content
The utility model is a kind of GaN MIS raceway groove HEMT devices.AlN is inserted on channel layer during GaN epitaxy
Thin layer, confinement both was carried out to two-dimensional electron gas as barrier layer, again as the etching cushion in subsequent technique.Carved by AlN
Damage when erosion cushion reduces and eliminates plasma etching grid recess to GaN surfaces, improve the property at GaN MIS interfaces
Can, so as to reduce channel resistance and total conducting resistance.
To achieve the above object, the utility model uses following technical scheme：
A kind of GaN MIS raceway groove HEMT devices, the material structure of the HEMT device include substrate and successively life upwards
Long AlN nucleating layers, GaN cushions, GaN channel layers, AlN insert layers, AlGaN potential barrier and GaN cap.
Further, the thickness of the AlN nucleating layers is 20-100nm；The thickness of the GaN cushions is 1-5 μm；It is described
The thickness of GaN channel layers is 50-1000nm；The thickness of the AlN insert layers is less than 20nm；The thickness of the AlGaN potential barrier
For 10-50nm；The thickness of the GaN cap is less than 10nm.
Further, the substrate is SiC substrate, Si substrates, GaN substrate or Al2O3Substrate it is any.
A kind of method for preparing GaN MIS raceway groove HEMT devices, methods described comprise the following steps：
1) passed sequentially through on backing material MOCVD method growth in situ AlN nucleating layers, GaN cushions, GaN channel layers,
AlN insert layers, AlGaN potential barrier and GaN cap；
2) after using the isolation of conventional process flow completion device, source and drain ohmic contact craft, the etching of grid groove is carried out；
In the etching process of groove, at bottom of the etching close to AlGaN potential barrier, the AlN works higher than AlGaN etching selection ratio is selected
Skill condition continues to etch, it is ensured that etching is clean completely, while etch away sections AlN layers by AlGaN in each groove on wafer, remaining
Part AlN layers；
3) corroded with hot phosphoric acid, to erode the AlN layers of remainder in each groove on wafer；
4) it is surface-treated with the HF acid and HCl acid of dilution, removes the oxide on surface；Gate dielectric layer is deposited afterwards；
5) grid metal is deposited, deposit passivation dielectric layer is passivated protection after the completion of grid metal, then in each primitive unit cell
Source-drain electrode is once carved hole, and deposit metal forms source field plate on source-drain electrode；
6) the second passivation dielectric layer is finally deposited, carries out secondary quarter hole, medium is etched at source, leakage, gate electrode briquetting
Window, in the thick metal of medium window area deposit, and form the interconnection of medium bridge；The 3rd passivation layer or polyimides are deposited,
Whole chip surface is protected, and etches the window at electrode briquetting.
Further, the corrosion temperature that hot phosphoric acid is corroded in step 3) is 160-210 DEG C.
Further, step 4) gate dielectric layer is SiO2, SiN or Al2O3。
The utility model has following advantageous effects：
The utility model inserts AlN thin layers during GaN epitaxy on channel layer, both as barrier layer to Two-dimensional electron
Gas carries out confinement, again as the etching cushion in subsequent technique.Plasma etching is reduced and eliminated by AlN insert layers
To the damage on GaN surfaces during grid recess, the performance at GaN MIS interfaces is improved, reduces channel resistance so as to play and always leads
Be powered the effect hindered.
Brief description of the drawings
Fig. 1 is the utility model GaN MIS raceway groove HEMT device material structure schematic diagrams；
Fig. 2 is remainder AlN layers after grid recess etching in the utility model GaN MIS raceway groove HEMT device preparation process
Device architecture schematic diagram；
Fig. 3 is that the device architecture in the utility model GaN MIS raceway groove HEMT device preparation process after completion grid recess shows
It is intended to；
Fig. 4 is that the device architecture after gate dielectric layer is deposited in the utility model GaN MIS raceway groove HEMT device preparation process
Schematic diagram；
Fig. 5 is that the device architecture in the utility model GaN MIS raceway groove HEMT device preparation process after completion source field plate shows
It is intended to.
Embodiment
Below, refer to the attached drawing, the utility model is more fully illustrated, shown shown in the drawings of of the present utility model
Example property embodiment.However, the utility model can be presented as a variety of multi-forms, it is not construed as being confined to what is described here
Exemplary embodiment.And these embodiments are to provide, so that the utility model is fully and completely, and will be of the present utility model
Scope is fully communicated to one of ordinary skill in the art.
As shown in figure 1, the utility model provides a kind of GaN MIS raceway groove HEMT devices, the material knot of the HEMT device
Structure include substrate 1 and grow up successively AlN nucleating layers 2, GaN cushions 3, GaN channel layers 4, AlN insert layers 5,
AlGaN potential barrier 6 and GaN cap 7.The utility model inserts AlN thin layers, both conduct during GaN epitaxy on channel layer
Barrier layer carries out confinement to two-dimensional electron gas 10, again as the etching cushion in subsequent technique.
The thickness of AlN nucleating layers 2 is 20-100nm；The thickness of GaN cushions 3 is 1-5 μm；The thickness of GaN channel layers 4 is
50-1000nm；The thickness of AlN insert layers 5 is less than 20nm；The thickness of AlGaN potential barrier 6 is 10-50nm；The thickness of GaN cap 7
Less than 10nm.
Substrate 1 is SiC substrate, Si substrates, GaN substrate or Al2O3Substrate it is any.
The utility model additionally provides a kind of method for preparing GaN MIS raceway groove HEMT devices, and this method includes following step
Suddenly：
Step 1：MOCVD method growth in situ AlN nucleating layers 2, GaN cushions 3, GaN are passed sequentially through on backing material
Channel layer 4, AlN insert layers 5, AlGaN potential barrier 6 and GaN cap 7；
Step 2：As shown in Fig. 2 as in general technological process, the isolation of device, source and drain Ohmic contact 9 are completed
After technique, the etching of grid groove 8 is carried out；Make mask with photoresist and use Cl base atmosphere direct etching GaN, or SiO can be used2Make
For mask, SiO is first etched2Figure.In the etching process of groove, at bottom of the etching close to AlGaN potential barrier 6, choosing
Select the AlN process conditions higher than AlGaN etching selection ratio to continue to etch, it is ensured that AlGaN is etched completely in each groove on wafer
Totally, while etch away sections AlN layers, remainder AlN layers；Because AlGaN etch uniformities are poor, therefore AlN in each groove
Remaining thickness is all different.
Step 3：As shown in figure 3, it is 160-210 DEG C to carry out corrosive attack temperature with hot phosphoric acid.Because MOCVD methods exist
Long AlN layer quality is not very good on GaN, while is etched again by plasma, therefore hot phosphoric acid energy fast erosion
AlN, but do not corrode GaN.AlN etching cushions protect the GaN surface influence that subject plasma does not etch well.
Step 4：As shown in figure 4, after corroding the AlN residue thin layers in clean each groove, entered with the HF acid and HCl acid of dilution
Row surface treatment, remove the oxide on surface.Gate dielectric layer 11 is deposited, gate dielectric layer 11 can be SiO2、SiN、Al2O3Deng (when
Gate medium is SiO2When be MOS raceway groove HEMT), CVD method or ALD methods can be used.The thickness of gate dielectric layer 11 is in 10-
Between 100nm, designed according to the requirement of threshold voltage and operating voltage.
Step 5：As shown in figure 5, deposit grid metal 12, is performed etching.Or form grid metal with the method for lithography stripping
12.Grid metal 12 can be TiNiAu, TiPtAu, TiAl, Al etc..Passivation dielectric layer is deposited after the completion of grid metal 12 to be passivated
Protection, dielectric passivation can be SiO2, SiN, or one or more layers etc..Then carried out once in the source-drain electrode of each primitive unit cell
Hole is carved, deposit metal is on source-drain electrode, and 13 be drain metal in figure；And form source field plate 14.Metal has also been made in chip simultaneously
Source and drain briquetting (PAD) place.The metal thickeied on source-drain electrode can reduce the conducting resistance of each primitive unit cell interconnection in device.
Step 6：The second passivation dielectric layer is finally deposited, carries out secondary quarter hole, is etched at source, leakage, gate electrode briquetting
Medium window, in the thick metal of medium window area deposit, and form the interconnection of medium bridge；Deposit the 3rd passivation layer or polyamides is sub-
Amine, whole chip surface is protected, and etch the window at electrode briquetting.
It is described above simply to illustrate that the utility model, it is understood that the utility model be not limited to the above implementation
Example, meets the various variants of the utility model thought within the scope of protection of the utility model.
Claims (3)
- A kind of 1. GaN MIS raceway groove HEMT devices, it is characterised in that the material structure of the HEMT device include substrate and according to Secondary the AlN nucleating layers grown up, GaN cushions, GaN channel layers, AlN insert layers, AlGaN potential barrier and GaN cap.
- 2. GaN MIS raceway groove HEMT devices according to claim 1, it is characterised in that the thickness of the AlN nucleating layers is 20-100nm；The thickness of the GaN cushions is 1-5 μm；The thickness of the GaN channel layers is 50-1000nm；The AlN is inserted The thickness for entering layer is less than 20nm；The thickness of the AlGaN potential barrier is 10-50nm；The thickness of the GaN cap is less than 10nm.
- 3. GaN MIS raceway groove HEMT devices according to claim 1, it is characterised in that the substrate is SiC substrate, Si Substrate, GaN substrate or Al2O3Substrate it is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720738269.9U CN207068860U (en) | 2017-06-23 | 2017-06-23 | A kind of GaN MIS raceway groove HEMT devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720738269.9U CN207068860U (en) | 2017-06-23 | 2017-06-23 | A kind of GaN MIS raceway groove HEMT devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207068860U true CN207068860U (en) | 2018-03-02 |
Family
ID=61509502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720738269.9U Active CN207068860U (en) | 2017-06-23 | 2017-06-23 | A kind of GaN MIS raceway groove HEMT devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207068860U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107240605A (en) * | 2017-06-23 | 2017-10-10 | 北京华进创威电子有限公司 | A kind of GaN MIS raceway grooves HEMT device and preparation method |
| CN110828292A (en) * | 2018-08-13 | 2020-02-21 | 西安电子科技大学 | Semiconductor device based on composite substrate and preparation method thereof |
-
2017
- 2017-06-23 CN CN201720738269.9U patent/CN207068860U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107240605A (en) * | 2017-06-23 | 2017-10-10 | 北京华进创威电子有限公司 | A kind of GaN MIS raceway grooves HEMT device and preparation method |
| CN110828292A (en) * | 2018-08-13 | 2020-02-21 | 西安电子科技大学 | Semiconductor device based on composite substrate and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107240605A (en) | A kind of GaN MIS raceway grooves HEMT device and preparation method | |
| CN110034186B (en) | III-nitride enhanced HEMT based on composite barrier layer structure and manufacturing method thereof | |
| US11888052B2 (en) | Semiconductor device and manufacturing method thereof employing an etching transition layer | |
| CN102629624B (en) | Metal-insulator-semiconductor (MIS) grid enhanced high electron mobility transistor (HEMT) device based on gallium nitride (GaN) and manufacture method of MIS grid enhanced HEMT device | |
| CN105355555A (en) | GaN-based enhanced power electronic device and preparation method thereof | |
| JP5087240B2 (en) | Manufacturing method of nitride semiconductor device | |
| CN108305834A (en) | A kind of preparation method of enhancement type gallium nitride fieldtron | |
| CN102916046B (en) | Nitride high-voltage device on silicon substrate and manufacture method thereof | |
| WO2018032601A1 (en) | Method for preparing enhanced gan-based hemt device | |
| CN102683406B (en) | GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof | |
| CN108155099A (en) | A kind of p-type grid HEMT device comprising dielectric layer and preparation method thereof | |
| CN108417493A (en) | P-type grid enhancement transistor and preparation method thereof based on oxidation self-stopping technology technology | |
| JP2008078526A (en) | Nitride semiconductor device and its manufacturing method | |
| CN102097483A (en) | GaN-base heterostructure enhancement type insulated gate field effect transistor and preparation method thereof | |
| CN108365008A (en) | Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron | |
| CN106158960A (en) | GaN enhancement mode MOSFET and preparation method is formed based on digitized wet method grid lithographic technique | |
| CN106298904A (en) | Nitridation gallio enhancement device with gallium nitride interposed layer and preparation method thereof | |
| CN109659355A (en) | Normally-off gallium oxide field-effect transistor structure and preparation method | |
| CN207068860U (en) | A kind of GaN MIS raceway groove HEMT devices | |
| CN107785258A (en) | A kind of preparation method of 4H SiC p-type insulated gate bipolar transistors | |
| CN105448974A (en) | GaN-based thin film transistor structure and preparation method therefor | |
| CN105280694A (en) | Semiconductor power component | |
| CN104465403A (en) | Enhanced AlGaN/GaN HEMT device preparation method | |
| JP2005311029A (en) | Nitride semiconductor device and manufacturing method thereof | |
| CN113628962B (en) | III-nitride enhanced HEMT device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PP01 | Preservation of patent right |
Effective date of registration: 20180814 Granted publication date: 20180302 |
|
| PP01 | Preservation of patent right | ||
| PD01 | Discharge of preservation of patent |
Date of cancellation: 20200810 Granted publication date: 20180302 |
|
| PD01 | Discharge of preservation of patent | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231016 Address after: Room JZ2467, Yard 2, Junzhuang Road, Junzhuang Town, Mentougou District, Beijing, 102399 (cluster registration) Patentee after: Beijing Xingyun Lianzhong Technology Co.,Ltd. Address before: 100176 courtyard 17, Tonghui Ganqu Road, Daxing Economic and Technological Development Zone, Beijing Patentee before: BEIJING HUAJINCHUANGWEI ELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |