CN102683406B - GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof - Google Patents
GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof Download PDFInfo
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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Abstract
The invention discloses a GaN-based MS grid enhancement type high electron mobility transistor and a manufacture method thereof which mainly resolve the problems of low current density and poor reliability of a GaN-based enhancement type device. The structure of the device is that a transition layer (2) and a GaN main buffer layer (3) are sequentially arranged on a lining (1), a groove (4) is etched in the middle of the GaN main buffer layer, an AlGaN main barrier layer (5) is respectively arranged above the GaN mian buffer layer (3) on two sides of the groove, and a GaN auxiliary buffer layer (6) and an AlGaN auxiliary barrier layer (7) are sequentially arranged on the inner wall of the groove and the surface of the AlGaN main barrier layer (5) on two sides of the groove. A source electrode (8), a drain electrode (9), a grid electrode (11) and a medium layer (10) are arranged on the AlGaN secondary barrier layer (7). The source electrode (8) and the drain electrode (9) are respectively located on two sides above the AlGaN auxiliary barrier layer (7), the grid electrode (11) is located in the middle above the AlGaN auxiliary barrier layer (7), and the medium layer (10) is distributed on an area outside the source electrode, the drain electrode and the grid electrode. The transistor has the advantages of being good in enhancement type characteristic, high in current density, high in breakdown voltage, simple and mature in manufacture process and high in reliability, thereby being capable of being used in high temperature switch devices and digital circuits.
Description
Technical field
The invention belongs to microelectronics technology, relate to semi-conducting material, device and manufacture craft thereof.MS grid enhancement type high electron mobility transistor and the manufacture method of GaN base, can be used in high temperature high power application scenario and digital circuit elementary cell specifically.
Background technology
Along with the development of modern weapons equipment and Aero-Space, nuclear energy, the communication technology, automotive electronics, Switching Power Supply, the performance of semiconductor device is had higher requirement.Typical Representative as semiconductor material with wide forbidden band, the features such as GaN sill has that energy gap is large, electronics saturation drift velocity is high, critical breakdown strength is high, thermal conductivity is high, good stability, corrosion-resistant, radioresistance, can be used for making high temperature, high frequency and high-power electronic device.In addition, GaN also has good characteristic electron, can form the AlGaN/GaN heterostructure of modulation doping with AlGaN, and this structure at room temperature can obtain higher than 1500cm
2the electron mobility of/Vs, and up to 3 * 10
7the peak value velocity of electrons and 2 * 10 of cm/s
7the saturated electrons speed of cm/s, and obtain the two-dimensional electron gas density higher than second generation compound semiconductor heterostructure, being described as is the ideal material of development microwave power device.Therefore, the high electron mobility transistor (HEMT) based on AlGaN/GaN heterojunction has extraordinary application prospect aspect microwave high power device.
The main status that the development of the growth of AlGaN/GaN heterojunction material and AlGaN/GaN HEMT device is studied in occupation of GaN electronic device all the time.Yet the major part work for the research of GaN base electron device concentrates on depletion-mode AlGaN/GaN HEMT device for over ten years, this is because the existence of stronger polarization charge in AlGaN/GaN heterostructure, make the enhancement device of manufacturing based on GaN become very difficult, so the research of high-performance AlGaN/GaN enhancement mode HEMT have very important significance.First, it is the ideal material of development microwave power device that GaN sill is described as, and enhancement device in the circuit such as microwave power amplifier and low noise amplifier owing to having reduced negative voltage source, thereby greatly reduce complexity and the cost of circuit, and AlGaN/GaN enhancement mode HEMT device has good circuit compatibility at microwave high power device and circuit; Meanwhile, the development of enhancement device makes the digital circuit of the integrated depletion type/enhancement device of monolithic become possibility; And in the power application aspect of opening the light, AlGaN/GaN enhancement mode HEMT also has very large application prospect; Thereby the research of high-performance AlGaN/GaN enhancement mode HEMT device has obtained great attention.
At present, no matter be domestic or in the world, there are much the reports about AlGaN/GaN enhancement mode HEMT.At present report mainly contain following several technology:
1.F ion implantation technique, the i.e. plasma injection technique based on fluoride CF4, the people such as the Yong Cai of Hong Kong University of Science and Thchnology have successfully developed the enhancement mode HEMT device based on F ion implantation technique, this device is by injecting F ion in the AlGaN barrier layer under AlGaN/GaN HEMT grid, strong elecrtonegativity due to F ion, F ion in barrier layer can provide stable negative electrical charge, thereby can effectively exhaust the strong two-dimensional electron gas of channel region, when the F number of ions in AlGaN barrier layer reaches some, the two-dimensional electron gas at grid lower channel place exhausts completely, thereby realize enhancement mode HEMT device.But F injection technique inevitably can be introduced the damage of material, and the controllability of device threshold voltage is not high.This device at room temperature thin layer carrier concentration up to 1.3 * 10
13cm
-2, mobility is 1000cm
2/ Vs, threshold voltage reaches 0.9V, and maximum drain current reaches 310mA/mm.Referring to document Yong Cai, Yugang Zhou, Kevin J.Chen and Kei May Lau, " High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment ", IEEE Electron Device Lett, Vol.26, No.7, JULY2005.
2. nonpolar or semi-polarity GaN material is realized enhancement device, and the people such as Masayuki Kuroda successfully use r face
a face on sapphire
n-AlGaN/GaN HEMT has realized the enhancing of device, because nonpolar or semi-polarity material is owing to lacking polarity effect, therefore its two-dimensional electron gas is very little does not even have, so the AlGaN/GaN HEMT device based on nonpolar or semi-polarity material has enhancing characteristic.The threshold voltage of its report is-0.5V, by reduction, mixes concentration and can further increase device threshold voltage, but its device property bad, its electron mobility only has 5.14cm
2/ Vs, room temperature lower block resistance is very large.And its grid leak TV university is little has reached 1.1 * 10 when Vgs=-10V
-5a/mm.Referring to document Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka, " Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire ", Journal of Aplied Phisics, Vol.102, No.9, November2007.
3. thin barrier layer technology, 1996, first the people such as M.Asif Khan have realized AlGaN/GaN enhancement mode HEMT device by the thin barrier layer technology of AlGaN of 10nm, thin barrier layer AlGaN/GaN enhancement mode HEMT device is due to barrier layer thickness attenuate, its polarity effect weakens, the raceway groove place two-dimensional electron gas being caused by polarity effect reduces, thereby realizes moving to right of device threshold voltage.But the result that they obtain is unsatisfactory, and its peak value mutual conductance only has 23mS/mm.Referring to document M.Asif Khan, Q.Chen, C.J.Sun, J.W.Yang, and M.Blasingame, " Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors " Appl.Phys.Lett, Vol.68, No.4, January1996.
4. groove gate technique, the people such as W.B.Lanford utilize groove gate technique to make the enhancement device that threshold voltage reaches 0.47V by MOCVD, and this device architecture comprises from bottom to top: SiC substrate, nucleating layer, the GaN that 2um is thick, the AlGaN that 3nm is thick, the n-AlGaN that 10nm is thick, the AlGaN that 10nm is thick.This technology is passed through the barrier layer etching certain depth under grid, make the attenuation of grid lower barrierlayer, thereby 2DEG concentration under grid is reduced, and the carrier concentration of source-drain area keeps higher value constant, the enhancing characteristic that so both can realize device, can guarantee certain current density again.Its epitaxial growth of enhancement device that utilizes groove gate technique to realize is easily controlled, but its control is poor, and etching process can form damage.Referring to document W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida, " Recessed-gate enhancement-mode GaN HEMT with high threshold voltage ", Electronics Letrers, Vol.41, No.7March2005.
In sum, AlGaN/GaN HEMT enhancement device mainly adopts based on groove gate technique with based on the formation of fluorine ion injection technique in the world at present, and it all exists following deficiency:
(1) increase of threshold voltage take that to reduce current density be cost often, is difficult to realize the enhancement device that high threshold voltage and high current density coexist;
(2) groove gate technique or fluorine ion injection technique all can cause damage to material, although annealed, can eliminate certain damage, but residual damage still can impact device performance and reliability, the repeatability of current this technique is also not high simultaneously;
(3) make the technology difficulty of the long short channel device of short grid larger, cause device reliability low.
Summary of the invention
The object of the invention is to overcome the defect of above-mentioned prior art, propose a kind of MS grid enhancement type high electron mobility transistor and manufacture method of GaN base, to increase the current density of device, reduce technology difficulty, improve the reliability of device, meet practical application.
For achieving the above object, the structure of High Electron Mobility Transistor provided by the invention comprises from bottom to top: comprise from bottom to top: substrate, transition zone and GaN host buffer layer, is characterized in that:
The centre of GaN host buffer layer is etched with groove, the bottom surface of this groove is 0001 polar surface, groove side is non-zero 001, and the GaN host buffer layer top of groove both sides is the main barrier layer of AlGaN, forms main two-dimensional electron gas 2DEG layer on the main barrier layer of GaN host buffer layer and AlGaN interface;
In the bottom surface of groove and side surface direction and the main barrier layer of the AlGaN of groove both sides surface, is provided with GaN resilient coating and AlGaN barrier layer successively; On GaN resilient coating of groove floor top and the interface of AlGaN barrier layer, form time two-dimensional electron gas 2DEG layer; GaN resilient coating of groove side surface direction top and AlGaN barrier layer are the AlGaN/GaN heterojunction of non-zero 001, the two-dimensional electron gas 2DEG layer of this heterojunction boundary place formation enhancement mode; On GaN resilient coating of groove both sides and the interface of AlGaN barrier layer, form auxiliary two-dimensional electron gas 2DEG layer;
The upper of described AlGaN barrier layer is source class, leakage level, grid and dielectric layer, this source class and leakage level lay respectively at both sides for AlGaN barrier layer top, grid is positioned at the centre of AlGaN barrier layer top, and dielectric layer is distributed in source class, leaks the region outside level, grid level;
Described auxiliary two-dimensional electron gas 2DEG layer, the Two-dimensional electron gas-bearing formation of enhancement mode and inferior two-dimensional electron gas 2DEG layer, by electron stream through forming the first conducting channel; Described main two-dimensional electron gas 2DEG layer, the two-dimensional electron gas 2DEG layer of enhancement mode and inferior two-dimensional electron gas 2DEG layer, through forming the second conducting channel, make the region of groove both sides be double channel structure by electron stream.
The horizontal level of described two-dimensional electron gas 2DEG layer is lower than the horizontal level of main two-dimensional electron gas 2DEG layer.
The main barrier layer of described AlGaN and AlGaN barrier layer are that doping content is 10 * 10
19cm
-3n-type AlGaN.
For achieving the above object, MS grid enhancement type high electron mobility transistor and the manufacture method of GaN base of the present invention, comprise the steps:
1) in reative cell, substrate surface is carried out to preliminary treatment;
2) the GaN host buffer layer that epitaxial thickness is 1.2um-3.2um on substrate;
3) Al of extension N-type doping on GaN epitaxial loayer
xga
1-xthe main barrier layer of N forms AlGaN/GaN heterogenous junction epitaxy layer, this Al on substrate
xga
1-xthe main barrier layer thickness of N is 15nm-38nm, and 0.18≤x≤0.4;
4) photoetching AlGaN/GaN heterogenous junction epitaxy layer, and adopt reactive ion etching RIE method, on AlGaN/GaN epitaxial loayer, etching shape is grown into 0.5um, the groove that the degree of depth is 40nm-160nm;
5) GaN the resilient coating that is 24nm-120nm by the epitaxial loayer after etching by metal organic chemical vapor deposition MOCVD reative cell secondary epitaxy thickness;
6) adopt the MOCVD technology Al that epitaxial thickness is 15nm-38nm on the GaN of secondary epitaxy layer
xga
1-xn barrier layer, and 0.18≤x≤0.4;
7) at the Al of secondary epitaxy
xga
1-xon N barrier layer, adopt the dielectric layer that plasma-reinforced chemical vapor deposition PECVD method deposition thickness is 1nm-20nm;
8), on dielectric layer, make source, leakage, gate region by lithography, and etching is removed the dielectric layer under window, acquisition source, leakage, grid window;
9) make source, drain region by lithography, adopt the metal of electron beam evaporation technique deposit ohmic contact, the row metal of going forward side by side is peeled off;
10) metal ohmic contact is annealed, formation source, drain contact electrode;
11) make gate region by lithography, and adopt electron beam evaporation technique deposit gate metal, after peeling off, form schottky gate electrode;
12) photoetching has formed the epitaxial wafer of source, leakage, grid, obtains thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, completes element manufacturing.
Described step 2) in, the process conditions of extension GaN host buffer layer are: temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and gallium source flux is 220sccm.
In described step 5), the process conditions of GaN resilient coating of secondary epitaxy are: temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and gallium source flux is 150sccm.
In described step 7), by the process conditions of plasma-reinforced chemical vapor deposition PECVD method dielectric layer deposited, be: ammonia flow is 2.5sccm, nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, and power is 25W.
Tool of the present invention has the following advantages:
1. the present invention is owing to being etched with groove in the middle of GaN host buffer layer, and the bottom surface of groove is 0001 polar surface, groove side is non-zero 001, therefore along non-zero 001 GaN resilient coating of extension in groove side surface direction and the AlGaN/GaN heterojunction structure of AlGaN barrier layer formation, this Structure Decreasing has even been eliminated polarity effect, the two-dimensional electron gas that this heterojunction boundary place is formed is very low, even there is no two-dimensional electron gas, make recess sidewall heterojunction boundary place form the two-dimensional electron gas 2DEG layer of enhancement mode; Simultaneously owing to forming main two-dimensional electron gas 2DEG layer on the GaN host buffer layer in groove both sides and the main barrier layer of AlGaN interface, on GaN resilient coating of groove both sides and AlGaN barrier layer interface, form auxiliary two-dimensional electron gas 2DEG layer, on GaN resilient coating in groove floor and AlGaN barrier layer interface, form time two-dimensional electron gas 2DEG layer, thereby form the first conducting channel during through the two-dimensional electron gas 2DEG layer of auxiliary two-dimensional electron gas 2DEG layer, enhancement mode and inferior two-dimensional electron gas 2DEG layer when electron stream; When electron stream forms the second conducting channel through two-dimensional electron gas 2DEG layer and the inferior two-dimensional electron gas 2DEG layer of main two-dimensional electron gas 2DEG layer, enhancement mode, make the present invention there is double channel conductive mechanism.
2. the present invention is for the first conducting channel, only have when grid applies positive voltage to a certain degree, the two-dimensional electron gas 2DEG layer of the enhancement mode at the inferior resilient coating of groove side and time barrier layer interface could form Two-dimensional electron gas channel, thereby realize the conducting of the first conductive channel, realized the enhancing characteristic of device.
For the second conductive channel, because the inferior GaN resilient coating of groove side diauxic growth is equivalent to one deck separator, only have the grid of working as to apply certain positive voltage, in this GaN separator, form stronger horizontal drift electric field, at this drift field effect lower channel electronics, can realize conducting, thereby form electric current.
Existing AlGaN/GaN HEMT device is due to the existence of high concentration two-dimensional electron gas 2DEG, and when grid voltage is zero even lower negative value, device is all conducting state, thereby is difficult to realize the enhancing of device; And High Electron Mobility Transistor of the present invention is the conducting of the first conducting channel or the conducting of the second conducting channel, all need certain grid positive voltage, so the present invention can realize good enhancing characteristic.
3. the present invention is because the region of the groove both sides of device is double channel structure, and the AlGaN barrier layer of the second conducting channel top adopts even N+ type doping of N-type, not only can greatly reduce the ohmic contact resistance of device, and greatly reduce the series resistance of device source electrode and drain electrode; Simultaneously owing to introducing the conductive mechanism of the second conducting channel, can make electron stream greatly shorten through the distance of the two-dimensional electron gas 2DEG of the enhancement mode of recess sidewall layer, avoided the lower restriction to electric current of two-dimensional electron gas 2DEG layer conductivity of the enhancement mode of recess sidewall, significantly improved the current density of device, made the present invention there is high current density characteristic; In addition because the power line rising from gate electrode can end at the first conducting channel, the main barrier layer of N-type AlGaN, AlGaN barrier layer of N-type and the second conductive channel, power line between grid and raceway groove is disperseed, electric field strength weakens, thereby improved the puncture voltage of device, made the present invention there is high-breakdown-voltage.
4. the processing step in device manufacture method of the present invention is all relatively ripe both at home and abroad at present, and technological process is also relatively simple, and cost is low, can be completely compatible with ripe depletion-mode AlGaN/GaN HEMT device preparation technology.In addition, the present invention has adopted reactive ion etching method to carry out etching, and in follow-up high temperature secondary growth, the surface damage that can form etching is to a certain extent repaired, to reduce the impact of etching injury on device performance and reliability.Compare with current domestic and international conventional groove grid lithographic method, the more effective material damage of having avoided etching to cause of the present invention's energy, device reliability is higher.
Accompanying drawing explanation
Fig. 1 is the MS grid enhancement type high electron mobility transistor structure figure of GaN base of the present invention;
Fig. 2 is the MS grid enhancement type high electron mobility transistor process chart that the present invention prepares GaN base.
Embodiment
With reference to Fig. 1, the MS grid enhancement type high electron mobility transistor of GaN base of the present invention, comprising: substrate 1, transition zone 2, GaN host buffer layer 3, groove 4, the main barrier layer 5 of AlGaN, GaN resilient coating 6, AlGaN barrier layer 7, source class 8, leak level 9, dielectric layer 10, grid 11; Substrate 1 top is transition zone 2; Transition zone 2 tops are GaN host buffer layer 3, and these GaN host buffer layer 3 thickness are 1.2um-3.2um; Groove 4 is etched in the centre of GaN host buffer layer 3, and this groove 4 is long is 0.5um, and the degree of depth is 40nm-160nm, and the bottom surface of groove 4 is 0001 polar surface, and groove 4 sides are non-zero 001; GaN host buffer layer 3 top of groove 4 both sides are the main barrier layer 5 of AlGaN of N-type doping, and the thickness of the main barrier layer 5 of this AlGaN is 15nm-38nm, and doping content is 10 * 10
19cm
-3, and 0.18≤x≤0.4; The main barrier layer of GaN host buffer layer 3 and AlGaN forms main two-dimensional electron gas 2DEG layer 12 on 5 interfaces; In the bottom surface of groove 4 and side surface direction and the main barrier layer of the AlGaN of groove both sides 5 surfaces are GaN resilient coating 6, and the thickness of this GaN time resilient coating 6 is 24nm-120nm; GaN resilient coating 6 tops are AlGaN the barrier layer 7 of N-type doping, and the thickness of this AlGaN time barrier layer 7 is 15nm-38nm, and doping content is 10 * 10
19cm
-3, and 0.18≤x≤0.4; On groove 4 GaN the resilient coatings 6 of top, bottom surface and the interface of AlGaN barrier layer 7, form time two-dimensional electron gas 2DEG layer 13, and the horizontal level of this two-dimensional electron gas 2DEG layer 13 is lower than the horizontal level of main two-dimensional electron gas 2DEG layer 12; On GaN the resilient coating 6 of groove 4 both sides and the interface of AlGaN barrier layer 7, form auxiliary two-dimensional electron gas 2DEG layer 14; GaN resilient coating in groove side surface direction 6 and AlGaN barrier layer 7 are the AlGaN/GaN heterojunction of non-zero 001, the two-dimensional electron gas 2DEG layer of this heterojunction boundary place formation enhancement mode; The upper of AlGaN barrier layer 7 is source class 8, leakage level 9, grid 11 and dielectric layer 10, this source class 8 and leakage level 9 lay respectively at the both sides of AlGaN barrier layer 7 tops, grid 11 is positioned at the centre of AlGaN barrier layer 7 tops, dielectric layer 10 is distributed in source class, leaks the region outside level, grid level, and its thickness is 1nm-20nm; Electron stream through the auxiliary two-dimensional electron gas 2DEG layer 14 in groove left side, the Two-dimensional electron gas-bearing formation of enhancement mode of groove left side wall, the Two-dimensional electron gas-bearing formation of the enhancement mode of inferior two-dimensional electron gas 2DEG layer 13 of groove floor and groove right side wall, the auxiliary two-dimensional electron gas 2DEG layer on groove right side 14 formation the first conducting channels 16; The main two-dimensional electron gas 2DEG layer 12 of electron stream on the left of groove is, the two-dimensional electron gas 2DEG layer of enhancement mode of groove left side wall, the Two-dimensional electron gas-bearing formation of the inferior two-dimensional electron gas 2DEG layer 13 of groove floor and groove right side wall enhancement mode,, the main two-dimensional electron gas 2DEG layer on groove right side 12 forms the second conducting channels 17, make the region of groove 4 both sides be double channel structure.
With reference to Fig. 2, the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base of the present invention, provides following three kinds of embodiment.
Embodiment 1
Being made into GaN host buffer layer thickness is 1.2um, Al
0.4ga
0.6the main barrier layer thickness of N is 15nm, and groove etching depth is 40nm, and GaN buffer layer thickness is 24nm, Al
0.4ga
0.6n barrier layer thickness is 15nm, and the MS grid enhancement type high electron mobility transistor of the GaN base that gate dielectric layer thickness is 1nm, the steps include:
Step 1, the heat treatment of substrate and surfaces nitrided:
Sapphire Substrate is placed in to metal organic chemical vapor deposition MOCVD reative cell, the vacuum degree of reative cell is evacuated to 1 * 10
-2under Torr, under the ammonia that the hydrogen that is 1500sccm and flow are 2000sccm mixed gas protected, Sapphire Substrate is heat-treated with surfaces nitrided at flow, heating-up temperature is 1050 ℃, and pressure is 20Torr.
Step 2, extension AlN transition zone:
Adopt MOCVD technology, in temperature, it is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, ammonia flow is 2000sccm, aluminium source flux is under the process conditions of 30sccm, through heat treatment and surfaces nitrided after epitaxial thickness is 150nm in Sapphire Substrate AlN transition zone, as Fig. 2 (a).
Step 3, extension GaN host buffer layer:
Adopting MOCVD technology, is 1050 ℃ in temperature, and pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, under the process conditions that gallium source flux is 220sccm, the GaN host buffer layer that epitaxial thickness is 1.2um on AlN transition zone, as Fig. 2 (b).
Step 4, the Al of extension N-type doping
0.4ga
0.6the main barrier layer of N:
Adopting MOCVD technology, is 920 ℃ in temperature, and pressure is 40Torr, hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and aluminium source flux is 10sccm, gallium source flux is under the process conditions of 40sccm, the N-type doped with Al that epitaxial thickness is 15nm on host buffer layer
0.4ga
0.6the main barrier layer of N, by passing into silane SiH in growth course
4realizing doping content is 10 * 10
19cm
-3n-type doping, on AlN transition zone, formed like this AlGaN/GaN heterojunction, in matter junction interface, place has formed two-dimensional electron gas 2DEG, the epitaxial slice structure of formation is as Fig. 2 (c).
Step 5, deposit SiO
2layer mask layer:
After epitaxial wafer is cleaned, adopt the electron beam evaporation equipment SiO that deposition thickness is 150nm on epitaxial wafer
2layer, as Fig. 2 (d), this SiO
2layer can form on epitaxial wafer surface the bilayer mask figure jointly shielding with photoresist, is more conducive to the not protection on etch areas surface.
Step 6, photoetching etching form groove structure:
In deposit SiO
2on the epitaxial wafer surface of layer, by positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method, at chlorine Cl
2flow is 15sccm, and power is 200W, etching epitaxial wafer under the process conditions that pressure is 10mT, and etching depth is 40nm, forms groove structure, as Fig. 2 (e).
Step 7, removes photoresist and removes SiO
2mask layer:
With acetone soln, remove after etching remaining positive glue on epitaxial wafer, then the SiO of deposit in corrosion step five in HF solution
2mask, finally cleans and dries up with nitrogen with ultra-pure water.
Step 8, the heat treatment of epitaxial wafer and surfaces nitrided:
The vacuum degree of reative cell is evacuated to 1 * 10
-2under Torr, the mixed gas protected lower of the ammonia that the hydrogen that is 1500sccm at flow and flow are 2000sccm heat-treated the epitaxial wafer after cleaning, and heating-up temperature is 1000 ℃, and pressure is 20Torr.
Step 9, GaN resilient coating of secondary epitaxy:
Utilizing MOCVD technology, is 1050 ℃ in temperature, and pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, under the process conditions that gallium source flux is 150sccm, GaN the resilient coating that epitaxial thickness is 24nm on epitaxial wafer, as Fig. 2 (f).
Step 10, secondary epitaxy Al
0.4ga
0.6n barrier layer:
Utilize MOCVD technology, adopting temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and aluminium source flux is 10sccm, the process conditions that gallium source flux is 40sccm, and in growth course, pass into silane SiH
4realizing doping content is 10 * 10
19cm
-3n-type doping, the N-type doped with Al that extension formation thickness is 15nm on GaN resilient coating
0.4ga
0.6n barrier layer, like this in groove floor and the Al of groove both sides
0.4ga
0.6n barrier layer and GaN resilient coating have formed AlGaN/GaN heterojunction, and this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay the epitaxial slice structure of formation outward as Fig. 2 (g).
Step 11, deposit SiN dielectric layer:
Utilize plasma-reinforced chemical vapor deposition PECVD method, at ammonia flow, be 2.5sccm, nitrogen flow is 900sccm, silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, power is under the process conditions of 25W, deposition thickness is the SiN dielectric layer of 1nm, and this dielectric layer covers whole groove, as Fig. 2 (h).
Step 12, makes source, ornamental perforated window mouth by lithography:
12a) by positive-glue removing, soft baking, exposure and development, the photoetching window of formation source, leakage, grid, and adopt wet etching method to remove the SiN dielectric film under source, leakage, gate region.
12a) to having removed the epitaxial wafer of the SiN dielectric film under source, leakage, gate region, carry out positive-glue removing, soft baking, exposure and development acquisition source, drain region window, and utilize plasma degumming machine to remove the photoresist thin layer that window area does not develop clean, to improve the rate of finished products of metal-stripping.
Step 13, evaporation metal ohmic contact:
Adopt electron beam evaporation instrument, in vacuum degree, be less than 2.0 * 10
-6pa, power bracket is 600W, and evaporation rate is not more than under the process conditions of 3 dust/seconds evaporates Ti, Al, Ni, tetra-layers of metal ohmic contact of Au, and the thickness of Ti, Al, Ni, Au is respectively 30nm, 180nm, 40nm, 60nm.
Step 14, metal-stripping also carries out ohmic contact annealing:
First the epitaxial wafer that is evaporated metal ohmic contact is soaked to 20min in acetone soln, then carry out ultrasonic cleaning, then ultra-pure water flushing and nitrogen dry up, to realize peeling off of metal, the last ohmic contact annealing of carrying out 30s in nitrogen atmosphere, at the temperature of 850 ℃, Cheng Yuan, drain contact electrode, as Fig. 2 (i).
Step 15, makes grid window by lithography:
On epitaxial wafer after annealing, carry out positive-glue removing, soft baking, exposure and develop obtaining grid window.
Step 10 six, evaporation grid metal:
Adopt electron beam evaporation instrument, deposit Ni, Au double layer of metal, the thickness of Ni, Au is respectively 30nm, 200nm, subsequently device is immersed in stripper and carries out metal-stripping, then with ultra-pure water, rinse 2min, last nitrogen dries up, the final gate electrode that obtains, as Fig. 2 (j).
Step 10 seven, completes element manufacturing:
Photoetching has formed the epitaxial wafer of source, leakage, grid, obtains thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, completes element manufacturing as shown in Figure 1.
Embodiment 2
Being made into GaN host buffer layer thickness is 2.5um, Al
0.3ga
0.7the main barrier layer thickness of N is 28nm, and groove etching depth is 100nm, and GaN buffer layer thickness is 70nm, Al
0.3ga
0.7n barrier layer thickness is 28nm, and the MS grid enhancement type high electron mobility transistor of the GaN base that gate dielectric layer thickness is 10nm, the steps include:
Step 1 is identical with the step 1 of embodiment 1.
Step 2 is identical with the step 2 of embodiment 1.
Step 3, adopt the MOCVD technology GaN host buffer layer that epitaxial thickness is 2.5um on AlN transition zone, as Fig. 2 (b), the process conditions that extension adopts are: temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and gallium source flux is 220sccm.
Step 4, adopts the N-type doped with Al that MOCVD technology epitaxial thickness on host buffer layer is 28nm
0.3ga
0.7the main barrier layer of N, on AlN transition zone, formed like this AlGaN/GaN heterojunction, in matter junction interface, place has formed two-dimensional electron gas 2DEG, and the epitaxial slice structure of formation is as Fig. 2 (c), and the process conditions that extension adopts are: temperature is 920 ℃, pressure is 40Torr, hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and aluminium source flux is 10sccm, gallium source flux is 40sccm, and by pass into silane SiH in growth course
4realizing doping content is 10 * 10
19cm
-3n-type doping.
Step 5 is identical with the step 5 of embodiment 1.
Step 6, in deposit SiO
2on the epitaxial wafer surface of layer, by positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method etching epitaxial wafer, etching depth is 100nm, form groove structure as Fig. 2 (e), the process conditions that etching adopts are: chlorine Cl
2flow is 15sccm, and power is 200W, under the process conditions that pressure is 10mT.
Step 7 is identical with the step 7 of embodiment 1.
Step 8 is identical with the step 8 of embodiment 1.
Step 9, utilizes MOCVD technology, GaN the resilient coating of epitaxial thickness 70nm on epitaxial wafer, as Fig. 2 (f), the process conditions that extension adopts are: temperature is 1050 ℃, and pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and gallium source flux is 150sccm.
Step 10, utilizes MOCVD technology, and on GaN resilient coating, extension forms the N-type doped with Al that thickness is 28nm
0.3ga
0.7n barrier layer, like this in groove floor and the Al of groove both sides
0.3ga
0.7n barrier layer and GaN resilient coating have formed AlGaN/GaN heterojunction, this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay the epitaxial slice structure of formation outward as Fig. 2 (g), the process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm, ammonia flow is 5000sccm, aluminium source flux is 10sccm, and gallium source flux is 40sccm, and in growth course, passes into silane SiH
4realizing doping content is 10 * 10
19cm
-3n-type doping.
Step 11, utilize plasma-reinforced chemical vapor deposition PECVD method, deposition thickness is the SiN dielectric layer of 10nm, and this dielectric layer covers whole groove, as Fig. 2 (h), the process conditions that deposit adopts are: ammonia flow is 2.5sccm, nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, pressure is 900mT, and power is 25W.
Step 12 is identical with the step 12 of embodiment 1.
Step 13 is identical with the step 13 of embodiment 1.
Step 14 is identical with the step 14 of embodiment 1.
Step 15 is identical with the step 15 of embodiment 1.
Step 16 is identical with the step 10 six of embodiment 1.
Step 17 is identical with the step 10 seven of embodiment 1.
Embodiment 3
Being made into GaN host buffer layer thickness is 3.2um, Al
0.18ga
0.82the main barrier layer thickness of N is 38nm, and groove etching depth is 160nm, and GaN buffer layer thickness is 120nm, Al
0.18ga
0.82n barrier layer thickness is 38nm, and the MS grid enhancement type high electron mobility transistor of the GaN base that gate dielectric layer thickness is 20nm, the steps include:
Steps A is identical with the step 1 of embodiment 1.
Step B is identical with the step 2 of embodiment 1.
Step C, adopting temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, the process conditions that gallium source flux is 220sccm, by MOCVD technology, the GaN host buffer layer that epitaxial thickness is 3.2um on AlN transition zone, as Fig. 2 (b).
Step D, adopting temperature is 920 ℃, pressure is 40Torr, hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and aluminium source flux is 10sccm, gallium source flux is the process conditions of 40sccm, by MOCVD technology, and the N-type doped with Al that epitaxial thickness is 38nm on host buffer layer
0.18ga
0.82the main barrier layer of N, by passing into silane SiH in growth course
4realizing doping content is 10 * 10
19cm
-3n-type doping, on AlN transition zone, formed like this AlGaN/GaN heterojunction, in matter junction interface, place has formed two-dimensional electron gas 2DEG, the epitaxial slice structure of formation is as Fig. 2 (c).
Step e is identical with the step 5 of embodiment 1.
Step 6, in deposit SiO
2on the epitaxial wafer surface of layer, by positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method, at chlorine Cl
2flow is 15sccm, and power is 200W, etching epitaxial wafer under the process conditions that pressure is 10mT, and etching depth is 160nm, forms groove structure, as Fig. 2 (e).
Step F is identical with the step 7 of embodiment 1.
Step G is identical with the step 8 of embodiment 1.
Step H, is 1050 ℃ in temperature, and pressure is 20Torr, hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, under the process conditions that gallium source flux is 150sccm, by MOCVD technology, GaN the resilient coating of epitaxial thickness 120nm on epitaxial wafer, as Fig. 2 (f).
Step I, adopting temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, aluminium source flux is 10sccm, the process conditions that gallium source flux is 40sccm, and in growth course, pass into silane SiH
4realizing doping content is 10 * 10
19cm
-3n-type doping, utilize MOCVD technology, the N-type doped with Al that extension formation thickness is 38nm on GaN resilient coating
0.18ga
0.82n barrier layer, like this in groove floor and the Al of groove both sides
0.18ga
0.82n barrier layer and GaN resilient coating have formed AlGaN/GaN heterojunction, and this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay the epitaxial slice structure of formation outward as Fig. 2 (g).
Step J, at ammonia flow, be 2.5sccm, nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, pressure is 900mT, power is under the process conditions of 25W, utilizes plasma-reinforced chemical vapor deposition PECVD method, the SiN dielectric layer that deposition thickness is 20nm, this dielectric layer covers whole groove, as Fig. 2 (h).
Step K is identical with the step 12 of embodiment 1.
Step L is identical with the step 13 of embodiment 1.
Step M is identical with the step 14 of embodiment 1.
Step N is identical with the step 15 of embodiment 1.
Step O is identical with the step 10 six of embodiment 1.
Step P is identical with the step 10 seven of embodiment 1.
Above-described embodiment is several preferred embodiment of the present invention only; do not form any limitation of the invention; obviously for those skilled in the art; after having understood content of the present invention and principle; can be in the situation that not deviating from the principle and scope of the present invention; the method according to this invention is carried out various corrections and the change in form and details, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (6)
1. a MS grid enhancement type high electron mobility transistor for GaN base, comprises: substrate (1), transition zone (2) and GaN host buffer layer (3), is characterized in that from bottom to top:
The centre of GaN host buffer layer (3) is etched with groove (4), the bottom surface of this groove (4) is 0001 polar surface, groove (4) side is non-zero 001, GaN host buffer layer (3) top of groove (4) both sides is the main barrier layer of AlGaN (5), on GaN host buffer layer (3) and the main barrier layer of AlGaN (5) interface, forms main two-dimensional electron gas 2DEG layer (12);
The main barrier layer of AlGaN (5) surface of in the bottom surface of groove (4) and side surface direction and groove both sides, is provided with GaN resilient coating (6) and AlGaN barrier layer (7) successively; On GaN the resilient coating (6) of groove floor top and the interface of AlGaN barrier layer (7), form time two-dimensional electron gas 2DEG layer (13); GaN resilient coating (6) in groove side surface direction and AlGaN barrier layer (7) are the AlGaN/GaN heterojunction of non-zero 001, and this heterojunction boundary place forms the two-dimensional electron gas 2DEG layer of enhancement mode; On GaN the resilient coating (6) of groove both sides and the interface of AlGaN barrier layer (7), form auxiliary two-dimensional electron gas 2DEG layer (14);
Described AlGaN barrier layer (7) is upper is source class (8), leakage level (9), grid (11) and dielectric layer (10), this source class (8) and leakage level (9) lay respectively at the both sides of AlGaN barrier layer (7) top, grid (11) is positioned at the centre of AlGaN barrier layer (7) top, and dielectric layer (10) is distributed in source class, leaks the region outside level, grid level;
Described auxiliary two-dimensional electron gas 2DEG layer (14), the Two-dimensional electron gas-bearing formation of enhancement mode and inferior two-dimensional electron gas 2DEG layer (13), by electron stream through forming the first conducting channel (16); Described main two-dimensional electron gas 2DEG layer (12), the two-dimensional electron gas 2DEG layer of enhancement mode and inferior two-dimensional electron gas 2DEG layer (13), by electron stream, through forming the second conducting channel (17), make the region of groove (4) both sides be double channel structure;
It is 10 * 10 that the main barrier layer of described AlGaN (5) and AlGaN barrier layer (7) are doping content
19cm
-3n-type AlGaN.
2. enhancement type high electron mobility transistor according to claim 1, is characterized in that, the horizontal level of inferior two-dimensional electron gas 2DEG layer (13) is lower than the horizontal level of main two-dimensional electron gas 2DEG layer (12).
3. a manufacture method for the MS grid enhancement type high electron mobility transistor of GaN base as claimed in claim 1, comprises the following steps:
1) in reative cell, substrate surface is carried out to preliminary treatment;
2) the GaN host buffer layer that epitaxial thickness is 1.2um-3.2um on substrate;
3) Al of extension N-type doping on GaN epitaxial loayer
xga
1-xthe main barrier layer of N forms AlGaN/GaN heterogenous junction epitaxy layer, this Al on substrate
xga
1-xthe main barrier layer thickness of N is 15nm-38nm, and 0.18≤x≤0.4;
4) photoetching AlGaN/GaN heterogenous junction epitaxy layer, and adopt reactive ion etching RIE method, on AlGaN/GaN epitaxial loayer, etching shape is grown into 0.5um, the groove that the degree of depth is 40nm-160nm;
5) GaN the resilient coating that is 24nm-120nm by the epitaxial loayer after etching by metal organic chemical vapor deposition MOCVD reative cell secondary epitaxy thickness;
6) adopt MOCVD technology at the GaN of secondary epitaxy
inferior bufferingthe Al that on layer, epitaxial thickness is 15nm-38nm
xga
1-xn barrier layer, and 0.18≤x≤0.4;
7) at the Al of secondary epitaxy
xga
1-xon N barrier layer, adopt the dielectric layer that plasma-reinforced chemical vapor deposition PECVD method deposition thickness is 1nm-20nm;
8), on dielectric layer, make source, leakage, gate region by lithography, and etching is removed the dielectric layer under window, acquisition source, leakage, grid window;
9) make source, drain region by lithography, adopt the metal of electron beam evaporation technique deposit ohmic contact, the row metal of going forward side by side is peeled off;
10) metal ohmic contact is annealed, formation source, drain contact electrode;
11) make gate region by lithography, and adopt electron beam evaporation technique deposit gate metal, after peeling off, form schottky gate electrode;
12) photoetching has formed the epitaxial wafer of source, leakage, grid, obtains thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, completes element manufacturing.
4. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 2) in, the process conditions of extension GaN host buffer layer are: temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, ammonia flow is 6000sccm, and gallium source flux is 220sccm.
5. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 5) in, the process conditions of GaN resilient coating of secondary epitaxy are: temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, ammonia flow is 3000sccm, and gallium source flux is 150sccm.
6. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 7) in, by the process conditions of plasma-reinforced chemical vapor deposition PECVD method dielectric layer deposited, be: ammonia flow is 2.5sccm, nitrogen flow is 900sccm, silane flow rate is 200sccm, temperature is 300 ℃, and pressure is 900mT, and power is 25W.
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| CN105140280B (en) * | 2015-07-27 | 2017-12-01 | 西南交通大学 | A kind of high pressure Multiple heterostructures device with normal Pass Ravine road |
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| US11316038B2 (en) | 2018-11-20 | 2022-04-26 | Stmicroelectronics S.R.L. | HEMT transistor with adjusted gate-source distance, and manufacturing method thereof |
| TWI701840B (en) * | 2019-08-14 | 2020-08-11 | 新唐科技股份有限公司 | Enhancement mode hemt device |
| CN111463259B (en) * | 2020-03-10 | 2022-09-13 | 安徽长飞先进半导体有限公司 | High electron mobility field effect transistor and preparation method thereof |
| US11721743B2 (en) * | 2020-12-22 | 2023-08-08 | Applied Materials, Inc. | Implantation enabled precisely controlled source and drain etch depth |
| CN115810663A (en) * | 2021-09-14 | 2023-03-17 | 联华电子股份有限公司 | High electron mobility transistor and manufacturing method thereof |
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| CN102130160A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof |
| CN102203936A (en) * | 2009-07-30 | 2011-09-28 | 住友电气工业株式会社 | Semiconductor device and method for manufacturing same |
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| CN102203936A (en) * | 2009-07-30 | 2011-09-28 | 住友电气工业株式会社 | Semiconductor device and method for manufacturing same |
| CN102130160A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof |
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| JP特开2011-222768A 2011.11.04 |
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