CN105140280B - A kind of high pressure Multiple heterostructures device with normal Pass Ravine road - Google Patents
A kind of high pressure Multiple heterostructures device with normal Pass Ravine road Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
Abstract
The present invention relates to the heterojunction device of the novel enhanced mechanism of Power Electronic Technique, more particularly to a kind of high pressure Multiple heterostructures device with normal Pass Ravine road, the Multiple heterostructures type of the present invention often closes channel device, mainly pass through the 3rd semiconductor layer, 4th semiconductor layer, 5th semiconductor layer, 6th semiconductor layer forms Multiple heterostructures, side has nonplanar structure under the gate, the polarised direction of nonplanar hetero-junctions raceway groove and the 3rd semiconductor layer, 4th semiconductor layer, there is certain angle in the Material growth direction of 5th semiconductor layer and the 6th semiconductor layer, realize that the two-dimensional electron gas (2DEG) of heterojunction boundary is discontinuous, non- closed type electrical connection is formd between source and drain, finally realize that Multiple heterostructures often close channel device.Beneficial effects of the present invention are that Multiple heterostructures often close channel device, steady operation, domain and technique can be easily achieved under high temperature high field environments, and the threshold voltage in easily controllable often Pass Ravine road.
Description
Technical field
The present invention relates to the normal Pass Ravine road realization principle of semiconductor technology, particularly Multiple heterostructures and realize technology of preparing.
Background technology
III-V semi-conducting materials in third generation semiconductor have that energy gap is big, electron saturation velocities are high, breakdown electric field
High, the features such as heat conductivility and corrosion resistance are strong, such as GaN, AlN, in terms of electronic device, III-V material is more suitable than silicon
Together in making high temperature resistant, high frequency, High-Field and large-power semiconductor device.
It is stronger due to existing in iii-v heterojunction structure when preparing the electronic device of iii-v heterojunction structure
Two-dimensional electron gas, such as the HEMT (HEMTs) of AlGaN/GaN hetero-junctions, it is all depletion device to be mostly,
And be then not easy to realize for the electronic device of enhanced iii-v hetero-junctions, and in high-frequency element, device for power switching and numeral
In many cases it is desirable that enhancement device in circuit, so to enhanced iii-v hetero-junctions.
Realizing the method for the HEMT (HEMTs) of enhanced iii-v hetero-junctions mainly has：(1) p-type
The enhanced HEMTs of cap layers；(2) the enhanced HEMTs of recessed barrier layer；(3) the enhanced HEMTs of double potential barrier layer；(4) insulated gate electrode is heterogeneous
Junction transistors；(5) fluorine ion injects enhanced HEMTs etc..
A kind of device of enhanced AlGaN/GaN single heterojunctions is proposed in the A of Publication No. CN 103715086 Chinese patent
Part, at least one on-plane surface single heterostructure of the devices use so that the polarised direction and Material growth of III-V material
Crystal orientation has certain angle, and then weakens the electric field that can produce two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG), Jin Ershi
Existing enhancement device.But because III-V growth materials grow more complicated, the shape such as making groove, projection and step from substrate
Formula, it is then than control relatively difficult to achieve by epitaxial growth on-plane surface single heterojunction raceway groove.In real technique, Multiple heterostructures
Device is easier to realize, and flexible and changeable.
The content of the invention
As described in the background art, by making the forms such as groove, projection and step in the substrate, extension is then passed through
The mode of growth, the shape of substrate is transferred to channel layer so that the area of grid of channel layer forms nonplanar structure, and utilization is non-
The forms such as the non-polar plane of planar structure, semi-polarity face realize the interruption of two-dimensional electron gas, so as to realize enhancement device.But
From present technology, the technique that the shape of substrate is transferred to channel layer by several layers of deposition growings is unusual complicated difficult
Control, and the non-polar plane of nonplanar single heterojunction or semi-polarity face mode are than relatively difficult to achieve.
Therefore, the invention discloses a kind of enhancement device, the enhancement device to realize pinch off two-dimensional electron gas or two dimension
It according to Group III-V semiconductor is a kind of characteristic of polar semiconductor that the principle of hole gas, which is,.Such as wurtzite structure iii-v chemical combination
In thing, in crystal orientation [0001] orAlGaN/GaN hetero-junctions, even if undoping, on the GaN faces of the hetero-junctions
Very high two-dimensional electron gas (2DEG) can be produced.As shown in figure 1, piezoelectric polarization σi’j’=Ci’j’k’m’εk’m’, wherein Ci’j’k’m’For
Elastic stiffness coefficient, εk’m’For the coefficient of strain, when forming hetero-junctions, piezoelectric polarization σi’j’C can be passed throughi’j’k’m’、εk’m’In crystalline substance
Upward value is tried to achieve, and as shown in Figure 1a, when taking the crystal orientation of (10-11)-plane, a- planes and r- planes, can be obtained not
Same piezoelectric polarization electric field, in multiheterostructure, piezoelectric polarization electric field is to the two-dimensional electron gas (2DEG) at heterojunction boundary
With adjustment effect, piezoelectric electro field strength, two-dimensional electron gas is easier to gather, and piezoelectric field is weak, gathers the energy of two-dimensional electron gas
Power weakens；As shown in Figure 1 b, in AlGaN and GaN along [0001] andThe spontaneous polarization electric field of crystal orientation be it is most strong,
And when AlGaN potential barrier than it is relatively thin when, the two-dimensional electron gas of AlGaN/GaN heterojunction boundaries is mainly that spontaneous polarization electric field causes
, thus in crystal orientation [0001] andOn hetero-junctions caused by two-dimensional electron gas (2DEG) be most strong, and along crystalline substance
To with crystal orientation [0001] andWhen having the AlGaN/GaN hetero-junctions of certain angle, (10-11)-plane, a- such as Fig. 1 b are put down
Face and r- planes, spontaneous polarization electric field can weaken, notably when along crystal orientation and crystal orientation [0001] andIt is heterogeneous when vertical
During knot, there is no spontaneous polarization electric field；The present invention forms Multiple heterostructures by being different from the growth plane of c- planes, non-by adjusting
Piezoelectric polarization electric field and spontaneous polarization electric field at the Material growth crystal orientation regulation heterojunction boundary of plane Multiple heterostructures so that boundary
The conduction band of SQW is more than fermi level at face, so as to be difficult to form Two-dimensional electron at on-plane surface Multiple heterostructures channel interface
Gas.
To achieve these goals, technical scheme provided by the invention is as follows：A kind of high pressure polyisocyanate with normal Pass Ravine road
Matter junction device, including the first semiconductor substrate layer 201, the second semiconductor buffer layer the 202, the 3rd half set gradually from the bottom up
Conductor layer 203, the 4th semiconductor layer 204 and the 5th semiconductor layer 205；The both ends upper surface of 4th semiconductor layer 204 point
The first Ohmic contact 101 and the second Ohmic contact 103 are not provided with；There is metal electrode on 5th semiconductor layer 205
102；3rd semiconductor layer 203 and the 4th semiconductor layer 204 contact interface formed the first hetero-junctions, the described the 4th half
The semiconductor layer 205 of conductor layer 204 and the 5th forms the second hetero-junctions in contact interface；Characterized in that, the metal electrode 102
Lower section has the on-plane surface hetero-junctions for making that Two-dimensional electron gas channel interrupts immediately below it.
Further, as shown in Fig. 2 the on-plane surface hetero-junctions is to pass through the 4th half by the 5th semiconductor layer 205 is recessed
Conductor layer 204 is connected to be formed with the upper surface of the 3rd semiconductor layer 203；5th semiconductor layer 205 and metal electrode 102 it
Between form groove, the metal electrode 102 is filled in a groove；Have between 5th semiconductor layer 205 and metal electrode 102
There is the 6th semiconductor layer 206.
Further, the both ends of the 6th semiconductor layer 206 connect with the first Ohmic contact 101 and second ohm respectively
Touch 103 connections；Also there is the 7th semiconductor layer 207 between 6th semiconductor layer 206 and metal electrode 102；Described 7th
The both ends of semiconductor layer 207 are connected with the first Ohmic contact 101 and the second Ohmic contact 103 respectively.
Further, first semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；Described
Second based semiconductor 202 is one kind in SiC, AlN, GaN, AlGaN；3rd semiconductor layer 203, the 4th semiconductor layer
204th, the 5th semiconductor layer 205, the 6th semiconductor layer 206 and the 7th semiconductor layer 207 are III-V；Described
The electrode material of one Ohmic contact 101 and the second Ohmic contact 103 is one or more groups in gold, silver, aluminium, titanium, platinum and indium
Close；The material of described metal electrode 102 is one or more groups in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum and indium
Close.
A kind of high pressure Multiple heterostructures device with normal Pass Ravine road, including the first semiconductor lining set gradually from the bottom up
Bottom 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203 and the 4th semiconductor layer 204；3rd semiconductor layer
203 both ends upper surface is respectively arranged with the first Ohmic contact 101 and the second Ohmic contact 103；4th semiconductor layer 204
It is upper that there is metal electrode 102；3rd semiconductor layer 203 is heterogeneous in contact interface formation first with the 4th semiconductor layer 204
Knot；Make the on-plane surface that Two-dimensional electron gas channel interrupts immediately below it heterogeneous characterized in that, the lower section of metal electrode 102 has
Knot.
Further, the 4th based semiconductor layer 204 is made up of bending side and horizontal plane；4th semiconductor layer
On-plane surface hetero-junctions is formed at 204 bending side；Under the bending side of 4th semiconductor layer 204 is located at metal electrode 102 just
Side.
Further, the bending side of the 4th semiconductor layer 204 is to be folded upward at, the 4th semiconductor layer 204
The shape of cross section between lower surface and the upper surface of the 3rd semiconductor layer 203 at bending side is trapezoidal, the trapezoidal bottom
Width is more than upper bottom edge width, the 3rd semiconductor layer 203 be filled in it is trapezoidal in and with the bending side of the 4th semiconductor layer 204
Lower surface connection；Also there is the 5th semiconductor layer 205 between 4th semiconductor layer 204 and metal electrode 102, described
Five semiconductor layers 205 are completely covered on the upper surface of the 4th semiconductor layer 204；The metal electrode 102 is covered in the 5th half and led
The upper surface of the bending side part of body layer 205.
Further, the bending side of the 4th semiconductor layer 204 is to be folded upward at, the 4th semiconductor layer 204
The shape of cross section between lower surface and the upper surface of the 3rd semiconductor layer 203 at bending side is trapezoidal, the trapezoidal bottom
Width is more than upper bottom edge width；It is described it is trapezoidal in be filled with the 8th semiconductor layer 208, the 8th semiconductor layer 208 and the 4th
The junction of semiconductor layer forms the second hetero-junctions；The metal electrode 102 is covered in the bending side of the 4th semiconductor layer 204
Upper surface.
Further, the bending side of the 4th semiconductor layer 204 is to be folded upward at, the 4th semiconductor layer 204
The shape of cross section between lower surface and the upper surface of the 3rd semiconductor layer 203 at bending side is trapezoidal, the trapezoidal bottom
Width is more than upper bottom edge width；3rd semiconductor layer 203 be filled in it is trapezoidal in；The metal electrode 102 is vertical by first
Face, the second vertical plane and plane are formed；The plane of the metal electrode 102 is mutually flat with the horizontal plane of the 4th semiconductor layer 204
OK；The plane of the metal electrode 102 connects with the second vertical plane of the first vertical plane of metal electrode 102 and metal electrode 102
Connect to form inverted U-shaped；The plane of the metal electrode 102 and the first vertical plane of metal electrode 102 and metal electrode 102
Second vertical plane is mutually perpendicular to；First vertical plane lower surface of the metal electrode 102 and the bending side of the 4th semiconductor layer 204
The horizontal plane upper surface connection of side, its upper surface is connected with plane one end lower surface of metal electrode 102；The metal electrode
102 the second vertical plane lower surface is connected with the upper surface of the bending side opposite side horizontal plane of the 4th semiconductor layer 204, its upper table
Face is connected with the plane other end lower surface of metal electrode 102；The plane of the metal electrode 102 and the 4th semiconductor layer 204
There is the tenth semiconductor layer 210 between the upper bottom surface surface of bending side；Tenth semiconductor layer 210, metal electrode 102 hang down
Face directly, there is the 9th semiconductor layer 209 between the level of metal electrode 102 and the bending side of the 4th semiconductor layer 204.
Further, the bending side of the 4th semiconductor layer 204 is the 204 recessed formation of the 4th semiconductor layer, described
Shape of cross section between the bending place upper surface of four semiconductor layer 204 and the horizontal plane of the 4th semiconductor layer 204 is trapezoidal, and this is trapezoidal
Bottom width be more than upper bottom edge width；The metal electrode 102 is made up of plane and vertical plane, the metal electrode 102
The upper surface of plane lower surface and the 4th semiconductor layer 204 be generally aligned in the same plane, the vertical plane of metal electrode 102 is arranged on ladder
In shape bending side；The plane of metal electrode 102 and the vertical plane of metal electrode 102 are orthogonal to form T-type structure；The metal
There is the tenth semiconductor layer 210, it bends with trapezoidal shape between the vertical plane of electrode 102 and the upper surface of the 4th semiconductor layer 204
There is the 9th semiconductor layer 209 between the side of surface side.
Further, first semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；Described
Second based semiconductor 202 is one kind in SiC, AlN, GaN, AlGaN；3rd semiconductor layer 203, the 4th semiconductor layer
204th, the 8th semiconductor layer 208, the 9th semiconductor layer 209 and the tenth semiconductor layer 210 are III-V；Described
The electrode material of one Ohmic contact 101 and the second Ohmic contact 103 is the one or more in gold, silver, aluminium, titanium, platinum and indium
Combination, the material of the metal electrode 102 are one or more groups in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum and indium
Close.
Because this enhancement device is when making, the methods of being by etching, depositing the metal electrode on channel layer
The on-plane surface multiheterostructure that region is formed, technique are relatively easily realized, and the on-plane surface Multiple heterostructures formed are more flexible
It is changeable.
Brief description of the drawings
Fig. 1 is the lattice structure schematic diagram of III-V；
Wherein Fig. 1 (a) is the wurtzite structure figure of III-V, and Fig. 1 (b) is the buergerite of III-V
The lattice structure figure of structure；
Fig. 2 is a kind of structural representation of the embodiment 1 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 3 is a kind of structural representation of the embodiment 2 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 4 is a kind of structural representation of the embodiment 3 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 5 is a kind of structural representation of the embodiment 4 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 6 is a kind of structural representation of the embodiment 5 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 7 is a kind of structural representation of the embodiment 6 of high pressure Multiple heterostructures device with normal Pass Ravine road of the present invention；
Fig. 8 be the present invention a kind of high pressure Multiple heterostructures device making technics flow with normal Pass Ravine road on substrate
Deposit schematic diagram after the second based semiconductor, the 3rd semiconductor layer and the 4th semiconductor layer material；
Fig. 9 is to be etched in a kind of high pressure Multiple heterostructures element manufacturing flow with normal Pass Ravine road of the present invention on device
4th semiconductor layer material forms structural representation after groove；
Figure 10 is to be led in a kind of high pressure Multiple heterostructures element manufacturing flow with normal Pass Ravine road of the present invention the 4th half
The structural representation being sequentially depositing on body layer after the 5th semiconductor layer, the 6th semiconductor layer and the 7th semiconductor layer material；
Figure 11 is to be led in a kind of high pressure Multiple heterostructures element manufacturing flow with normal Pass Ravine road of the present invention the 4th half
Body layer both ends make the structural representation after Ohmic contact；
A kind of high pressure Multiple heterostructures device with normal Pass Ravine road that Figure 12 is the present invention is completed on the 7th semiconductor layer
The schematic diagram of metal electrode deposition.
Embodiment
Embodiment 1
A kind of high pressure heterojunction device in the often Pass Ravine road of this example, as shown in Fig. 2 including set gradually from the bottom up the
Semi-conductive substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 5th half
Conductor layer 205, the 6th semiconductor layer 206；The both ends of 4th semiconductor layer 204 are respectively arranged with the first Ohmic contact 101
With the second Ohmic contact 103；There is metal electrode 102, metal electrode 102 is in the first Europe on the 6th described semiconductor layer 206
Between nurse contact 101 and the second Ohmic contact 103；The junction shape of 3rd semiconductor layer 203 and the 4th semiconductor layer 204
Into the first hetero-junctions, the junction of the 4th semiconductor layer 204 and the 5th semiconductor layer 205 forms the second hetero-junctions, described
The junction of 5th semiconductor layer 205 and the 3rd semiconductor layer 203 forms the 3rd hetero-junctions, the 5th semiconductor layer 205 and the 6th
The junction of semiconductor layer 206 forms the 4th hetero-junctions；The hetero-junctions of 5th semiconductor layer 205 and the 6th semiconductor layer 206
Self poling electric field is opposite with the self poling electric field of the 4th semiconductor layer 204 and the hetero-junctions of the 5th semiconductor layer and in metal electrode
102 on-plane surface Multiple heterostructures formed below.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Five semiconductor layers 205, the 6th semiconductor layer 206 are mainly the described in GaN, InN, AlGaN, InGaN, InAlGaN or AlN
The electrode material of one Ohmic contact 101 and the second Ohmic contact 103 includes one kind or more in gold, silver, aluminium, titanium, platinum or indium
Kind combination；The material of described metal electrode 102 includes one kind in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum or indium
Or multiple combinations.
A kind of principle of high pressure Multiple heterostructures device with normal Pass Ravine road of embodiment 1, is by metal electrode 102
The 3rd semiconductor layer 203, the 4th semiconductor layer 204, the 5th semiconductor layer 205, the 6th semiconductor layer 206 of lower section form non-flat
The trapezoidal groove multiheterostructure in face；Semiconductor in the upper and lower surface and device of groove in addition to projection is along crystalline substance
To [0001] or crystal orientationDeposition growing, the 4th semiconductor layer the 204, the 5th half of the groove side being made up of bending segment
The semiconductor layer 206 of conductor layer 205 and the 6th be along with crystal orientation [0001] or crystal orientationThere is certain angle deposition growing；
Along [0001] orWhen the Group III-V semiconductor of direction growth forms hetero-junctions, the polarized electric field of heterojunction boundary is most
By force, the 5th semiconductor layer 205 of the trapezoidal groove lower surface is connected at the 3rd hetero-junctions formed very with the 3rd semiconductor layer 203
Easily form two-dimensional electron gas (2DEG) raceway groove；In groove side, due to the 4th semiconductor layer 204, the 5th semiconductor herein
The direction of growth and [0001] of the 205, the 6th semiconductor layer 206 of layer orIt is not parallel, so the 4th semiconductor layer 204 and
The second hetero-junctions and the 5th semiconductor layer 205 that the connection of five semiconductor layers 205 is formed are connected what is formed with the 6th semiconductor layer 206
The polarized electric field of 4th hetero-junctions is weaker, and the self poling of the 4th hetero-junctions of the 5th semiconductor layer 205 and the 6th semiconductor 206
The self poling direction of an electric field of second hetero-junctions of the direction of electric field and the 4th semiconductor layer 204 and the 5th semiconductor layer 205 on the contrary,
Further weaken the self poling electric field of the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203 so that groove side
Two-dimensional electron gas (2DEG) at the first hetero-junctions section in face exhausts.
Embodiment 2
The high pressure Multiple heterostructures device in a kind of often Pass Ravine road of this example, as shown in figure 3, including setting gradually from the bottom up
First semiconductor substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 5th
Semiconductor layer 205, the 6th semiconductor layer 206, the 7th semiconductor layer 207；The both ends of 4th semiconductor layer 204 are set respectively
There are the first Ohmic contact 101 and the second Ohmic contact 103；There is metal electrode 102, gold on the 7th described semiconductor layer 207
Belong to electrode 102 between the first Ohmic contact 101 and the second Ohmic contact 103；3rd semiconductor layer 203 and the 4th half is led
The junction of body layer 204 forms the first hetero-junctions, the junction shape of the 4th semiconductor layer 204 and the 5th semiconductor layer 205
Into the second hetero-junctions, the junction of the 5th semiconductor layer 205 and the 3rd semiconductor layer 203 forms the 3rd hetero-junctions, and the 5th half leads
The junction of the semiconductor layer 206 of body layer 205 and the 6th forms the 4th hetero-junctions, the 6th semiconductor 206 and the 7th semiconductor layer 207
Junction form the 5th hetero-junctions, the 5th semiconductor layer 205 leads with the 4th hetero-junctions of the 6th semiconductor layer 206 and the 6th half
The self poling electric field and the 4th semiconductor layer 204 and the 5th semiconductor of 5th hetero-junctions of the semiconductor layer 207 of body layer 206 and the 7th
The self poling electric field of second hetero-junctions of layer 205 is opposite and in the on-plane surface Multiple heterostructures formed below of metal electrode 102.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Five semiconductor layers 205, the 6th semiconductor layer 206 and the 7th semiconductor layer 207 be mainly GaN, InN, AlGaN, InGaN,
InAlGaN or AlN；The first described Ohmic contact 101 and the electrode material of the second Ohmic contact 103 include gold, silver, aluminium,
One or more combinations in titanium, platinum and indium；The material of described metal electrode 102 include titanium, gold, nickel, platinum, nobelium, tungsten, silver,
One or more combinations in aluminium, titanium, molybdenum and indium.
The principle of embodiment 2, it is by the 3rd semiconductor layer 203, the 4th semiconductor layer below metal electrode 102
204th, the 5th semiconductor layer 205, the 6th semiconductor layer 206 and the 7th semiconductor layer 207 form nonplanar trapezoidal groove polyisocyanate
Matter junction structure；Semiconductor in the upper and lower surface and device of groove in addition to groove is along crystal orientation [0001] or crystal orientationDeposition growing, the 4th semiconductor layer 204, the 5th semiconductor layer the 205, the 6th of the groove side being made up of bending segment
Semiconductor layer 206, the 7th semiconductor layer 207 be along with crystal orientation [0001] or crystal orientationThere is certain angle deposition growing
's；Along [0001] orWhen the Group III-V semiconductor of direction growth forms hetero-junctions, the polarized electric field of heterojunction boundary
It is most strong, thus the 5th semiconductor layer 205 of the lower surface of the trapezoidal groove formation is connected with the 3rd semiconductor layer 203 it is the 3rd different
Matter knot is readily formed two-dimensional electron gas (2DEG) raceway groove；In groove side, due to the 4th semiconductor layer the 204, the 5th herein
The direction of growth of semiconductor layer 205, the 6th semiconductor layer 206 and the 7th semiconductor layer and [0001] orIt is not parallel, institute
The second hetero-junctions formed with the 4th semiconductor layer 204 and the junction of the 5th semiconductor layer 205, the 5th semiconductor layer 205 and the
The 4th hetero-junctions that the junction of six semiconductor layer 206 is formed, the 6th semiconductor layer 206 and the junction shape of the 7th semiconductor layer 207
Into the 5th hetero-junctions polarized electric field it is weaker, and the 4th hetero-junctions that the 5th semiconductor layer 205 and the 6th semiconductor 206 are formed
And the 6th direction and the 4th half of the self poling electric field of the 5th hetero-junctions for being formed of semiconductor layer 206 and the 7th semiconductor layer 207
The self poling direction of an electric field for the second hetero-junctions that the semiconductor layer 205 of conductor layer 204 and the 5th is formed is on the contrary, further second is heterogeneous
The self poling electric field of knot so that two-dimensional electron gas (2DEG) exhausts at the second heterojunction boundary of groove side.
Embodiment 3
The high pressure Multiple heterostructures device in a kind of often Pass Ravine road of this example, as shown in figure 4, including setting gradually from the bottom up
First semiconductor substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 5th
Semiconductor layer 205；The both ends of 3rd semiconductor layer 203 are respectively arranged with the first Ohmic contact 101 and the second Ohmic contact
103；There is metal electrode 102, metal electrode 102 is in the first Ohmic contact 101 and second on the 5th described semiconductor layer 205
Between Ohmic contact 103；The junction of 3rd semiconductor layer 203 and the 4th semiconductor layer 204 forms the first hetero-junctions, institute
The junction for stating the 4th semiconductor layer 204 and the 5th semiconductor layer 205 forms the second hetero-junctions, the 4th semiconductor layer 204 and the
The self poling electric field of the hetero-junctions of five semiconductor layers 205 and the hetero-junctions of the 3rd semiconductor layer 203 and the 4th semiconductor layer 204
Self poling electric field is opposite and in the on-plane surface Multiple heterostructures formed below of metal electrode 102.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Five semiconductor layers 205 are mainly GaN, InN, AlGaN, InGaN, InAlGaN or AlN；The described He of the first Ohmic contact 101
The electrode material of second Ohmic contact 103 includes one or more combinations in gold, silver, aluminium, titanium, platinum and indium；Described metal
The material of electrode 102 includes one or more combinations in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum and indium.
The principle of embodiment 3, it is by the 3rd semiconductor layer 203, the 4th semiconductor layer below metal electrode 102
204th, the 5th semiconductor layer 205 forms nonplanar trapezoidal raised double-heterostructure；Raised upper and lower surface and
Semiconductor in device in addition to projection is along crystal orientation [0001] or crystal orientationDeposition growing, the projection being made up of bending segment
The 4th semiconductor layer 204, the 5th semiconductor layer 205 of side be along with crystal orientation [0001] or crystal orientationThere is certain angle
Deposition growing；Along [0001] orWhen the Group III-V semiconductor of direction growth forms hetero-junctions, heterojunction boundary
Polarized electric field is most strong, so the 4th semiconductor layer 204 of the trapezoidal raised upper surface is connected formation with the 3rd semiconductor layer 203
The first hetero-junctions at be readily formed two-dimensional electron gas (2DEG) raceway groove；In raised side, due to the 3rd semiconductor herein
The 203, the 4th semiconductor layer 204 of layer, the 5th semiconductor layer 205 the direction of growth and [0001] orIt is not parallel, so side
The first hetero-junctions and the 5th semiconductor layer 205 that the 4th semiconductor layer 204 at face and the connection of the 3rd semiconductor layer 203 are formed with
The spontaneous polarization electric field for the second hetero-junctions that the connection of 4th semiconductor layer 204 is formed is weaker, and the 5th semiconductor layer 205 and the 4th
The of the direction of the self poling electric field of second hetero-junctions of semiconductor 204 and the 4th semiconductor layer 204 and the 3rd semiconductor layer 203
The self poling direction of an electric field of one hetero-junctions is on the contrary, further weaken the first of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203
The self poling electric field of hetero-junctions so that the two-dimensional electron gas (2DEG) at the first hetero-junctions of raised side exhausts.
Embodiment 4
A kind of high pressure heterojunction device in the often Pass Ravine road of this example, as shown in figure 5, including set gradually from the bottom up the
Semi-conductive substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 8th half
Conductor layer 208；The both ends of 3rd semiconductor layer 203 are respectively arranged with the first Ohmic contact 101 and the second Ohmic contact
103；The junction of 3rd semiconductor layer 203 and the 4th semiconductor layer 204 forms the first hetero-junctions, the 4th semiconductor
The bending segment of layer 204 raises up to form trapezoidal shape bending segment for the 4th semiconductor layer 204, the bottom of the trapezoidal shape bending segment
Width is more than upper bottom edge width；Be filled with the 8th semiconductor layer 208 in the trapezoidal shape bending segment, the 8th semiconductor layer with
The upper bottom edge junction of 4th semiconductor layer forms the second hetero-junctions；The metal electrode 102 is covered in trapezoidal shape bending segment
Side outer surface and upper bottom edge upper surface；The on-plane surface hetero-junctions formed below of metal electrode 102.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Eight semiconductor layers 208 are mainly GaN, InN, AlGaN, InGaN, InAlGaN or AlN；Further, described first ohm
The electrode material of the Ohmic contact 103 of contact 101 and second includes one or more combinations in gold, silver, aluminium, titanium, platinum and indium；Institute
The material for the metal electrode 102 stated includes one or more combinations in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum and indium.
A kind of principle of high pressure heterojunction device with Multiple heterostructures of embodiment 4, is by under metal electrode 102
Deposition growing has the 8th semiconductor layer 208 between the 3rd semiconductor layer 203 and the 4th semiconductor layer 204 of side, and the 3rd half leads
Body layer 203, the 4th semiconductor layer 204, the 8th semiconductor layer 208 form nonplanar trapezoidal raised heterojunction structure, raised
Semiconductor in upper and lower surface and device in addition to projection is along crystal orientation [0001] or crystal orientationDeposition growing
, the 4th semiconductor layer 204, the 8th semiconductor layer 208 of the raised side being made up of bending segment be along with crystal orientation [0001]
Or crystal orientationThere is certain angle deposition growing；8th semiconductor layer 208 and the 3rd half of the trapezoidal raised lower surface
Conductor layer 203 forms the 3rd hetero-junctions, because the thickness ratio of the 8th semiconductor layer 208 is thicker so that the 3rd herein is heterogeneous
Fail to form two-dimensional electron gas (2DEG) at junction interface；4th semiconductor layer 204 of trapezoidal upper convex surface and the 8th semiconductor
Second hetero-junctions of layer 208, be along [0001] orThe Group III-V semiconductor hetero-junctions of direction growth, hetero-junctions circle
The polarized electric field in face is most strong, so being readily formed two-dimensional electron gas (2DEG) ditch at the second heterojunction boundary of upper convex surface
Road；On the contrary, the second hetero-junctions in raised side, due to the life of the 3rd semiconductor layer 204, the 8th semiconductor layer 208 of side
Length direction and [0001] orIt is not parallel, so the polarized electric field of the Multiple heterostructures of raised side is weaker so that convex side
It is difficult to form 2DEG at second heterojunction boundary in face.
Embodiment 5
A kind of high pressure heterojunction device in the often Pass Ravine road of this example, as shown in fig. 6, including set gradually from the bottom up the
Semi-conductive substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 9th half
Conductor layer 209, the tenth based semiconductor 210；The both ends of 3rd semiconductor layer 203 are respectively arranged with the first Ohmic contact 101
With the second Ohmic contact 103；There is metal electrode 102, gold on the 9th described semiconductor layer 209 and the tenth semiconductor layer 210
Belong to electrode 102 between the first Ohmic contact 101 and the second Ohmic contact 103；3rd semiconductor layer 203 and the 4th half is led
The junction of body layer 204 forms the first hetero-junctions, the junction shape of the 9th semiconductor layer 209 and the 4th semiconductor layer 204
Into the second hetero-junctions, the junction of the tenth semiconductor layer 210 and the 4th semiconductor layer 204 forms the 3rd hetero-junctions；9th
The second hetero-junctions and the tenth semiconductor layer 210 of the semiconductor layer 204 of semiconductor layer 209 and the 4th and the 4th semiconductor layer 204
The self poling electric field of 3rd hetero-junctions and the self poling of the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203
Electric field is opposite and in the on-plane surface Multiple heterostructures formed below of metal electrode 102.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Nine semiconductor layers 209 and the tenth based semiconductor 210 are mainly GaN, InN, AlGaN, InGaN, InAlGaN or AlN；Described
The electrode material of first Ohmic contact 101 and the second Ohmic contact 103 includes gold, silver, aluminium, titanium, platinum or indium；Described gold
The material of category electrode 102 includes titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum or indium.
A kind of high pressure Multiple heterostructures device with normal Pass Ravine road of embodiment 5, is by below metal electrode 102
3rd semiconductor layer 203, the 4th semiconductor layer 204 form nonplanar trapezoidal raised heterojunction structure, and in upper convex surface
The 4th semiconductor layer 204 bending segment and the horizontal segment difference semiconductor layer 209 of deposition growing the 9th and the tenth semiconductor layer
210；Semiconductor in the upper and lower surface and device of groove in addition to groove is along crystal orientation [0001] or crystal orientationDeposition growing, the 3rd semiconductor layer 203, the 4th semiconductor layer 204 and of the raised side being made up of bending segment
Nine semiconductor layers 209 be along with crystal orientation [0001] or crystal orientationThere is certain angle deposition growing；In the trapezoidal projection
4th based semiconductor 204 on surface and the 3rd semiconductor layer 203 constitute the first heterojunction structure, along [0001] orWhen the Group III-V semiconductor of direction growth forms hetero-junctions, the polarized electric field of heterojunction boundary is most strong, so the 3rd is different
Two-dimensional electron gas (2DEG) raceway groove is readily formed at matter knot；In raised side, because the 3rd semiconductor layer the 203, the 4th half is led
Body layer 204, the 9th semiconductor layer 209 the direction of growth and [0001] orIt is not parallel, the 9th semiconductor layer 209 and the 4th
Second hetero-junctions of semiconductor layer 204 and the polarization electricity of the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203
Field is weaker, and the self poling direction of an electric field of the direction of the self poling electric field of the second hetero-junctions and the first hetero-junctions is on the contrary, further
Weaken the self poling electric field of the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203 so that the of raised side
The two-dimensional electron gas (2DEG) of the upper surface of three semiconductor layer 203 exhausts.
Embodiment 6
A kind of high pressure Multiple heterostructures device in the often Pass Ravine road of this example, as shown in fig. 7, comprises set gradually from the bottom up
First semiconductor substrate layer 201, the second semiconductor buffer layer 202, the 3rd semiconductor layer 203, the 4th semiconductor layer the 204, the 9th
Semiconductor layer 209, the tenth semiconductor layer 210；The both ends of 3rd semiconductor layer 203 are respectively arranged with the first Ohmic contact
101 and second Ohmic contact 103；There is metal electrode 102 on the 9th described semiconductor layer 209 and the tenth semiconductor layer 210,
Metal electrode 102 is between the first Ohmic contact 101 and the second Ohmic contact 103；3rd semiconductor layer 203 and the 4th half
The junction of conductor layer 204 forms the first hetero-junctions, the junction of the 9th semiconductor layer 209 and the 4th semiconductor layer 204
The second hetero-junctions is formed, the junction of the tenth semiconductor layer 210 and the 4th semiconductor layer 204 forms the 3rd hetero-junctions；The
The second hetero-junctions and the tenth semiconductor layer 210 and the 4th semiconductor layer 204 of nine semiconductor layers 209 and the 6th semiconductor layer 204
The 3rd hetero-junctions self poling electric field and the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203 from pole
Change electric field conversely and in the on-plane surface Multiple heterostructures formed below of metal electrode 102.
First semiconductor substrate layer 201 is one kind in sapphire, silicon and carborundum；The second described semiconductor delays
It is mainly one kind in SiC, AlN, GaN, AlGaN to rush layer 202；3rd semiconductor layer 203, the 4th semiconductor layer 204,
Nine semiconductor layers 209 and the tenth semiconductor layer 210 are mainly GaN, InN, AlGaN, InGaN, InAlGaN or AlN；Further
, the first described Ohmic contact 101 and the electrode material of the second Ohmic contact 103 are included in gold, silver, aluminium, titanium, platinum and indium
One or more combination；The material of described metal electrode 102 is included in titanium, gold, nickel, platinum, nobelium, tungsten, silver, aluminium, titanium, molybdenum and indium
One or more combinations.
The principle of embodiment five, it is by the 3rd semiconductor layer 203, the 4th semiconductor layer below metal electrode 102
204 form nonplanar trapezoidal groove heterojunction structure, and the bending segment and water of the 4th semiconductor layer 204 in groove upper surface
Flat the section difference semiconductor layer 209 of deposition growing the 9th and the tenth semiconductor layer 210；The upper and lower surface and device of groove
In semiconductor in addition to groove be along crystal orientation [0001] or crystal orientationDeposition growing, the groove side being made up of bending segment
3rd semiconductor layer 203, the 4th semiconductor layer 204 and the 9th semiconductor layer 209 in face be along with crystal orientation [0001] or crystal orientationThere is certain angle deposition growing；5th semiconductor layer 204 of the trapezoidal groove lower surface and the 3rd semiconductor layer 203
Constitute the first heterojunction structure, along [0001] orThe Group III-V semiconductor of direction growth forms hetero-junctions
When, the polarized electric field of heterojunction boundary is most strong, so being readily formed two-dimensional electron gas at the hetero-junctions of groove lower surface first
(2DEG) raceway groove；In groove side, due to the life of the 3rd semiconductor layer 203, the 4th semiconductor layer 204, the 9th semiconductor layer 209
Length direction and [0001] orIt is not parallel, the 9th semiconductor layer 209 of side and the second of the 4th semiconductor layer 204 heterogeneous
The polarized electric field of knot and the first hetero-junctions of the 4th semiconductor layer 204 and the 3rd semiconductor layer 203 is weaker, and the 9th semiconductor layer
209 and the 4th the direction of self poling electric field of the second hetero-junctions of semiconductor layer 204 led with the 4th semiconductor layer 204 and the 3rd half
The self poling direction of an electric field of first hetero-junctions of body layer 203 is on the contrary, further weaken the 4th semiconductor layer 204 and the 3rd semiconductor
The self poling electric field of first hetero-junctions of layer 203 so that the two-dimensional electron gas of the upper surface of the 3rd semiconductor layer 203 of groove side
(2DEG) exhausts.
In order to be better understood from the structure of the present invention, the present invention provides a kind of with normal Pass Ravine road hetero-junctions high tension apparatus
Making programme：
The first step：Organic chemistry deposition process is used on a silicon substrate, is sequentially depositing AlN cushions and GaN, AlxGa1- xN, x value are 0~1；AlxGa1-xN and GaN junctions form AlxGa1-xN/GaN hetero-junctions, such as Fig. 8, are then swashed with pulse
Light deposition about 500nm Si3N4Film is as mask, in AlxGa1-xNotch window is etched on N, as shown in Figure 9；
Second step：In AlxGa1-xUsing organic chemical vapor deposition method (MOCVD), atom on N and bottom portion of groove GaN
Layer Epitaxial deposition (ALD) or molecular beam epitaxial method (MBE) are in depositing AlyGa1-yN、AlzGa1-zN、AlwGa1-wN layers, wherein
Y, z, w value are 0~1；And AlyGa1-yN and GaN junctions form AlxGa1-xN/GaN hetero-junctions, AlyGa1-yN and
AlxGa1-xN junctions form AlyGa1-y/AlxGa1-xN hetero-junctions, AlzGa1-zN and AlyGa1-yN junctions form AlzGa1-zN/
AlyGa1-yN hetero-junctions, AlwGa1-wN and AlzGa1-zN junctions form AlwGa1-wN/AlzGa1-zN hetero-junctions such as Figure 10；
3rd step：With alcohol, acetone and deionized water respectively to AlwGa1-wN/AlzGa1-zN、AlzGa1-zN/AlyGa1-yN、
AlyGa1-y/AlxGa1-xN、AlxGa1-x/ GaN hetero-junctions is cleaned by ultrasonic, and is etched after nitrogen drying with ion etching process
Ohmic contact regions, etching gas BCl3, then deposited by electron beam evaporation growth Ohm contact electrode (Ti/Al/Au) and at 850 DEG C
Short annealing about 30s, such as Figure 11 under N2 atmosphere；
5th step：Growth metal electrode 102 is evaporated in groove with electron beam again, such as Figure 12.
Claims (1)
1. a kind of high pressure Multiple heterostructures device with normal Pass Ravine road, including the first Semiconductor substrate set gradually from the bottom up
Layer (201), the second semiconductor buffer layer (202), the 3rd semiconductor layer (203) and the 4th semiconductor layer (204)；Described 3rd half
The both ends upper surface of conductor layer (203) is respectively arranged with the first Ohmic contact (101) and the second Ohmic contact (103)；Described
The both ends of four semiconductor layers (204) are connected with the first Ohmic contact (101) and the second Ohmic contact (103) respectively, and the described 4th
There is metal electrode (102) on semiconductor layer (204)；3rd semiconductor layer (203) is connecing with the 4th semiconductor layer (204)
Touch interface and form the first hetero-junctions；Characterized in that, having below the metal electrode (102) makes two-dimensional electron gas immediately below it
The on-plane surface hetero-junctions that raceway groove interrupts；4th semiconductor layer (204) is made up of bending side and horizontal plane；Described 4th half leads
On-plane surface hetero-junctions is formed at the bending side of body layer (204)；The bending side of 4th semiconductor layer (204) is located at metal electrode
(102) immediately below,
The bending side of 4th semiconductor layer (204) is is folded upward at, at the bending side of the 4th semiconductor layer (204)
Shape of cross section between lower surface and the 3rd semiconductor layer (203) upper surface is trapezoidal, and the trapezoidal bottom width is more than
Upper bottom edge width；3rd semiconductor layer (203) be filled in it is trapezoidal in；The metal electrode (102) is by the first vertical plane,
Two vertical planes and plane are formed；The plane of the metal electrode (102) is mutually flat with the horizontal plane of the 4th semiconductor layer (204)
OK；The plane of the metal electrode (102) is hung down with the second of the first vertical plane of metal electrode (102) and metal electrode (102)
Face connection directly and form inverted U-shaped；The plane of the metal electrode (102) and the first vertical plane and gold of metal electrode (102)
Second vertical plane of category electrode (102) is mutually perpendicular to；Led with the 4th half first vertical plane lower surface of the metal electrode (102)
The horizontal plane upper surface connection of the bending side side of body layer (204), its upper surface and plane one end following table of metal electrode (102)
Face connects；Second vertical plane lower surface of the metal electrode (102) and the bending side opposite side water of the 4th semiconductor layer (204)
The upper surface connection of plane, its upper surface is connected with the plane other end lower surface of metal electrode (102)；The metal electrode
(102) there is the tenth semiconductor layer (210) between plane and the upper bottom surface surface of the 4th semiconductor layer (204) bending side；Institute
State the tenth semiconductor layer (210), the vertical plane of metal electrode (102), the plane of metal electrode (102) and the 4th semiconductor layer
(204) there is the 9th semiconductor layer (209), the 9th semiconductor layer (209) and the 4th semiconductor layer between bending side
(204) junction forms the second hetero-junctions, the tenth semiconductor layer (210) and the junction of the 4th semiconductor layer (204)
The 3rd hetero-junctions is formed, wherein the self poling electric field of the self poling electric field and the first hetero-junctions of the second hetero-junctions and the 3rd hetero-junctions
On the contrary, weaken the self poling electric field of the first hetero-junctions of the 4th semiconductor layer and the 3rd semiconductor layer so that the of raised side
The two-dimensional electron gas of three semiconductor layer upper surfaces exhausts.
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| CN102856366A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhancement type device |
| CN102856355A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhanced semiconductor device |
| CN103620751A (en) * | 2011-07-12 | 2014-03-05 | 松下电器产业株式会社 | Nitride semiconductor device and method for manufacturing same |
| CN103715244A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103620751A (en) * | 2011-07-12 | 2014-03-05 | 松下电器产业株式会社 | Nitride semiconductor device and method for manufacturing same |
| CN102683406A (en) * | 2012-04-29 | 2012-09-19 | 西安电子科技大学 | GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof |
| CN102856366A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhancement type device |
| CN102856355A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhanced semiconductor device |
| CN103715244A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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