JP2007088185A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which normally off type is achieved while suppressing increase in on resistance, and to provide its fabrication process. <P>SOLUTION: The semiconductor device comprises a first layer of a first nitride semiconductor having a step on the upper surface, a second layer of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor formed on the first layer while covering the step where the thickness of the step above the side face is smaller than the thickness above the major surfaces on the upper and lower sides of the side face, a gate electrode provided on the second layer above the side face of the step, a source electrode provided on the second layer above any one of the major surfaces on the upper and lower sides of the side face, and a drain electrode provided on the second layer above the other of the major surfaces on the upper and lower sides of the side face. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a nitride semiconductor and a method for manufacturing the same.

  In recent years, gallium nitride (GaN), which has been developed as a material for light-emitting devices, is being considered for application to high-power electronic devices due to its high breakdown voltage characteristics, high thermal conductivity, and high electron mobility characteristics. . In the heterojunction structure of aluminum gallium nitride (AlGaN) doped with impurities (donor) and non-doped gallium nitride (GaN), lattice distortion due to lattice mismatch occurs in AlGaN on GaN, thereby A piezoelectric polarization effect is generated, and as a result, a two-dimensional electron gas is generated on the GaN side at the heterojunction interface of AlGaN / GaN. When there are few impurities in GaN, in a two-dimensional electron gas, since the impurity scattering at the time of an electron movement reduces, it becomes a high mobility. A GaN-based HEMT (High Electron Mobility Transistor) that takes advantage of this feature is expected to play an active role in a wide range of fields such as high frequency applications and power electronics applications due to its high mobility characteristics.

  In order to use the GaN-based HEMT as a power device, a normally-off type is preferable in order to reduce power consumption. As a method for realizing a normally-off type in an AlGaN / GaN HEMT, a recess is formed in the AlGaN layer, which is a Schottky layer, by etching, and the thickness of the AlGaN film just below the gate electrode is reduced, thereby reducing the piezoelectric polarization effect. A method of depleting channel carriers by using pinning by a gate electrode or an interface state can be considered. When the Al composition in the AlGaN layer is about 0.25, the thickness of the AlGaN layer for normally-off is required to be 5 nm or less. However, with the current etching technology, it is difficult to control the thickness of AlGaN after etching to several nanometers with high accuracy and reproducibility.

  Another possible method is to control the thickness of the AlGaN layer to several nanometers at the crystal growth stage without using etching. Although the thickness can be controlled by using a crystal growth technique such as MOCVD (Metal Organic Chemical Vapor Deposition), in this case, the channel is depleted from the source to the drain. End up. When used as a switching device such as a power supply device, this method is not practical because on-resistance is the most important characteristic.

  Further, in Patent Document 1, a facet having a plane orientation of (1-101) is formed by selective growth on the (0001) plane, and the plane orientation of the interface between the electron transit layer and the barrier layer is (1-101). And a gate, a source, and a drain are formed on the facet. By setting the plane orientation of the interface between the electron transit layer and the barrier layer to (1-101), the polarization charge generated at the interface is reduced as compared with the case where the plane orientation of the interface is (0001). Since the concentration of the electron gas is reduced, Patent Document 1 aims to realize a normally-off type.

However, in the configuration of Patent Document 1, since the source-gate and the gate-drain also exist on the (1-101) plane having a low two-dimensional electron gas concentration, the on-resistance becomes high. In addition, it is not practical to grow a facet of (1-101) having an area enough to produce a practical device on the (0001) plane, which requires a large growth cost.
JP 2003-347315 A

  The present invention provides a semiconductor device that realizes a normally-off type while suppressing an increase in on-resistance, and a method for manufacturing the same.

According to one aspect of the invention,
A first layer made of a first nitride semiconductor and having a step on the upper surface;
The second nitride semiconductor has a band gap larger than that of the first nitride semiconductor, is stacked on the first layer so as to cover the step portion, and has a thickness on a side surface of the step portion. A second layer smaller than the thickness on the upper and lower main surfaces of the side surface;
A gate electrode provided on the second layer on the side surface of the step;
A source electrode provided on the second layer on one of the upper and lower main surfaces of the side surface;
A drain electrode provided on the second layer on the other of the upper and lower main surfaces of the side surface;
A semiconductor device is provided.

According to another aspect of the present invention,
A first layer made of a first nitride semiconductor and provided on the main surface with a facet inclined with respect to the main surface;
The first nitride semiconductor is made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor, and is stacked on the main surface and the facet of the first layer, and the thickness on the facet has a thickness on the main surface. A second layer smaller than the thickness above,
A gate electrode provided with the second layer sandwiched between the facets of the first layer;
A source electrode provided on a main surface lateral to the facet on the second layer;
A drain electrode provided on a main surface opposite to the source electrode on the second layer across the facet;
A semiconductor device is provided.

According to yet another aspect of the present invention,
Epitaxially growing a first layer comprising a first nitride semiconductor and having a face orientation with a plane orientation having a crystal growth rate smaller than that of the main surface on the underlying crystal;
Epitaxially growing a second layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor on the main surface and the facet of the first layer;
Forming a gate electrode on the second layer over the facet of the first layer;
Forming a source electrode on a main surface on the side of the facet on the second layer;
Forming a drain electrode on a main surface on the opposite side of the source electrode across the facet on the second layer;
A method of manufacturing a semiconductor device is provided.

  According to the present invention, a normally-off type can be realized while suppressing an increase in on-resistance, so that power consumption can be reduced.

  Hereinafter, specific embodiments to which the present invention is applied will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view of a main part of a semiconductor device 1 according to the first embodiment of the present invention.
FIG. 2 is a perspective view of a main part of the semiconductor device 1.

  The semiconductor device 1 according to the present embodiment mainly includes a first nitride semiconductor layer 8, a second nitride semiconductor layer 9 stacked on the first nitride semiconductor layer 8, and a second nitride. And gate, source, and drain electrodes 12 to 14 formed on the physical semiconductor layer 9.

  The second nitride semiconductor layer 9 has a larger band gap than the first nitride semiconductor layer 8. In this specific example, the first nitride semiconductor layer 8 is a non-doped GaN layer. The first nitride semiconductor layer 8 is formed by epitaxial growth on the non-doped GaN layers 4 and 6 which are base crystals (or buffer layers). For example, the GaN layer 4 is stacked on the sapphire substrate 2 via the AlN layer 3. A step portion 11 is provided on the upper surface of the first nitride semiconductor layer 8, and a side surface (hereinafter also simply referred to as “facet”) 8 a of the step portion 11 is inclined with respect to the main surface. For example, the surface orientation of the main surface is (0001), and the surface orientation of the facet 8a is (1-101).

  The second nitride semiconductor layer 9 is an n-type AlGaN layer obtained by adding an impurity (donor) to the AlGaN layer epitaxially grown on the first nitride semiconductor layer 8. The facet 8a (face orientation is (1--) than the crystal growth rate on the main faces 8c, 8b (face orientation is (0001)) on the upper and lower faces of the facet 8a in the first nitride semiconductor layer 8. 101)) The upward crystal growth rate is smaller. Therefore, the second nitride semiconductor layer 9 naturally has a thickness difference in the course of crystal growth, and the thickness on the facet 8a is smaller than the thickness on the main surfaces 8b and 8c.

  The gate electrode 12 is provided on the second nitride semiconductor layer 9 on the facet 8 a of the first nitride semiconductor layer 8. That is, the gate electrode 12 is provided between the facet 8 a of the first nitride semiconductor layer 8 and the second nitride semiconductor layer 9 interposed therebetween. It is desirable that the gate electrode 12 is provided not only on the facet 8a but also slightly protrudes from the upper main surface and the lower main surface of the facet 8a. The gate electrode 12 is in Schottky contact with the second nitride semiconductor layer 9.

  The source electrode 13 is provided on the lower side of the facet 8 a on the second nitride semiconductor layer 9. The drain electrode 14 is provided on the upper side of the facet 8 a on the second nitride semiconductor layer 9. That is, the source electrode 13 and the drain electrode 14 are formed on the main surface of the second nitride semiconductor layer 9 with the facet 8a interposed therebetween. The source electrode 13 and the drain electrode 14 are in ohmic contact with the second nitride semiconductor layer 9.

  The semiconductor device 1 according to the present embodiment is a HEMT (High Electron Mobility Transistor) using a two-dimensional electron gas generated at a heterojunction interface between a first nitride semiconductor layer 8 and a second nitride semiconductor layer 9. is there. The second nitride semiconductor layer 9 made of an n-type AlGaN layer functions as an electron supply layer (or barrier layer), and the first nitride semiconductor layer 8 made of a non-doped GaN layer without addition of impurities is used for electron travel. Acts as a layer. The second nitride semiconductor layer 9 is depleted, and a two-dimensional electron gas is accumulated in a very thin region of the first nitride semiconductor layer 8 near the interface with the second nitride semiconductor layer 9. When the gate voltage applied to the gate electrode 12 is changed, the concentration of the two-dimensional electron gas increases or decreases, and as a result, the drain current flowing between the source electrode 13 and the drain electrode 14 changes.

  If the thickness of the second nitride semiconductor layer 9 under the gate electrode 12 is sufficiently reduced, the depletion layer is not limited to the second nitride semiconductor layer 9 even if the gate voltage is zero volts (0 V). The first nitride semiconductor layer 8 is also spread and formed. Since the two-dimensional electron gas storage layer is extremely thin, if the depletion layer is formed to extend even a little over the first nitride semiconductor layer 8, a normally-off type semiconductor device in which the gate voltage is 0 V and the drain current does not flow is obtained.

  In the present embodiment, the Al composition in the second nitride semiconductor layer (AlGaN layer) 9 is about 0.25, and in this case, the thickness under the gate electrode 12 for normally-off is 5 nm or less. Required. In the present embodiment, since the thickness of the second nitride semiconductor layer 9 can be determined by controlling the epitaxial growth without using etching, a very thin film thickness of 5 nm or less can be accurately and reproducibly. Can be formed well. As a result, a normally-off type semiconductor device in which variation in characteristics such as pinch-off voltage is suppressed can be stably obtained.

  Further, in the second nitride semiconductor layer 9, the thickness of the portion between the gate electrode 12 and the source electrode 13 and the thickness of the portion between the gate electrode 12 and the drain electrode 14 are about 50 nm. It is sufficiently thicker than the thickness of the lower part of 12 (5 nm or less). For this reason, a large piezoelectric polarization effect is obtained, and the on-resistance can be reduced by forming a two-dimensional electron gas accumulation layer having a sufficiently high concentration.

  As described above, according to the present embodiment, it is possible to achieve both the suppression of an increase in on-resistance and the normally-off type, and the power consumption of the semiconductor device 1 can be reduced.

  In the present embodiment, the plane orientation of the interface (facet) 8a between the first nitride semiconductor layer 8 and the second nitride semiconductor layer 9 under the gate electrode 12 is (1-101), and the gate The plane orientation of the interface (facet) 8a between the first nitride semiconductor layer 8 and the second nitride semiconductor layer 9 between the electrode 12 and the source electrode 13 and between the gate electrode 12 and the drain electrode 14 is ( 0001). In a semiconductor device having a HEMT structure, the concentration of a two-dimensional electron gas generated at an interface having a plane orientation of (1-101) is higher than that of an interface having a plane orientation of (0001). Therefore, the fact that the semiconductor device 1 of this embodiment has the above-described interface orientation of the interface also contributes to realizing a normally-off type while suppressing an increase in on-resistance.

Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described.
3 to 7 are process cross-sectional views illustrating the main part of the manufacturing process of the semiconductor device 1 according to this embodiment.

  First, as shown in FIG. 3, the AlN layer 3 is laminated on the substrate 2 by 10 nm, for example, and the GaN layer 4 is laminated on the AlN layer 3 by 1 μm, for example. The substrate 2 is a sapphire substrate having a main surface with a plane orientation of (0001). The AlN layer 3 is epitaxially grown on the main surface of the sapphire substrate 2 by MOCVD (Metal Organic Chemical Vapor Deposition). The GaN layer 4 is epitaxially grown on the AlN layer 3 by the MOCVD method. Since the lattice constants of the substrate 2 and the GaN layer 4 are greatly different, the AlN layer 3 is interposed as an intermediate layer (buffer layer) between them. The substrate 2 is not limited to a sapphire substrate, and for example, a SiC substrate may be used.

Subsequently, after a silicon dioxide (SiO ₂ ) film having a thickness of 50 nm, for example, is laminated on the GaN layer 4 by a CVD (Chemical Vapor Deposition) method, the width (the lateral dimension in FIG. 3) is obtained by lithography and etching. ) Is 20 μm and the length (in the direction penetrating the paper surface in FIG. 3) is 2 mm. At this time, the mask 5 is formed so that the long side direction (the direction penetrating the paper surface in FIG. 3) faces the <11-20> direction on the GaN layer 4.

  Subsequently, after performing an appropriate pretreatment, a GaN layer 6 having a thickness of, for example, 500 nm is epitaxially grown on the GaN layer 4 by MOCVD. At this time, the epitaxial growth in the portion covered with the mask 5 on the surface (plane orientation (0001)) of the GaN layer 4 serving as the base for crystal growth is blocked, and the GaN layer 6 is formed in the portion not covered with the mask 5. Epitaxial growth. The GaN layer 6 grows not only in the direction perpendicular to the (0001) plane but also in the lateral direction, and is projected so as to protrude about 25 nm on the edge of the long side direction of the mask 5 as shown in FIG. Further, since the long side direction of the mask 5 is oriented in the <11-20> direction, a facet 6 a having a plane orientation of (1-101) is formed on the side of the long side of the mask 5. In the facet 6a, the length along the inclination direction is about 500 nm.

  Subsequently, the mask 5 is removed by wet etching, for example. Thereby, as shown in FIG. 5, a part 4 b of the surface (plane orientation is (0001)) of the GaN layer 4 is exposed. The GaN layer 6 is formed with a valley 7 having the exposed surface 4b of the GaN layer 4 as a bottom surface and a facet (plane orientation (1-101)) 6a as a side surface.

  Subsequently, after performing an appropriate pretreatment, as shown in FIG. 6, the GaN layer 8 is epitaxially grown by the MOCVD method. The valley portion 7 is filled by the epitaxial growth of the GaN layer 8, and the facet 8 a having substantially the same plane orientation (1-101) as the facet 6 a formed in the underlying GaN layer 6 is formed in the GaN layer 8. . In the GaN layer 8, the thickness on the main surface 4b of the GaN layer 4 and the main surface 6b of the GaN layer 6 is about 500 nm. In the present embodiment, the GaN layer 8 constitutes a first nitride semiconductor layer.

  Subsequently, as shown in FIG. 7, an AlGaN layer 9 is epitaxially grown as a second nitride semiconductor layer on the GaN layer (first nitride semiconductor layer) 8. Here, in the nitride semiconductor, the (1-101) plane has a smaller surface energy than the (0001) plane, nucleation is suppressed, and the crystal growth rate is low. The ratio of the crystal growth rate on the (1-101) plane to the crystal growth rate on the (0001) plane is about 0.05. Therefore, the thickness of the AlGaN layer 9 on the facet 8 a of the GaN layer 8 is smaller than the thickness on the main surfaces 8 b and 8 c of the GaN layer 8. In the present embodiment, the thickness of the AlGaN layer 9 is about 50 nm on the main surfaces 8b and 8c of the GaN layer 8, and is 2 to 2.5 nm on the facet 8a.

  Subsequently, as shown in FIGS. 1 and 2, source, drain, and gate electrodes 13, 14, and 12 are formed. In the second nitride semiconductor layer 9, the source electrode 13 is formed on the main surface located on the lower side of the facet 8 a, and the drain electrode 14 is formed on the main surface located on the upper side of the facet 8 a by vacuum evaporation and lift-off methods. It is formed. The source electrode 13 has a stripe shape whose long side direction is along the long side direction <11-20> of the facet 8a, and the drain electrode 14 is also a stripe whose long side direction is along the <11-20> direction. Present. Each of the source electrode 13 and the drain electrode 14 is configured by, for example, forming Ti and Al sequentially from the second nitride semiconductor layer 9 side, and is in ohmic contact with the second nitride semiconductor layer 9. The length of the source electrode 13 along the long side direction <11-20> is smaller than the long side direction length of the facet 8a.

  The gate electrode 12 is formed on the step portion 11 in the second nitride semiconductor layer 9 by vacuum deposition and a lift-off method. The gate electrode 12 is formed not only on the facet 8a but also slightly protruding from the upper main surface and the lower main surface of the facet 8a. The long side direction of the gate electrode 12 is along the long side direction <11-20> of the facet 8a, and the length along the long side direction <11-20> is the long side direction of the facet 8a. Less than length. The gate electrode 12 is configured by, for example, forming Ni and Au sequentially from the second nitride semiconductor layer 9 side, and is in Schottky contact with the second nitride semiconductor layer 9.

  After the formation of the source, drain, and gate electrodes 13, 14, and 12, although not shown, a passivation film made of silicon nitride is formed on the entire surface by CVD to cover the electrodes 13, 14, and 12, and After a protective film made of polyimide or the like is formed thereon, a pad opening for exposing a part of each electrode 13, 14, 12 or a wiring layer is formed.

  As described above, according to the present embodiment, the second difference under the gate electrode 12 is obtained by using the difference in crystal growth rate due to the difference in the plane orientation without using the etching technique with poor film thickness controllability. The thickness of the nitride semiconductor layer 9 is made thin so as to realize normally-off, and the thickness of the second nitride semiconductor layer 9 between the gate electrode 12 and the source electrode 13 and between the gate electrode 12 and the drain electrode 14. Is thick enough to reduce on-resistance. Thereby, the film thickness of the second nitride semiconductor layer 9 can be controlled with high accuracy and reproducibility, and the semiconductor device 1 having desired characteristics can be manufactured while suppressing manufacturing variations.

As a comparative example, after a second nitride semiconductor layer (AlGaN layer) 9 having a thickness of several nanometers is grown with good controllability by the MOCVD method or the like, an SiO ₂ film or the like is formed in the formation portion of the gate electrode 12 Then, there is a method in which the second nitride semiconductor layer 9 can be thinned only under the gate electrode 12 by re-growing the second nitride semiconductor layer 9 using the SiO ₂ film as a mask. However, impurities such as silicon, carbon and oxygen are deposited at a high concentration on the regrowth interface, which may lead to carrier trapping and gate leak loss, which may result in deterioration of the performance of the semiconductor device. There is.

  On the other hand, in this embodiment, the regrowth interface is present in a portion that does not substantially contribute to the operation (the surface of the GaN layers 4 and 6 that are buffer layers), and the second nitride as in the comparative example described above. Since it does not exist in the semiconductor layer (AlGaN layer) 9, it is possible to prevent a decrease in performance due to impurities at the regrowth interface.

  If the GaN layers 4 and 6 can be formed on the substrate 2 with few crystal defects, the second nitride semiconductor is formed on the exposed surface of the GaN layer 4 and the GaN layer 6 without forming the GaN layer 8. The layer (AlGaN layer) 9 may be epitaxially grown. That is, in this case, the GaN layers 4 and 6 function as the first nitride semiconductor layer.

  In order to perform various evaluations of the semiconductor device 1 according to this embodiment described above, for example, a gate electrode 12 having a longitudinal length a of 1.5 mm and a lateral length b of 1 μm was prepared. In the gate electrode 12, the length c in the short direction of the portion on the facet 8a is 500 nm. It can be said that the gate length is 500 nm because the portion that substantially functions as the gate is on the facet 8a. The lengths in the short direction of the source and drain electrodes 13 and 14 were 5 μm, the length between the source electrode 13 and the gate electrode 12 was 1 μm, and the length between the gate electrode 12 and the drain electrode 14 was 10 μm.

When various evaluations of the semiconductor device having such a size were performed, the maximum transconductance was 420 [mS / mm] and the maximum drain current was 400 [mA / mm]. The on-resistance per unit area was 2.1 [mmΩcm ² ]. The pinch-off voltage Vp was 1.34 [V], confirming the normally-off type. In addition, when the pinch-off voltage Vp of a plurality of semiconductor devices of the same specification built on a substrate having a diameter of 3 inches was evaluated, the standard deviation was 0.12 V with respect to the average value of 1.34 [V]. As a normally-off type, extremely good in-plane uniformity was obtained.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
FIG. 8 is a cross-sectional view of main parts of a semiconductor device 21 according to the second embodiment of the present invention.
FIG. 9 is a perspective view of a main part of the semiconductor device 21.

  The semiconductor device 21 according to the second embodiment mainly includes a first nitride semiconductor layer 27, a second nitride semiconductor layer 28 stacked on the first nitride semiconductor layer 27, and a second And the gate, source, and drain electrodes 32 to 34 formed on the nitride semiconductor layer 28.

  The first nitride semiconductor layer 27 is a non-doped GaN layer. The first nitride semiconductor layer 27 is formed by epitaxial growth on the non-doped GaN layer 24 which is a base crystal (or buffer layer) and the non-doped GaN layer 26 shown in FIG. The GaN layer 24 is stacked on the SiC substrate 22 via the AlM layer 23, for example. On the main surface 27c of the first nitride semiconductor layer 27, a step portion 31 having a triangular cross section is provided. It is inclined with respect to. For example, the surface orientation of the main surface 27c is (0001), the surface orientation of the facet 27a is (1-101), and the surface orientation of the facet 27b is equivalent to the facet 27a.

  The second nitride semiconductor layer 28 is an n-type AlGaN layer obtained by adding an impurity (donor) to the AlGaN layer epitaxially grown on the first nitride semiconductor layer 27. As described above with respect to the first embodiment, the crystal growth rate on the facets 27a and 27b is lower than the crystal growth rate on the main surface 27c of the first nitride semiconductor layer 27. Therefore, the second nitride semiconductor layer 28 naturally has a thickness difference in the course of crystal growth, and the thickness on the facets 27a and 27b is made smaller than the thickness on the main surface 27c.

  The gate electrode 32 is provided on the second nitride semiconductor layer 28 on the facets 27 a and 27 b of the first nitride semiconductor layer 27. That is, the gate electrode 32 is provided between the facets 27 a and 27 b of the first nitride semiconductor layer 27 with the second nitride semiconductor layer 28 interposed therebetween. Further, it is desirable that the gate electrode 32 is provided not only on the facets 27a and 27b but also slightly on the principal surface 27c at the base of the facets 27a and 27b. The gate electrode 32 is in Schottky contact with the second nitride semiconductor layer 28.

  The source electrode 33 is provided on the side of the facet 27 a on the second nitride semiconductor layer 28. The drain electrode 34 is provided on the side of the facet 27 b on the second nitride semiconductor layer 28. The source electrode 33 and the drain electrode 34 are formed on the main surface of the second nitride semiconductor layer 28 with the facets 27a and 27b interposed therebetween. The source electrode 33 and the drain electrode 34 are in ohmic contact with the second nitride semiconductor layer 28.

  Similarly to the first embodiment, the semiconductor device 21 according to the second embodiment also generates a two-dimensional electron gas generated at the heterojunction interface between the first nitride semiconductor layer 27 and the second nitride semiconductor layer 28. This is the HEMT used. The second nitride semiconductor layer 28 made of an n-type AlGaN layer functions as an electron supply layer (or barrier layer), and the first nitride semiconductor layer 27 made of a non-doped GaN layer without addition of impurities is an electron transit layer. Function as.

  Also in the second embodiment, since the thickness of the second nitride semiconductor layer 28 can be determined by controlling the epitaxial growth without using etching, a very thin film thickness of 5 nm or less under the gate is also possible. It can be formed with high accuracy and good reproducibility. As a result, a normally-off type semiconductor device in which variation in characteristics such as pinch-off voltage is suppressed can be stably obtained.

  Further, in the second nitride semiconductor layer 28, the thickness of the portion between the gate electrode 32 and the source electrode 33 and the thickness of the portion between the gate electrode 32 and the drain electrode 34 are about 50 nm. It is sufficiently thicker than the thickness of the lower part of 32 (5 nm or less). For this reason, a large piezoelectric polarization effect can be obtained, and the on-resistance can be reduced by forming a two-dimensional electron gas accumulation layer having a sufficiently high concentration.

  As described above, also in the second embodiment, it is possible to achieve both the suppression of an increase in on-resistance and the normally-off type, and the power consumption of the semiconductor device 21 can be reduced.

Next, an example of a method for manufacturing the semiconductor device 21 according to the second embodiment will be described.
9 to 13 are process cross-sectional views illustrating the main part of the manufacturing process of the semiconductor device 21 of this embodiment.

  First, as illustrated in FIG. 10, an AlN layer 23 is stacked on the substrate 22 by, for example, 10 nm, and a GaN layer 24 is stacked on the AlN layer 23 by, for example, 1 μm. The substrate 22 is a SiC substrate having a main surface with a plane orientation of (0001). The AlN layer 23 is epitaxially grown on the main surface of the substrate 22 by MOCVD. The GaN layer 24 is epitaxially grown on the AlN layer 23 by the MOCVD method. A sapphire substrate may be used as the substrate 22.

Subsequently, after a silicon dioxide (SiO ₂ ) film having a thickness of 100 nm, for example, is stacked on the GaN layer 24 by a CVD method, the width (lateral dimension in FIG. 10) is, for example, 1 μm by lithography and wet etching. A mask 25 having a stripe-shaped opening 25a having a length of 2 mm is formed. At this time, the opening 25 a is formed so that the long side direction (the direction penetrating the paper surface in FIG. 10) is directed to the <11-20> direction on the GaN layer 24.

  Subsequently, after performing an appropriate pretreatment, the GaN layer 26 is epitaxially grown by MOCVD. At this time, epitaxial growth at the portion covered with the mask 25 on the surface of the GaN layer 24 (plane orientation (0001)) is blocked, and the GaN layer 26 is selectively epitaxially grown only on the surface exposed from the opening 25a. Go. The GaN layer 26 grows not only in the direction perpendicular to the (0001) plane but also in the lateral direction. As a result, as shown in FIG. 11, the cross-sectional shape of the GaN layer 26 is such that the two corners at the bottom are perpendicular to the surface of the GaN layer 24 along the surface facing the opening 25a of the mask 25. Presents a substantially equilateral triangle shape. The length of one side of the substantially equilateral triangle is about 1 μm. Further, since the long side direction of the opening 25a faces the <11-20> direction, the GaN layer 26 has a side surface (facet) 26a having a plane orientation of (1-101) and a side surface equivalent thereto (facet) 26a. Facet) 26b is formed.

  Subsequently, after removing the mask 25 by, for example, wet etching, an appropriate pretreatment is performed, and the GaN layer 27 is epitaxially grown by MOCVD as shown in FIG. At this time, the missing portion of the bottom of the GaN layer 26 is filled to form two corners. Furthermore, facets 27a and 27b similar to the facets 26a and 26b of the GaN layer 26, which is the base crystal, are also formed on the GaN layer 27. That is, the face orientation of the facet 27a of the GaN layer 27 is (1-101), and the face orientation of the facet 27b is equivalent to (1-101). The plane orientation of the main surface 27c is (0001). In the GaN layer 27, the thickness on the main surface of the GaN layer 24 is about 500 nm. In the second embodiment, the GaN layer 27 is the first nitride semiconductor layer.

  Subsequently, as illustrated in FIG. 13, an AlGaN layer 28 is epitaxially grown on the GaN layer (first nitride semiconductor layer) 27 as a second nitride semiconductor layer. Here, the ratio of the crystal growth rate on the (1-101) plane to the crystal growth rate on the (0001) plane is about 0.05. Therefore, the thickness of the AlGaN layer 28 on the facets 27 a and 27 b of the GaN layer 27 is smaller than the thickness on the main surface 27 c of the GaN layer 27. In the present embodiment, the thickness of the AlGaN layer 28 is about 50 nm on the main surface 27c of the GaN layer 27 and 2 to 2.5 nm on the facets 27a and 27b.

  Subsequently, as shown in FIGS. 8 and 9, source, drain, and gate electrodes 33, 34, and 32 are formed. In the second nitride semiconductor layer 28, the source electrode 33 and the drain electrode 34 are vacuum deposited and lifted off with the step portion 31 sandwiched between the portions of the first nitride semiconductor layer 27 located on the major surface 27 c. Formed by law. The long side direction of the source electrode 33 has a stripe shape along the long side direction <11-20> of the facets 27a and 27b, and the long side direction of the drain electrode 34 also extends along the <11-20> direction. Exhibits a striped shape. The source electrode 33 and the drain electrode 34 are each configured by, for example, forming Ti and Al sequentially from the second nitride semiconductor layer 28 side, and are in ohmic contact with the second nitride semiconductor layer 28.

  The gate electrode 32 is formed in a portion of the second nitride semiconductor layer 28 located on the facets 27a and 27b by vacuum deposition and a lift-off method. The gate electrode 32 is formed not only on the facets 27a and 27b but also on the main surface near the roots of the facets 27a and 27b. The long side direction of the gate electrode 32 is along the long side direction <11-20> of the facets 27a and 27b. The gate electrode 32 is configured by, for example, forming Ni and Au sequentially from the second nitride semiconductor layer 28 side, and is in Schottky contact with the second nitride semiconductor layer 28.

  After the formation of the source, drain, and gate electrodes 33, 34, and 32, although not shown, a passivation film made of silicon nitride is formed on the entire surface by CVD to cover the electrodes 33, 34, and 32. After a protective film made of polyimide or the like is formed thereon, a pad opening for exposing a part of each electrode 33, 34, 32 or a wiring layer is formed.

  As described above, also in the second embodiment, the second growth under the gate electrode 32 is obtained by using the difference in crystal growth rate due to the difference in the plane orientation without using the etching technique with poor film thickness controllability. The thickness of the nitride semiconductor layer 28 is made thin so as to realize normally-off, and the thickness of the second nitride semiconductor layer 28 between the gate electrode 32 and the source electrode 33 and between the gate electrode 32 and the drain electrode 34. The thickness is sufficiently thick to reduce the on-resistance. Thereby, the film thickness of the second nitride semiconductor layer 28 can be controlled with high accuracy and reproducibility, and the semiconductor device 21 having desired characteristics can be manufactured while suppressing manufacturing variations.

  Furthermore, since the regrowth interface exists in a portion that does not substantially contribute to the operation (the surfaces of the GaN layers 24 and 26 that are buffer layers) and does not exist in the second nitride semiconductor layer 28, It is possible to prevent a decrease in performance due to impurities.

  Further, if the GaN layers 24 and 26 can be epitaxially grown with few crystal defects, the second nitride semiconductor layer 28 can be epitaxially grown on the GaN layers 24 and 26 without forming the GaN layer 27. Good. That is, in this case, the GaN layers 24 and 26 function as the first nitride semiconductor layer.

  In order to perform various evaluations of the semiconductor device 21 according to the second embodiment described above, for example, the longitudinal length of the gate electrode 32 is 1.5 mm, and the lateral length perpendicular to the longitudinal direction is 1 μm. I prepared something. In the gate electrode 32, the length in the short direction of the portion on the facets 27a and 27b is 500 nm. It can be said that the gate length is 500 nm because the portion that substantially functions as the gate is above the facets 27a and 27b. The length in the short direction of the source and drain electrodes 33 and 34 was 5 μm, the length between the source electrode 33 and the gate electrode 32 was 1 μm, and the length between the gate electrode 32 and the drain electrode 34 was 10 μm.

When various evaluations of the semiconductor device having such a size were performed, the maximum transconductance was 380 [mS / mm] and the maximum drain current was 350 [mA / mm]. The on-resistance per unit area was 2.8 [mmΩcm ² ]. The pinch-off voltage Vp was 0.61 [V], confirming the normally-off type. Further, when the pinch-off voltage Vp of a plurality of semiconductor devices of the same specification built on a substrate having a diameter of 3 inches was evaluated, the standard deviation was 0.04 V with respect to 0.61 [V] which is an average value. As a normally-off type, extremely good in-plane uniformity was obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made based on the technical idea of the present invention.

As shown in FIG. 14, the present invention is a semiconductor device having a MIS (metal-insulator-semiconductor) structure in which a gate insulating film 40 is interposed between the gate electrode 12 and the second nitride semiconductor layer 9. Is also applicable. Examples of the material of the gate insulating film 40 include SiN, AlN, and SiO ₂ . Of course, a similar gate insulating film may be interposed between the gate electrode 32 and the second nitride semiconductor layer 28 in the semiconductor device 21 shown in FIG.

  Examples of the material of the first and second nitride semiconductor layers include GaN, AlGaN, InGaN, InGaNAs, InGaNP, and AlInGaNP. Further, the first and second nitride semiconductor layers may have a structure in which a plurality of different types of nitride semiconductor layers are stacked.

Moreover, in the said embodiment, although the difference in film thickness was produced in the 2nd nitride semiconductor layer using the difference in the crystal growth rate in (1-101) plane and (0001) plane, these plane orientations Not limited to this, other plane orientations having such a relationship that a difference in the crystal growth rate and a difference in the film thickness may be used.
In the specification of the present application, “nitride semiconductor” refers to a chemical formula of InxAlyGa1-xyN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1), and the composition ratios x and y are within the respective ranges. It includes semiconductors of all compositions changed in In addition, the “nitride semiconductor” includes those further containing various impurities added to control the conductivity type.

1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention. It is a principal part perspective view of the semiconductor device which concerns on the 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment. FIG. 4 is a cross-sectional view showing a step that follows FIG. 3. FIG. 5 is a cross-sectional view showing a step that follows FIG. 4. FIG. 6 is a cross-sectional view showing a step that follows FIG. 5. FIG. 7 is a cross-sectional view showing a step that follows FIG. 6. It is principal part sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a principal part perspective view of the semiconductor device which concerns on the 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment. It is sectional drawing which shows the process following FIG. FIG. 12 is a cross-sectional view showing a step that follows FIG. 11. FIG. 13 is a cross-sectional view showing a step that follows FIG. 12. It is principal part sectional drawing of the semiconductor device which concerns on the modification of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Substrate 3 AlN layer 4 Non-doped GaN layer 5 Mask 6 Non-doped GaN layer 8 First nitride semiconductor layer (non-doped GaN layer)
8a Facet 8b, 8c Main surface 9 Second nitride semiconductor layer (n-type AlGaN layer)
DESCRIPTION OF SYMBOLS 11 Step part 12 Gate electrode 13 Source electrode 14 Drain electrode 21 Semiconductor device 22 Substrate 23 AlN layer 24 Non-doped GaN layer 25 Mask 26 Non-doped GaN layer 27 First nitride semiconductor layer (non-doped GaN layer)
27a, 27b Facet 27c Main surface 28 Second nitride semiconductor layer (n-type AlGaN layer)
31 Step 32 Gate electrode 33 Source electrode 34 Drain electrode 40 Gate insulating film

Claims (5)

A first layer made of a first nitride semiconductor and having a step on the upper surface;
The second nitride semiconductor has a band gap larger than that of the first nitride semiconductor, is stacked on the first layer so as to cover the step portion, and has a thickness on a side surface of the step portion. A second layer smaller than the thickness on the upper and lower main surfaces of the side surface;
A gate electrode provided on the second layer on the side surface of the step;
A source electrode provided on the second layer on one of the upper and lower main surfaces of the side surface;
A drain electrode provided on the second layer on the other of the upper and lower main surfaces of the side surface;
A semiconductor device comprising: The plane orientation of the main surface is (0001),
The semiconductor device according to claim 1, wherein a surface orientation of the side surface of the stepped portion is (1-101). A first layer made of a first nitride semiconductor and provided on the main surface with a facet inclined with respect to the main surface;
The first nitride semiconductor is made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor, and is stacked on the main surface and the facet of the first layer, and the thickness on the facet has a thickness on the main surface. A second layer smaller than the thickness above,
A gate electrode provided with the second layer sandwiched between the facets of the first layer;
A source electrode provided on a main surface lateral to the facet on the second layer;
A drain electrode provided on a main surface opposite to the source electrode on the second layer across the facet;
A semiconductor device comprising: The plane orientation of the main surface is (0001),
The semiconductor device according to claim 3, wherein the face orientation of the facet is (1-101). Epitaxially growing a first layer comprising a first nitride semiconductor and having a face orientation with a plane orientation having a crystal growth rate smaller than that of the main surface on the underlying crystal;
Epitaxially growing a second layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor on the main surface and the facet of the first layer;
Forming a gate electrode on the second layer over the facet of the first layer;
Forming a source electrode on a main surface on the side of the facet on the second layer;
Forming a drain electrode on the main surface of the second layer on the opposite side of the source electrode across the facet;
A method for manufacturing a semiconductor device, comprising:

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