JP2005285869A - Epitaxial substrate and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an epitaxial substrate for manufacturing FET which is superior in smoothness, by optimizing the combination of the off-angle of the main face of a sapphire substrate and the growth condition of a semiconductor laminate structural part. <P>SOLUTION: In the epitaxial substrate for manufacturing field effect transistor, the laminate structure formed of a nitride semiconductor is laminated on the main face of the sapphire substrate and the laminate structure has a heterostructure, where an electronic run layer consisting of gallium nitride or gallium nitride indium and a barrier layer consisting of aluminum nitride gallium are laminated sequentially. In the main face of the sapphire substrate, the off-angle α from a (01-12) face to a (0001) face satisfies 0°<x≤5°. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an epitaxial substrate on which a nitride semiconductor is grown and a semiconductor device using the same.

Aluminum nitride (hereinafter referred to as AlN), gallium nitride (hereinafter referred to as GaN), indium nitride (hereinafter referred to as InN), or a mixed crystal of them, aluminum gallium indium nitride (hereinafter referred to as Al _x Ga _{1−). Since} nitride-based semiconductors such as _xy In _y N (referred to as 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) can be used for light emitting / receiving elements and electron transit elements, A wide range of research has been conducted on crystal growth and application to semiconductor devices.

  Since nitride-based semiconductors cannot grow large bulk single crystals, they are generally heteroepitaxially grown using a heterogeneous substrate such as sapphire as a substrate for semiconductor growth.

  Epitaxial growth methods include metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), and halide vapor phase epitaxy (HVPE). The most common method for practical use is MOVPE. .

  Further, in the semiconductor device using the semiconductor element as described above, a structure in which a nitride semiconductor layer is stacked is epitaxially grown on the entire surface of the sapphire substrate, processed into a desired device shape, and then an electrode is formed. .

  Nitride-based semiconductor materials with a wide forbidden band have characteristics such as a high breakdown voltage, and can operate without breaking even under a high electric field, and are expected to be applied to semiconductor devices for high-power communication. .

  For example, in Patent Document 1, a field effect transistor (hereinafter referred to as an FET) is provided by a heterojunction that induces a high-density two-dimensional electron gas using a stacked structure portion 42 as shown in FIG.

First, an undoped GaN layer 422 having a thickness of 2 μm is grown on a sapphire substrate 41 (hereinafter referred to as a C-plane sapphire substrate) having a (0001) plane as a main surface through a buffer layer 421 having a thickness of 30 nm. , 30 nm undoped _Al 0.3 _{Ga 0.7} undoped _Al of the undoped GaN layer 424,10nm the n layer 423,10nm 0.3 _{Ga 0.7} n-type spacer layer 425,10nm of n _Al 0.3 Ga ₀ of _.7 N electron supply layer 426, 15 nm graded undoped Al _x Ga _1-x N barrier layer 427, 6 nm n-type Al _0.06 Ga _0.94 N contact layer 428 are sequentially laminated to form a laminated structure The portion 42 is formed to obtain the epitaxial substrate 4.

  A source electrode 431, a drain electrode 432, and a gate electrode 433 are formed on the epitaxial substrate 4 to obtain an FET.

  Thus, it is common to use the (0001) plane of the sapphire substrate or a plane with a small off-angle α from the (0001) plane (hereinafter, these are collectively referred to as the C plane). .

  Here, when the epitaxial substrate 4 made of a nitride-based semiconductor using the C-plane sapphire substrate 41 is manufactured, a nitride-based semiconductor having the C-plane as a main surface grows, and the influence of the piezoelectric field peculiar to the material is increased. In response, an inversion layer is formed in the vicinity of the interface of the heterojunction, so that a FET manufactured using the inversion layer is a so-called depletion type FET in which a drain current can already flow with a gate bias being zero.

  However, in reality, not only the above-described depletion type FET but also a so-called enhancement type FET in which the drain current cannot flow when the gate bias is zero and the drain current flows by applying the gate bias is also necessary.

  However, an FET using a nitride semiconductor does not have an enhancement type, and there are many restrictions on circuit design and its application is limited. Therefore, an enhancement type FET using a nitride semiconductor has been strongly desired.

  In order to manufacture the enhancement type FET, it is necessary to control the formation of the inversion layer in the semiconductor multilayer structure.

  For example, in an FET using a gallium arsenide-based semiconductor, the formation of an inversion layer can be controlled by adjusting the film thickness of a barrier layer made of aluminum gallium arsenide within a range of about several tens of nanometers. Depletion type and enhancement type Can be manufactured separately.

  The circuit design may have to be a depletion type FET, but on the other hand, it requires two types of power sources, plus and minus, to operate it, which consumes a lot of power and the electronic circuit that uses it. There was a problem that the number of parts increased.

  On the other hand, a nitride semiconductor on the C plane has a property that an inversion layer is easily generated at the interface of the heterojunction because the piezoelectric field is strong.

  For this reason, it is impossible to perform smooth growth even though it is necessary to grow a nitride-based semiconductor having a smooth surface with a surface orientation other than the C-plane that is not affected by the piezoelectric field. It was.

  Further, in the conventional low temperature buffer layer technology, a low temperature buffer layer having a film thickness of about several nanometers to several tens of nanometers is formed, but the C plane which is a typical plane orientation of sapphire as the substrate 11 for semiconductor growth. Alternatively, when the (11-20) plane is used, the underlying layer 121 laminated thereon is C-axis oriented, and the C-axis of the laminated structure and the perpendicular of the surface of the sapphire substrate coincide with each other, and the heterostructure is laminated. In this case, there is a problem that a piezo electric field is generated.

  In addition, when a nitride-based semiconductor layer is stacked on a (01-12) -plane sapphire substrate using a conventional low-temperature buffer layer technology, since the film thickness is thin, a smooth base layer cannot be formed. There was a problem that it was unsuitable for manufacturing a semiconductor device.

  In order to solve the above problem, for example, Patent Literature 2 already discloses a crystal growth method using a (01-12) plane sapphire substrate so that the C-axis of the laminated structure is parallel to the semiconductor growth substrate. In any case, the smoothness of the surface of the laminated structure portion is not described at all.

Further, there is no discussion about the operation of the FET when the crystal growth method is used.
Japanese Patent Laid-Open No. 10-335637 JP 2002-374003 A

  Surface smoothness is a very important factor when manufacturing FETs.

  However, even if the laminated structure is actually formed using a (01-12) plane fire substrate, it is rare that the surface becomes smooth, and it is difficult to obtain an FET using it. .

  Therefore, it has been necessary to provide an epitaxial substrate for manufacturing an FET with excellent smoothness by optimizing the combination of the off-angle of the main surface of the sapphire substrate and the growth conditions of the semiconductor multilayer structure.

  In view of the above, according to the present invention, a multilayer structure portion made of a nitride-based semiconductor is laminated on the main surface of a sapphire substrate, and the multilayer structure portion is made of at least gallium nitride or gallium indium nitride, and aluminum nitride. In an epitaxial substrate for manufacturing a field effect transistor having a heterostructure formed by sequentially stacking barrier layers made of gallium, the main surface of the sapphire substrate has an off-angle α from the (01-12) plane to the (0001) plane. Is a surface satisfying 0 ° <x ≦ 5 °.

In addition, an underlying layer made of aluminum gallium nitride Al _x Ga _1-x N satisfying a molar fraction x of aluminum nitride satisfying 0.5 ≦ x ≦ 1.0 is directly grown on the sapphire substrate. .

  The underlayer has a thickness in the range of 0.05 to 2.0 μm.

  In addition, the epitaxial substrate is used.

  By providing an epitaxial substrate made of a nitride-based semiconductor, enhancement-type FETs can be manufactured.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is a schematic view showing an epitaxial substrate 1 of the present invention.

On one main surface of the semiconductor growth substrate 11 made of a sapphire substrate, an underlayer made of aluminum nitride gallium Al _x Ga _1-x N with an AlN molar fraction x of 0.5 ≦ x ≦ 1.0. 121, an electron transit layer 122 made of GaN or GaInN, and a barrier layer 123 made of AlGaN are sequentially stacked.

  Then, the [0001] axis (d in the figure, hereinafter referred to as “C axis”) of the nitride-based semiconductor laminated structure 12 is set to be parallel to the main surface of the semiconductor growth substrate 11.

  As shown in FIG. 2, the angle formed by one main surface of the semiconductor growth substrate 11 and the sapphire (01-12) surface (b in the figure) is the off-angle α of the main surface of the semiconductor growth substrate 11, and the semiconductor growth The c-axis (c in the figure) of the working substrate 11 is inclined with respect to the main surface. In particular, in the case of a sapphire substrate whose main surface is such that 0 <α ≦ 5 ° (hereinafter referred to as (01-12) sapphire substrate), a base layer 121 grown on a (01-12) sapphire substrate. It is preferable that the C-axis (d in the figure) of the laminated structure portion 12 composed of the electron transit layer 122 and the barrier layer 123 is easy to grow so as to be parallel to the main surface.

  For this purpose, the AlN molar fraction of AlGaN constituting the underlayer 121 is preferably 0.5 to 1.0, and the film thickness is preferably 0.05 to 2.0 μm.

  When the off-angle α is 0 ° or larger than 5 °, the C-axis of the laminated structure portion 12 is not parallel to the main surface or cannot grow so as to have a smooth surface. There was a problem.

  The same problem occurs when the main surface is off-angled in the direction of the (11-20) plane.

In addition, when the film thickness of the underlayer 121 is larger than 2 μm, a crack occurs,
On the other hand, when the thickness is less than 0.05 μm, the growth that gives a smooth surface was not satisfied.

Here, the arithmetic average surface roughness of the nitride-based semiconductor layer 12 epitaxially grown may be measured by an atomic force microscope (AFM), and the root-mean-average surface roughness R _rms needs to be 10 nm or less. is there.

  However, according to the present invention, smooth growth of the surface is possible on the (01-12) sapphire substrate, and the C axis of the laminated structure portion 12 is oriented so as to be included in the plane of the laminated structure portion 12. The FET 3 can be made an enhancement type by not generating a piezo electric field in the direction of the perpendicular of the laminated structure portion 12.

  Even when smooth growth of the surface is possible, if the film thickness and composition of the underlayer 121 are not controlled and grown as in the present invention, cracks will occur in the laminated structure portion 12.

  Here, the electron transit layer 122 made of GaN or GaInN must not be doped with impurities in order to maintain electron mobility, but the film thickness may be in the range of 10 to 200 nm.

  Further, when GaInN is used for the electron transit layer 122, if the InN molar fraction is high, the two-dimensional electron gas density of the laminated structure portion 12 can be increased, but it is necessary because the mobility is lowered due to alloy scattering. Depending on the above, it is preferably 0.1 or less.

  Thereafter, a barrier layer 123 made of AlGaN is formed. The thickness of the barrier layer 123 is 5 to 50 nm, and a two-dimensional electron gas is formed at the interface between the electron transit layer 122 and the barrier layer 123 (when forming the inversion layer).

  Further, the barrier layer 123 is subjected to modulation doping, an undoped spacer layer (not shown) for the purpose of improving the electron mobility of the FET, and an electron supply layer (for example, doped with silicon for the purpose of supplying electrons). (Not shown).

  In addition, the electron transit layer 122 and the barrier layer 123 grown on the base layer 121 must have a crystal coherent with respect to the main surface of the base layer 121.

  Further, a contact layer 428 having a higher silicon density is grown on the barrier layer 123 with a film thickness of 3 to 20 nm for the purpose of easily forming an ohmic contact between the source electrode 31 and the drain electrode 32 as necessary. It may be allowed (not shown).

  The growth temperature of each layer may be set so as not to impair the characteristics of the epitaxial substrate 1 such as the composition, crystallinity, surface roughness, and electrical characteristics.

  Here, since the price of the (01-12) sapphire substrate 11 is low, sapphire whose principal surface is the C-plane or (11-20) plane, which is another typical plane orientation, is used as the semiconductor growth substrate 11. Compared to the above, there is an effect that the epitaxial substrate 1 can be manufactured at low cost.

  Next, an FET manufactured using the epitaxial substrate 1 will be described.

  As shown in FIG. 3, the FET 3 includes the epitaxial substrate 1, the source electrode 31, the drain electrode 32, and the gate electrode 33.

  The manufacturing method of FET3 should just use the existing photolithography technique, a vapor deposition technique, and an etching technique.

  For element isolation, for example, wet etching, dry etching, or the like can be used to perform mesa processing as shown in FIG. 3, or partial resistance can be increased by selective thermal oxidation or ion implantation. good.

  When the source electrode 31 and the drain electrode 32 are made of, for example, Ti / Al / Ti and then heat-treated at a temperature of 600 to 1000 ° C., a good ohmic junction can be formed.

  The gate electrode 33 is formed by, for example, stacking Ni / Au to form a Schottky junction.

  Finally, if Ti / Au is formed on the source, drain, and gate electrodes as pad electrodes, the FET 3 can be manufactured.

  The FET 3 manufactured as described above is a so-called enhancement type in which a drain current can flow when a gate bias is applied.

  As a first embodiment, an embodiment of the present invention will be described with reference to FIG.

  A MOVPE method was used as the growth method, and a (01-12) sapphire substrate was used as the semiconductor growth substrate 11. At this time, the off angle α in the (0001) plane direction was set to 1.0 °.

  Next, a base layer 121 made of AlN was grown at 200 nm at 1100 ° C., and an electron transit layer 122 made of GaN was grown at 50 nm at 1100 ° C.

  Next, a barrier layer 123 made of AlGaN having an AlN molar fraction of 0.25 at 1000 ° C. was grown to 27 nm.

  The barrier layer 123 was subjected to modulation doping and comprised of an undoped spacer layer 425 having a thickness of 7 nm and a silicon-doped electron supply layer 426 having a thickness of 20 nm (not shown), whereby the epitaxial substrate 1 was obtained. X-ray diffraction measurement confirmed that the C axis of the laminated structure portion 12 was in the plane of the laminated structure portion 12 and parallel to the main surface of the (01-12) sapphire substrate 11.

  Next, FET3 was manufactured using this epitaxial substrate 1. FIG.

  First, after forming a mask by photolithography, element isolation was performed by dry etching using a chlorine-based gas, and the etching depth was set to 60 nm.

  Next, Ti / Al / Ti are deposited to a thickness of 30/100/20 nm by electron beam evaporation to form a source electrode 31 and a drain electrode 32, and then heat-treated at 850 ° for 90 seconds in a nitrogen atmosphere. did.

  Next, Ni / Au was deposited to a thickness of 20/80 nm to form the gate electrode 33.

  Thus, the FET 3 of FIG. 3 was obtained, and it was an enhancement type in which a drain current flows when a gate bias is applied.

  Further, an epitaxial substrate was manufactured in the same manner as described above.

  In this case, AlGaN having an AlN molar fraction of 0.5 and a film thickness of 1 μm was used for the underlayer 121, and the growth temperature was 1000 °.

  Thereafter, an electron transit layer 122 made of GaN was grown to 50 nm at 1100 ° C.

  Next, a barrier layer 123 made of AlGaN having an AlN molar fraction of 0.25 at 1000 ° C. was grown to 27 nm.

  The barrier layer 123 was subjected to modulation doping, and was composed of a 7 nm undoped spacer layer and a 20 nm silicon doped electron supply layer 426 to obtain the epitaxial substrate 1. X-ray diffraction measurement confirmed that the C axis d of the laminated structure portion 12 was parallel to the main surface of the semiconductor growth substrate 11.

  The FET 3 obtained by the same method as described above using this epitaxial substrate 1 is as shown in FIG. 3, and is an enhancement type in which a drain current flows when a gate bias is applied.

Hereinafter, Examples 1 to 11 and Comparative Example 1 were prepared and evaluated under the conditions shown in Table 1 in order to compare the same evaluations as described above while changing the conditions.

  First, as in Comparative Examples 1 and 2, when a (01-12) sapphire substrate 11 having an off angle α of 0 ° and 6 ° was used, the surface roughness was increased.

  On the other hand, from Examples 1 to 4, the surface roughness was reduced when the off-angle α of the (01-12) sapphire substrate 11 was 0 ° <α ≦ 5 ° or less.

  Next, if the film thickness of the underlayer 121 is 0.05 to 2 μm as in Examples 6 and 7, the surface roughness can be kept small, but is smaller than 0.05 μm as in Example 5. And the surface roughness tended to increase.

  On the other hand, when the film thickness of the underlayer 121 is greater than 2 μm as in Example 8, there is a problem that cracks occur and the yield is lowered.

  Further, in order to investigate the optimal AlN mole fraction in the underlayer, when Examples 2, 9, 10, and 11 were compared, when the AlN mole fraction was smaller than 0.5, as in Example 9, There was a tendency for the surface roughness to deteriorate.

It is sectional drawing explaining the epitaxial substrate of this invention. It is sectional drawing explaining the crystal orientation relationship of a board | substrate and a laminated structure part of the epitaxial substrate of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is sectional drawing explaining the conventional semiconductor device.

Explanation of symbols

1 Epitaxial substrate 3 FET
4 Epitaxial Substrate 11 Semiconductor Growth Substrate ((01-12) Sapphire Substrate)
41 Semiconductor Growth Substrates 12, 42 Multilayer Structure (Nitride Semiconductor Layer)
31, 431 Source electrode 32, 432 Drain electrode 33, 433 Gate electrode 121 Underlayer 122 Electron transit layer 123 Barrier layer 421 Buffer layer 425 Spacer layer 426 Electron supply layer 427 Barrier layer 428 Contact layer α Off-angle a Semiconductor growth substrate 11 Normal line b of the main surface of the substrate (01-12) plane c of the semiconductor growth substrate 11 C axis of the semiconductor growth substrate 11 d C axis of the stacked structure portion 12

Claims (4)

A laminated structure portion made of a nitride semiconductor is laminated on the main surface of the sapphire substrate, and the laminated structure portion is sequentially laminated with an electron transit layer made of at least gallium nitride or gallium indium nitride and a barrier layer made of aluminum gallium nitride. In the epitaxial substrate for manufacturing a field effect transistor having a heterostructure as described above, the main surface of the sapphire substrate has an off angle α from the (01-12) plane to the (0001) plane direction of 0 ° <x ≦ 5 °. An epitaxial substrate characterized by being a surface satisfying the above. An underlayer made of aluminum gallium nitride Al _x Ga _1-x N satisfying a molar fraction x of aluminum nitride satisfying 0.5 ≦ x ≦ 1.0 is directly grown on the sapphire substrate. 2. The epitaxial substrate according to 1. The epitaxial substrate according to claim 2, wherein the film thickness of the underlayer is in the range of 0.05 to 2.0 μm. A semiconductor device using the epitaxial substrate according to claim 1.

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