JP2002374003A - Semiconductor device, and substrate for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be driven efficiently, and with fully improved element function. SOLUTION: An offset sapphire single crystal is used as a substrate. The offset sapphire single crystal has an offset surface, composed by rotating an R-surface sapphire single crystal or the R surface of the sapphire single crystal with an axis in 1 as the center, and a semiconductor layer made of a hexagonal group III nitride film, having a C axis in parallel with a film surface, is formed on the R surface or offset surface of the sapphire single crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a substrate for a semiconductor device, and more particularly to a semiconductor device which can be suitably used as a semiconductor light emitting device such as a light emitting diode device, and a method for manufacturing the semiconductor device. The present invention relates to a semiconductor element substrate that can be suitably used.

[0002]

2. Description of the Related Art Semiconductor devices such as semiconductor light emitting devices include:
It is easy to design physical properties such as band gap, and it can be easily multilayered by epitaxial growth,
As a result, hexagonal group III nitride semiconductors containing Al, Ga, In, and the like are used because desired device characteristics can be easily obtained.

FIG. 1 is a configuration diagram showing an example of a conventional semiconductor light emitting device. The semiconductor light emitting device 15 shown in FIG.
On a main surface 1A of a substrate 1 made of plane sapphire single crystal or the like, a low-temperature buffer layer 2 made of an AlN film or the like, a base layer 3 made of a GaN film or the like, an n-type conductive layer 4 made of an n-GaN film or the like, and n An n-type cladding layer 5 made of a GaN film or the like, a light emitting layer 6 made of an i-GaN film or the like, p-Ga
A p-type cladding layer 7 made of an N film or the like;
A p-type conductive layer 8 made of an aN film or the like is sequentially provided.

The semiconductor light emitting element 15 is partially etched away in the thickness direction to expose the exposed n.
An n-type electrode 9 is formed on the type conductive layer 4 and a p-type electrode 10 is formed on the p-type conductive layer 8 to constitute a so-called PIN type semiconductor light emitting device.

[0005] Such a PIN type semiconductor light emitting device 15
In, by applying a predetermined voltage between the n-type electrode 9 and the p-type electrode 10, electrons and holes are injected into the light emitting layer 7 via the n-type conductive layer 4 and the p-type conductive layer 8. . As a result, in the light emitting layer 7, the n-type clad layer 5
In addition, light corresponding to the band gap difference with the p-type cladding layer 7 is generated and emitted.

[0006]

However, the conventional semiconductor light emitting device as described above cannot realize a sufficiently high luminous efficiency and cannot generate and emit light of high output.

The present invention can be driven with high efficiency,
It is an object of the present invention to provide a semiconductor device having a sufficiently improved device function.

[0008]

In order to achieve the above object,
The present invention relates to a predetermined substrate and a semiconductor layer formed of a hexagonal group III nitride film having a C axis within a range of 10 degrees or less from a direction parallel to the film surface, which is epitaxially grown above a main surface of the substrate. And a semiconductor device comprising:

The present inventors have conducted intensive studies to improve the luminous efficiency of a semiconductor device, especially a semiconductor light emitting device, and to obtain a high output. As a result, they have found that the improvement of the luminous efficiency is affected by the crystallinity based on the dislocation and orientation of the semiconductor layer constituting the semiconductor light emitting device. Then, while reducing dislocations in the semiconductor layer and improving characteristics of an underlayer used when forming the semiconductor layer, the crystallinity of the semiconductor layer is improved, and an attempt is made to improve the luminous efficiency. Have been.

However, as a result of further study, when the semiconductor layer is made of a group III nitride containing Al, Ga, In and the like, the semiconductor layer is formed due to the inherent ferroelectricity and piezoelectricity of the group III nitride. It has been found that the luminous efficiency of the semiconductor light emitting device and the like is reduced.

That is, the semiconductor light emitting device 15 shown in FIG.
In the above, for example, the above-described i-GaN film constituting the light emitting layer 6 is formed with the C-axis oriented in a direction perpendicular to the film surface. The ferroelectricity described above appears parallel to the C axis. As a result, an electric field is generated in the light emitting layer 6 in a direction perpendicular to the film surface as shown by an arrow A in the figure. Furthermore, i-G
Even when the aN film receives a pressure from the outside due to a lattice mismatch or the like, an electric field as shown by an arrow A in the figure, which is parallel to the C axis, is generated based on its piezoelectricity.

Therefore, since the electrons and holes in the light emitting layer 6 are separated from each other and exist separately,
applying a predetermined voltage between the n-type electrode 9 and the p-type electrode 10,
When a current flows in a direction perpendicular to the light emitting layer 6, the probability of recombination of electrons and holes decreases, and the luminous efficiency decreases. Such a tendency is remarkable when a group III nitride film having a low In concentration, in which microconfinement of carriers cannot be sufficiently expected, is used, or in a high current injection region.

Therefore, the present inventors have conducted further studies in order to suppress the deterioration of the luminous efficiency due to the above-mentioned ferroelectricity and piezoelectricity. As a result, the present inventor has conceived that instead of the semiconductor film forming the light emitting layer or the like being oriented in the C-axis perpendicular to the film surface, the semiconductor film is oriented in the C-axis parallel to the film surface. Since the electric field caused by the above-described ferroelectricity and piezoelectricity appears parallel to the C-axis, in this case, the electric field caused by the ferroelectricity and the piezoelectricity is a diagram parallel to the main surface of the light emitting layer 6. It occurs in the direction indicated by the middle arrow B. Therefore, in the light emitting layer 6, electrons and holes are separated in a direction indicated by an arrow B parallel to the main surface.

On the other hand, a vertical electric field is applied to the light-emitting layer 6 through the n-type electrode 9 and the p-type electrode 10, thereby causing a current to flow in the vertical direction. Even if the electrons and holes are present separately in parallel with the main surface of the light emitting layer 6, the current flow in the vertical direction is not affected at all. Therefore, the electrons and holes in the light emitting layer 6 recombine without being affected by the electric field due to ferroelectricity or the like, so that the probability increases, and as a result, the luminous efficiency can be improved. You can do it.

The semiconductor device according to the present invention has the above-described P
In addition to the IN-type semiconductor light-emitting device, other semiconductor light-emitting devices, and various semiconductor light-receiving devices, in which an electric field generated due to the above-described ferroelectricity and / or piezoelectricity of the semiconductor film causes characteristic deterioration. It can be applied to elements, various electronic devices, and the like.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments of the present invention. The type of the substrate constituting the semiconductor element of the present invention includes a semiconductor layer made of a hexagonal group III nitride film having a C axis within a range of 10 degrees or less from a direction parallel to the film surface above the main surface. There is no particular limitation as long as it can be formed. It can be composed of any substrate depending on the type of the semiconductor element. However, preferably, a sapphire single crystal, a wurtzite structure single crystal, or a hexagonal SiC is used, and the main surface of the substrate is made of the R sapphire single crystal.

[Outside 2] Alternatively, it is preferable to configure a plane including the C axis of a wurtzite structure single crystal or hexagonal SiC, for example, a (hki0) plane (h and k are arbitrary integers, i = − (h + k)).

Further, an offset sapphire single crystal having a main surface as an offset surface obtained by rotating the R-plane of the sapphire single crystal about the [outside 1] axis may be used. Alternatively, a wurtzite structure single crystal or an offset wurtzite structure single crystal or an offset hexagonal crystal having a crystal plane including a C axis of a hexagonal SiC as a main surface obtained by offsetting the C axis. Si
C can also be used. Also in this case, a hexagonal group III nitride film having a C-axis can be easily formed within a range of 10 degrees from a direction parallel to the film surface by using a normal film forming method.

FIG. 2 is a view showing a crystal structure unit of a sapphire single crystal, and FIG. 3 is a plane showing a positional relationship between the R plane and the offset plane in the sapphire single crystal with respect to a C axis and a C plane. FIG.

As apparent from FIGS. 2 and 3, the R-plane of the sapphire single crystal is 57.70 ° from the C-plane direction perpendicular to the C-axis.
It is located at an inclination of 6 ° C. Then, the offset surface of the sapphire substrate, as shown in FIG.
The surface is rotated toward the C axis by an angle θ with respect to the [outside 1] axis, or as shown in FIG. It is obtained by rotating the R-plane by an angle φ with respect to the [outside 1] axis in a direction opposite to the C-axis.

The magnitudes of the angles θ and φ are preferably 0.
More than twice. In addition, the magnitude of the angle φ is 1 degree or more. Although the upper limit is not particularly limited,
Degree or less.

In addition, wurtzite structure single crystal and hexagonal S
When a plane including the C-axis of iC is used as the main plane, it is preferable that the crystal plane obtained by offsetting the C-axis be the main plane, and the angle is 0.2 degrees or more, particularly 1 degree or more. It is preferred that

When the substrate is formed from the above-mentioned offset single crystal obtained by rotating at an angle smaller than this or the single crystal not offset, the inverted twin crystal is formed in the hexagonal group III nitride film constituting the semiconductor layer. Crystals may be formed and the crystallinity may be deteriorated.

A substrate such as the above-described sapphire single crystal, wurtzite structure single crystal, and hexagonal SiC is integrated with the group III nitride film formed on the substrate made of the substrate. Thereby, it can be used as a substrate for a semiconductor element.

As described above, the semiconductor device of the present invention
It can be used for semiconductor light emitting elements, semiconductor light receiving elements, electronic devices, and the like. In particular, by using a semiconductor layer made of a hexagonal group III nitride film having a C-axis parallel to the film surface as a light emitting layer, ferroelectricity and / or
Alternatively, a reduction in the luminous efficiency due to the piezoelectricity is suppressed to achieve the maximum effect. Therefore, the semiconductor device of the present invention is particularly preferably used as a semiconductor light emitting device.

[0025]

The present invention will be described below in detail with reference to examples. (Example) An R-plane offset sapphire single crystal offset by 4 degrees in the direction opposite to the C-axis was used as a substrate, and was mounted on a susceptor installed in a quartz reaction tube.
Next, the substrate is moved to 1 by a heater in the susceptor.
Heated to 100 ° C.

Next, the pressure was set to 20 Torr, the substrate temperature was set to 1100 ° C., trimethyl aluminum (TMA) was used as an Al supply material, and ammonia gas (NH ₃ ) was used as a nitrogen supply material. A gas was introduced into the reaction tube together with the hydrogen carrier gas, and was supplied onto the substrate. Here, the gas supply molar ratio of TMA and NH ₃ is:
1: 2000. Then, an AlN film as an underlayer was formed to a thickness of 1 μm by epitaxial growth for 60 minutes.

When the orientation of the AlN film was examined by X-ray diffraction, it was found that the C-axis was almost parallel to the film surface, and the A-plane of AlN was growing with respect to the R-plane of sapphire. did. Next, once the substrate is taken out, Al
The surface of the N film was polished.

Next, the pressure was set to 100 Torr, the substrate temperature was set to 1050 ° C., trimethyl gallium (TMG) was used as a Ga supply material, and NH ₃ was used.
TMG and NH ₃ with gas and hydrogen carrier gas
So that the gas supply molar ratio becomes 1: 2000.
The Si-doped n-GaN film as an n-type conductive layer was formed to a thickness of 3 μm by performing epitaxial growth for 60 minutes while simultaneously supplying the N film and the SiH ₄ gas.

Next, TMG, TMA, and NH ₃ gas were supplied together with the hydrogen carrier gas so that the gas supply molar ratio was 8: 2: 20000, and the n-GaN was mixed with the hydrogen carrier gas.
By performing epitaxial growth for one minute while simultaneously supplying SiH ₄ gas on the film,
Si-doped n-Al _0.15 as n-type cladding layer
A Ga _0.85 N film was formed to a thickness of 0.02 μm.

Next, the substrate temperature was set to 900 ° C.
MG, TMI, and NH ₃Gas is transferred to these gas supply modes.
Hydrogen ratio to 9: 1: 100000.
N-Al together with carrier gas_0.15Ga_0.85
Supplying on N film and epitaxially growing for 1 minute
As a result, i-In as a light emitting layer_0.01Ga_0.99
An N film was formed to a thickness of 5 nm. Note that this i-In
_0.01Ga_{0 . 99}The orientation of the N film is determined by X-ray diffraction
Inspection revealed that the film had a C axis substantially parallel to the film surface, and the surface A was the main surface.
It was found to be formed as.

Next, TMG, TMA, and NH ₃ gas were supplied at a gas supply molar ratio of 95: 5: 200000.
And i-I together with the hydrogen carrier gas.
The i-Al _0.05 Ga _0.95 N film as a p-type cladding layer is supplied to the n _0.01 Ga _0.99 N film and epitaxially grown for 30 seconds to form a p-type cladding layer having a thickness of 0.00
It was formed to 5 μm.

Next, the substrate temperature was set to 1050 ° C.
The source gas other than the TMA is replaced with the i-Al _0.05 Ga
The Mg-doped p-Ga as the p-type conductive layer is obtained by performing epitaxial growth for 30 minutes while simultaneously supplying Cp ₂ Mg gas while supplying on the _0.95 N film.
An N film was formed to a thickness of 0.5 μm.

After the growth is completed, a part of the multilayer film formed as described above is removed until the n-GaN film is exposed,
A p-type electrode made of Au / Ni is formed on the p-GaN film, and Al / Ti is formed on the exposed surface of the n-GaN film.
Was formed to obtain a PIN-type semiconductor light-emitting device.

Thereafter, when a voltage of 5 V was applied between the p-type electrode and the n-type electrode, light emission with an efficiency of 30 lm / W was confirmed.

(Comparative Example) Each semiconductor film was produced in the same manner as in Example except that a C-plane sapphire single crystal was used as a substrate, and a PIN type semiconductor light emitting device was obtained. In this case, it was confirmed that the C axis of the n-GaN film underlying layer was perpendicular to the film surface, and the C axis of the i-In _0.01 Ga _0.99 N film light emitting layer was also perpendicular to the film surface. Was. When the luminous efficiency of the semiconductor light emitting device thus obtained was examined in the same manner as in the example, light emission with an efficiency of 10 lm / W was confirmed.

As is clear from the above examples and comparative examples, i-I having a C-axis substantially parallel to the film surface according to the present invention.
The semiconductor light emitting device including the n _0.01 Ga _0.99 N film light emitting layer is made of i-In _0.01 G having a C axis perpendicular to the film surface.
It can be seen that the luminous efficiency is greatly improved as compared with the semiconductor light emitting device having the a _0.99 N film light emitting layer.

Further, by using an offset R-plane sapphire single crystal as a substrate, an n-GaN underlayer having a C-axis substantially parallel to the film surface, and a desired i-In
_It can be seen that the _0.01 Ga _0.99 N film light emitting layer can be easily formed.

As described above, the present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above-described embodiments and does not depart from the scope of the present invention. All changes and modifications are possible. For example, in the above embodiment, it is assumed that the same CVD apparatus is used for fabricating the multilayer structure, but different CVD apparatuses may be used for each layer. During the formation of each layer, the surface can be smoothed by performing a polishing treatment or the like. Conversely, as described above, the polishing process for the AlN film as the underlayer is omitted, and the underlayer and the predetermined multilayer film structure formed thereon are formed in the same CV.
It can also be manufactured with a D apparatus.

[0039]

As described above, according to the semiconductor device of the present invention, it is possible to effectively suppress a decrease in device functions such as luminous efficiency due to ferroelectricity and / or piezoelectricity.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of a PIN semiconductor light emitting device.

FIG. 2 is a view showing a crystal structure unit of a sapphire single crystal.

FIG. 3 is a plan view showing a positional relationship between an R plane and an offset plane of a sapphire single crystal with respect to a C axis and a C plane.

[Explanation of symbols]

Reference Signs List 1 substrate, 2 low-temperature buffer layer, 3 underlayer, 4 n-type conductive layer, 5 n-type clad layer, 6 light-emitting layer, 7 p-type clad layer, 8 p-type conductive layer, 9 n-type electrode, 10 p-type electrode , 15 Semiconductor light emitting device

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Keiichiro Asai 2-56 Sudacho, Mizuho-ku, Nagoya, Aichi Prefecture Inside Nihon Insulator Co., Ltd. (72) Mitsuhiro Tanaka 2-56, Sudacho, Mizuho-ku, Nagoya-shi, Aichi Prefecture No. F-term in Nihon Insulators Co., Ltd. (reference) 5F041 AA03 CA04 CA14 CA23 CA40 CA65 CA82

Claims (17)

[Claims] An epitaxial growth is performed on a predetermined substrate and above the main surface of the substrate, and a predetermined substrate is formed in a direction parallel to the film surface.
Within a range of degrees, a semiconductor layer comprising a hexagonal group III nitride film having a C axis,
Semiconductor element. 2. The method according to claim 1, wherein the substrate is made of sapphire single crystal.
2. The semiconductor device according to claim 1, wherein the main surface of the substrate is formed by an R-plane of the sapphire single crystal. 3. 3. The substrate according to claim 1, wherein the sapphire single crystal has an R-plane. 2. The semiconductor device according to claim 1, comprising an offset sapphire single crystal whose main surface is an offset surface rotated about an axis. 4. The offset plane of the offset sapphire single crystal is obtained by rotating the R plane of the sapphire single crystal by at least 0.2 degree around an [outside 1] axis. Item 4. A semiconductor device according to item 3. 5. The offset plane of the offset sapphire single crystal is formed by rotating the R plane of the sapphire single crystal about the [outside 1] axis at least once in a direction opposite to the C axis of the sapphire single crystal. The semiconductor device according to claim 4, wherein: 6. The substrate comprises a wurtzite structure single crystal or a hexagonal SiC single crystal, and the main surface of the substrate has a C axis of the wurtzite structure single crystal or the hexagonal SiC single crystal. The semiconductor device according to claim 1, wherein the semiconductor device comprises a plane including the semiconductor element. 7. The substrate comprises a wurtzite structure single crystal or a hexagonal SiC single crystal, and the main surface of the substrate has a C axis of the wurtzite structure single crystal or the hexagonal SiC single crystal. 7. The semiconductor device according to claim 6, wherein the crystal plane includes an offset crystal plane obtained by offsetting the C-axis. 8. The offset plane of the wurtzite structure single crystal or the hexagonal SiC single crystal has the C axis set at 0.
The semiconductor device according to claim 7, wherein the semiconductor device is offset at least twice. 9. The semiconductor device according to claim 1, wherein said hexagonal group III nitride semiconductor layer constitutes a light emitting layer, and said semiconductor element constitutes a semiconductor light emitting element. Semiconductor element. 10. A hexagonal group III nitride film which is epitaxially grown above a main surface of a predetermined base material and has a C axis within a range of 10 degrees from a direction parallel to the film surface. A substrate for a semiconductor device, comprising: 11. The sapphire single crystal according to claim 11, wherein said base material is made of sapphire single crystal.
The substrate for a semiconductor element according to claim 10, wherein the substrate is constituted by a surface. 12. The base material is made of an offset sapphire single crystal whose main surface is an offset plane obtained by rotating the R plane of the sapphire single crystal about the [outside 1] axis. A substrate for a semiconductor element according to claim 10. 13. The offset plane of the offset sapphire single crystal, wherein the R plane of the sapphire single crystal is rotated by 0.2 degrees or more about an [outside 1] axis. Item 13. A substrate for a semiconductor element according to item 12. 14. The offset plane of the offset sapphire single crystal is obtained by rotating the R plane of the sapphire single crystal at least once about the [outside 1] axis in a direction opposite to the C axis of the sapphire single crystal. The substrate for a semiconductor element according to claim 13, wherein: 15. The base material is composed of a wurtzite structure single crystal or a hexagonal SiC single crystal, and the main surface of the base material is
11. A plane including the C-axis of the wurtzite structure single crystal or the hexagonal SiC single crystal.
3. The substrate for a semiconductor element according to item 1. 16. The base material is made of a wurtzite structure single crystal or a hexagonal SiC single crystal, and the main surface of the base material is
The crystal plane including a C axis of the wurtzite structure single crystal or the hexagonal SiC single crystal is constituted by an offset crystal plane obtained by offsetting the C axis. A substrate for a semiconductor element as described in the above. 17. The method according to claim 16, wherein the offset plane of the wurtzite structure single crystal or the hexagonal SiC single crystal is obtained by rotating the C axis by 0.2 degrees or more. Semiconductor element.