JPH0677537A - Light emitting diode - Google Patents

Light emitting diode

Info

Publication number
JPH0677537A
JPH0677537A JP22411092A JP22411092A JPH0677537A JP H0677537 A JPH0677537 A JP H0677537A JP 22411092 A JP22411092 A JP 22411092A JP 22411092 A JP22411092 A JP 22411092A JP H0677537 A JPH0677537 A JP H0677537A
Authority
JP
Japan
Prior art keywords
lead member
electrode
light emitting
element chip
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP22411092A
Other languages
Japanese (ja)
Inventor
Hiromasa Gotou
広将 後藤
Hideaki Imai
秀秋 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP22411092A priority Critical patent/JPH0677537A/en
Publication of JPH0677537A publication Critical patent/JPH0677537A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To obtain an LED excellent in characteristics with high reproducibility, by connecting an element chip using an insulative substrate with a lead member, by using die bonding together with wire bonding. CONSTITUTION:When a lead member has a notch part, the electrode part 18 of an element chip 20 is connected with a lead member 16 by a bonding method, and then an electrode 19 is connected with a lead member 15 by using a wire. When a lead member has a hole part, an electrode part 18 of the element chip 20 is connected with the lead member 22 by a die bonding method, and then the electrode 19 is connected with a lead 21 by using a wire. As the material for die bonding of the light emitting chip and the lead member, e.g. Au-Si, Pb-Sn alloy based solder is used. Thereby a stable LED of high quality is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、透明絶縁性基板を用い
た発光素子チップをリードフレームに実装した発光ダイ
オードに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode in which a light emitting element chip using a transparent insulating substrate is mounted on a lead frame.

【0002】[0002]

【従来の技術】従来、実用化されている発光ダイオード
(LED)に実装されている素子チップはGaAs、I
nPなどの導電性基板を用いていることから正負の電極
部は素子チップの表と裏に形成されていた。従来のリー
ドフレームに素子チップを実装し樹脂で封止したLED
の断面図を図11に示す。上述したように導電性基板を
用いて作製した素子チップは表と裏に電極を有する構造
をとっているため、この素子チップ20をリードフレー
ム52に接着する場合には片方の電極をリードフレーム
のミラー部14にハンダあるいは導電性ペーストにより
接着し、もう片方の電極はワイヤーボンディング法によ
ってリード部材50に接続するような構造をとってい
た。 このリード部材50、51に素子チップを実装し
た後にエポキシ樹脂などで封止してLED30を形成し
ていた。 近年では、透明絶縁性基板を用いたフリップ
チップ方式の素子チップによるLEDが提案されてい
る。(特開平4ー10670)この透明絶縁性基板上に
発光層を形成した発光素子チップを用いて作製したLE
Dとしては、図12に示すような構造であり、素子チッ
プ20の電極25、26は正負の電極とも発光層側に位
置し、リード部材54、53との接続は、ハンダあるい
は導電性ペーストにより行われていた。
2. Description of the Related Art Conventionally, element chips mounted on a light emitting diode (LED) which has been put into practical use are GaAs and I.
Since a conductive substrate such as nP is used, the positive and negative electrode parts are formed on the front and back of the element chip. LED with element chip mounted on conventional lead frame and sealed with resin
A cross-sectional view of the is shown in FIG. Since the element chip manufactured using the conductive substrate as described above has a structure having electrodes on the front and back sides, when adhering this element chip 20 to the lead frame 52, one electrode of the lead frame is The structure is such that it is adhered to the mirror portion 14 with solder or a conductive paste, and the other electrode is connected to the lead member 50 by a wire bonding method. After mounting the element chips on the lead members 50 and 51, the LED 30 is formed by sealing with an epoxy resin or the like. In recent years, an LED with a flip-chip type element chip using a transparent insulating substrate has been proposed. (JP-A-4-10670) LE manufactured by using a light emitting element chip in which a light emitting layer is formed on this transparent insulating substrate.
D has a structure as shown in FIG. 12, the electrodes 25 and 26 of the element chip 20 are located on the light emitting layer side with both positive and negative electrodes, and the connection with the lead members 54 and 53 is made by soldering or conductive paste. It was done.

【0003】[0003]

【発明が解決しようとする課題】上述したように発光素
子チップに導電性基板を用いたときには、基板に電流を
流すことができるので、正負の電極は基板側に1つ、発
光層側に1つ形成することが可能である。リードフレー
ムに接続する際には基板側の電極をリード部材にダイボ
ンディングし、発光層側の電極は他のリード部材にワイ
ヤーボンディングするという方法でLEDを作製してい
た。しかし、透明絶縁性基板を素子チップに用いた場合
には、発光層側に正負一対の電極を有するフリップチッ
プ方式をとるため、素子チップとリード部材の接続は上
述した接続方法をとることができない。このため、発光
層側に形成された2種の電極をリードフレームに接続す
るためには、2本のリード部材の素子チップとの接続面
は平坦にして、この平坦面に素子チップの電極面をハン
ダあるいは導電性ペーストにより接着する工程をとる。
しかしこの方法では、同一面内に2種の電極を形成しな
ければならないため1mm角以下の素子チップサイズで
は電極サイズは200μm以下としなけらばならず、ハ
ンダあるいは導電性ペーストによる接着工程において2
種の電極部が接触してしまうという問題があった。ま
た、素子チップサイズに対するハンダあるいは導電性ペ
ーストにより接着される電極面積が広いため、より効率
よく発光させるために用いられるミアンダ状、ネット状
あるいはクシ状のような複雑な電極パターンを形成する
ことはできなかった。あるいは、1つのLEDから2色
以上の発光を得る多色発光ダイオードを作製する場合に
は、3箇所以上の電極部を必要とするため電極面積はさ
らに小さくしなければならず、ハンダあるいは導電性ペ
ーストによる電極とリード部材との接続は不可能であっ
た。
As described above, when a conductive substrate is used for the light emitting element chip, a current can be passed through the substrate, so that one positive and negative electrode is provided on the substrate side and one is provided on the light emitting layer side. It is possible to form one. When connecting to a lead frame, an LED was produced by a method in which an electrode on the substrate side was die-bonded to a lead member and an electrode on the light emitting layer side was wire-bonded to another lead member. However, when the transparent insulating substrate is used for the element chip, the flip chip method having a pair of positive and negative electrodes on the light emitting layer side is adopted, and therefore the element chip and the lead member cannot be connected by the above-described connection method. . Therefore, in order to connect the two kinds of electrodes formed on the light emitting layer side to the lead frame, the connecting surfaces of the two lead members with the element chip should be flat, and the electrode surface of the element chip should be placed on this flat surface. A step of bonding with a solder or a conductive paste.
However, in this method, two kinds of electrodes must be formed in the same plane, so that the electrode size must be 200 μm or less for the element chip size of 1 mm square or less.
There is a problem that the seed electrode portions come into contact with each other. In addition, since the electrode area adhered by solder or conductive paste with respect to the element chip size is large, it is not possible to form a complicated electrode pattern such as meander shape, net shape, or comb shape used for more efficient light emission. could not. Alternatively, when a multicolor light emitting diode that obtains light emission of two or more colors from one LED is produced, the electrode area must be further reduced because three or more electrode portions are required, and solder or conductive It was impossible to connect the electrode and the lead member with the paste.

【0004】本発明は、前記問題点を解決して簡単に再
現よく発光特性の良好なLEDを提供しようとするもの
である。 課題を解決するための手段 本発明者らは前記問題点を解決するために鋭意研究を重
ねた結果、絶縁性基板を用いた素子チップとリード部材
を接続する際に、ダイボンディングとワイヤーボンディ
ングを併用することで、再現よく良好な特性を有するL
EDを得ることができるようになったものである。
The present invention is intended to solve the above-mentioned problems and to provide an LED which has good emission characteristics in a simple and reproducible manner. Means for Solving the Problems As a result of intensive studies to solve the above problems, the present inventors have conducted die bonding and wire bonding when connecting an element chip and a lead member using an insulating substrate. L which has good characteristics with good reproducibility when used together
It is now possible to obtain an ED.

【0005】すなわち、本発明は透明絶縁性基板上にn
型半導体層、p型およびi型半導体層から選ばれた2種
以上の組合せからなる発光層を少なくとも一つ有し、か
つ半導体層の所定の部位に発光層に電圧を印加するため
の電極を有するプレーナ構造の素子チップにおいて、一
つの電極をリード部材と直接に接続され、かつ他の少な
くとも一つの電極が他のリ−ド部材とワイヤ−により接
続されていることを特徴とする発光ダイオードを提供す
るものである。
That is, according to the present invention, n is formed on a transparent insulating substrate.
Type semiconductor layer, at least one light emitting layer composed of a combination of two or more selected from p type and i type semiconductor layers, and an electrode for applying a voltage to the light emitting layer at a predetermined portion of the semiconductor layer. In a device chip having a planar structure, a light emitting diode characterized in that one electrode is directly connected to a lead member and at least one other electrode is connected to another lead member by a wire. It is provided.

【0006】本発明における透明絶縁性基板としては、
360nmから900nmの範囲で透過率が80%以上
を有することが好ましく、代表的なものとしてサファイ
ア、(Al2 3 )、石英(SiO2 )、酸化マグネシ
ウム(MgO)、チタン酸ストロンチウム(SrTiO
3 )、フッ化カルシウム(CaF2 )、フッ化マグネシ
ウム(MgF2 )、酸化チタン(TiO2 )などがある
が、その他透明で絶縁性のものであればなんでもよい。
しかし、基板上に直接形成する半導体薄膜の格子定数が
この透明絶縁性基板の格子定数に極力合ったたものを用
いるのがよい。この透明絶縁性基板と基板上に直接形成
する半導体薄膜との格子不整合は10%以下とするのが
好ましく、さらに好ましくは5%以下とするのがよい。
このために該透明絶縁性基板を所定の角度だけオフした
ものを使用することも好ましいものである。例えばGa
Nの場合はサファイアR面を9.2゜オフした基板を用
いることが好ましいものとなる。透明絶縁性基板と半導
体薄膜との格子不整合が非常に大きい場合には、この透
明絶縁性基板と半導体薄膜との間にバッファ層を設けて
もよい。バッファ層としてはアモルファス状の物質、例
えばAlN、GaN、Si、SiCなど、あるいは単結
晶物質として、例えばAlN、ZnO、SiC等を設け
ることができる。
As the transparent insulating substrate in the present invention,
It is preferable that the transmittance is 80% or more in the range of 360 nm to 900 nm, and typical examples thereof include sapphire, (Al 2 O 3 ), quartz (SiO 2 ), magnesium oxide (MgO), and strontium titanate (SrTiO 3).
3 ), calcium fluoride (CaF 2 ), magnesium fluoride (MgF 2 ), titanium oxide (TiO 2 ), etc., but any other transparent and insulating material may be used.
However, it is preferable that the semiconductor thin film formed directly on the substrate has a lattice constant that matches the lattice constant of the transparent insulating substrate as much as possible. The lattice mismatch between the transparent insulating substrate and the semiconductor thin film formed directly on the substrate is preferably 10% or less, more preferably 5% or less.
Therefore, it is also preferable to use the transparent insulating substrate which is turned off at a predetermined angle. For example Ga
In the case of N, it is preferable to use a substrate in which the sapphire R plane is off by 9.2 °. When the lattice mismatch between the transparent insulating substrate and the semiconductor thin film is very large, a buffer layer may be provided between the transparent insulating substrate and the semiconductor thin film. As the buffer layer, an amorphous substance such as AlN, GaN, Si, or SiC, or a single crystal substance such as AlN, ZnO, or SiC can be provided.

【0007】本発明において透明絶縁性基板上に発光層
を形成する方法としては、MBE(Molecular
Beam Epitaxy)法、CBE(Chemi
cal Beam Epitaxy)法、MOMBE
(Metal OrganicMBE)法、CVD(C
hemical Vapour Depositio
n)法、MOCVD(Metal Organic C
VD)法等の半導体成長装置を用いることができる。上
記した薄膜作製方法により透明絶縁性基板上に発光層を
形成する。この発光層はMIS構造、pn接合を有する
シングルヘテロ構造およびダブルヘテロ構造、あるいは
量子井戸構造あるいは超格子構造のいずれでもよい。
In the present invention, a method for forming a light emitting layer on a transparent insulating substrate is MBE (Molecular).
Beam Epitaxy) method, CBE (Chemi)
cal beam epitaxy method, MONBE
(Metal Organic MBE) method, CVD (C
chemical Vapor Deposition
n) method, MOCVD (Metal Organic C)
A semiconductor growth apparatus such as the VD) method can be used. The light emitting layer is formed on the transparent insulating substrate by the above-described thin film manufacturing method. This light emitting layer may have any of a MIS structure, a single hetero structure having a pn junction and a double hetero structure, a quantum well structure or a superlattice structure.

【0008】本発明における発光層とは、n型半導体
層、p型およびi型半導体層から選ばれた2種以上の組
み合わせからなる発光層のことである。また、これらの
発光層を形成する半導体は、IIIーV族化合物半導
体、IIーVI族化合物半導体のどちらでもよいが、I
IIーV族化合物半導体であるGaN系半導体は透明絶
縁性基板であるサファイア、CaF2 、MgO等に結晶
性の良好な薄膜の成長が可能であり特に好ましいもので
ある。
The light emitting layer in the present invention is a light emitting layer composed of a combination of two or more kinds selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer. The semiconductor forming these light emitting layers may be either a III-V group compound semiconductor or a II-VI group compound semiconductor.
A GaN-based semiconductor, which is a II-V group compound semiconductor, is particularly preferable because it can grow a thin film having good crystallinity on a transparent insulating substrate such as sapphire, CaF 2 , and MgO.

【0009】本発明での発光素子チップは透明絶縁性基
板を用いるために発光層側の同一平面内に正負一対の電
極を形成する必要があり、発光層のエッチングを行わな
ければならない。この発光素子チップ作製のために行う
エッチング方法としては発光層の種類により、ウエット
エッチング法、ドライエッチング法のどちらを用いても
よい。エッチング後に熱処理を行うことも好ましいこと
であり、この熱処理を行うことによりエッチングにより
受けた膜質の劣化を回復することができ、界面抵抗を下
げて低電圧で発光に必要な電流を得ることができる。熱
処理を行う装置としては管状炉、ランプアニール炉等の
雰囲気を制御できる炉であればよい。
Since the light emitting device chip of the present invention uses the transparent insulating substrate, it is necessary to form a pair of positive and negative electrodes in the same plane on the light emitting layer side, and the light emitting layer must be etched. Either an wet etching method or a dry etching method may be used as an etching method for manufacturing the light emitting element chip, depending on the type of the light emitting layer. It is also preferable to perform heat treatment after etching, and by performing this heat treatment, deterioration of the film quality that has been caused by etching can be recovered, and the interface resistance can be lowered to obtain the current necessary for light emission at low voltage. . The apparatus for heat treatment may be a furnace capable of controlling the atmosphere such as a tubular furnace or a lamp annealing furnace.

【0010】本発明における発光素子チップの電極形成
方法としては、MBE法、真空蒸着法、電子ビーム蒸着
法、スパッタ法等がある。電極材料としてはn型半導体
とp型あるいはi型半導体それぞれにオーミック接触が
得られるものが好ましく、金属単体でもよく、2種以上
の金属を混合して合金化したものを用いてもよい。この
オーミック接触を得るための条件はn型半導体側の電極
としては半導体の仕事関数よりも小さな仕事関数を有す
る金属がよく、p型半導体側の電極としては半導体の仕
事関数よりも大きな仕事関数を有する金属を用いるのが
よい。例えば、IIIーV族化合物半導体であるGaN
の場合には、n型GaN層にはAl、In、Ti、P
b、Sb、Nb、Zr、Mn等を電極に用いることがよ
く、i型あるいはp型GaN層にはAu、Pt、Ge、
As、Ir、Re、Rh、Pd、Ni、W等を電極に用
いることで良好なオーミック接触が得られる。また、こ
のオーミック電極形成後に素子チップをリード部材に接
着する際に、接着性を向上させるためや、電極部の耐熱
性を向上するためにオーミック電極上にNi、Ti、A
u、W等の金属を積層することも好ましい。
The electrode forming method of the light emitting element chip in the present invention includes MBE method, vacuum evaporation method, electron beam evaporation method, sputtering method and the like. As the electrode material, a material that can obtain ohmic contact with each of the n-type semiconductor and the p-type or i-type semiconductor is preferable, and a single metal may be used, or a material obtained by mixing two or more kinds of metals and alloying them may be used. The condition for obtaining the ohmic contact is preferably a metal having a work function smaller than that of the semiconductor for the electrode on the n-type semiconductor side, and a work function larger than that of the semiconductor for the electrode on the p-type semiconductor side. It is preferable to use the metal which has. For example, GaN which is a III-V compound semiconductor
In this case, the n-type GaN layer has Al, In, Ti, P
It is preferable to use b, Sb, Nb, Zr, Mn, or the like for the electrode, and Au, Pt, Ge, or the like for the i-type or p-type GaN layer.
Good ohmic contact can be obtained by using As, Ir, Re, Rh, Pd, Ni, W or the like for the electrode. Further, when the element chip is adhered to the lead member after forming the ohmic electrode, Ni, Ti, A is formed on the ohmic electrode in order to improve the adhesiveness and to improve the heat resistance of the electrode portion.
It is also preferable to stack metals such as u and W.

【0011】電極形成後にAr、N2 、He等の不活性
ガス流中あるいは該半導体の構成元素を含むガス流中で
半導体の分解温度以下で熱処理することも好ましく、こ
れにより電極と半導体との界面抵抗を下げることが可能
になり、良好なダイオード特性を得ることができる。本
発明におけるリードフレームの形状は素子チップをリー
ド部材に固定しかつ電圧を印加するための接続部と、素
子チップのそれぞれの部位に電圧を印加するための各電
極と他のリード部材をワイヤ−によってそれぞれ接続で
きる構造であればよく発光素子チップの電極形状により
変えることができる。また、リードフレームは発光を有
効に集光するためにミラー面を設けることが望ましい。
発光素子チップの電極形状とリードフレーム形状の組合
せの例を図2(a)、(b)に示すがこれに限定される
ものではない。図2(a)はリ−ド部材16に切り欠き
部を有する例であり、素子チップ20の電極部18をリ
−ド部材16にダイボンディング法により接続し、その
後電極部19とリ−ド部材15とをワイヤ−により接続
する。図2(b)はリ−ド部材22に孔部を有する例で
あり、素子チップ20の電極部18をリ−ド部材22に
ダイボンディング法により接続し、その後電極部19と
リ−ド部材21とをワイヤ−により接続する。
After the electrode is formed, it is also preferable to perform heat treatment at a temperature not higher than the decomposition temperature of the semiconductor in a flow of an inert gas such as Ar, N 2 or He or in a flow of a gas containing the constituent elements of the semiconductor. The interface resistance can be lowered, and good diode characteristics can be obtained. The shape of the lead frame in the present invention is such that a connecting portion for fixing the element chip to the lead member and applying a voltage, each electrode for applying a voltage to each part of the element chip, and the other lead member are wired. Any structure can be used as long as they can be connected to each other by changing the shape of the electrodes of the light emitting element chip. Further, it is desirable that the lead frame be provided with a mirror surface in order to effectively collect the emitted light.
An example of the combination of the electrode shape of the light emitting element chip and the lead frame shape is shown in FIGS. 2A and 2B, but is not limited to this. FIG. 2A shows an example in which the lead member 16 has a notch, and the electrode portion 18 of the element chip 20 is connected to the lead member 16 by a die bonding method, and then the electrode portion 19 and the lead portion 19 are connected. The member 15 is connected by a wire. FIG. 2B shows an example in which the lead member 22 has a hole portion. The electrode portion 18 of the element chip 20 is connected to the lead member 22 by a die bonding method, and then the electrode portion 19 and the lead member are connected. 21 is connected by a wire.

【0012】本発明における発光素子チップとリード部
材にダイボンディングを行う際の接着の材料としては、
一般的に使われているものが使用できる。例えばAuー
Si、PbーSn合金系ハンダや、このハンダに少量の
Bi、Sb、Ag、Cd、Zn、In等の金属を添加し
たもの、BiにNa、Tl、Cd、Sn、Pb等を添加
し合金化したもの、InにZn、Cd、Sn、Bi等を
添加し合金化したもの、GaにAg、Zn、Sn、In
等を添加し合金化したもの、Au、Al、In、Ag等
の金属あるいは導電性成分としてAg、Au、Cu等を
含んだ導電性ペースト等がある。素子チップとリード部
材とを接着する方法としては、従来のダイボンディング
装置を用いて行う。即ち、ハンダあるいは金属等の接着
層を素子チップの該電極部、もしくはリード部材の素子
チップの接着面に蒸着法、塗布法あるいはメッキ法等に
より形成した後、該電極部と該リード部材を密着させな
がらリード部材を接着材料の融点以上に加熱して接着を
行う。
As a material for adhesion when die-bonding the light emitting device chip and the lead member in the present invention,
What is generally used can be used. For example, Au-Si, Pb-Sn alloy-based solder, a small amount of metal such as Bi, Sb, Ag, Cd, Zn, and In added to this solder, Bi, Na, Tl, Cd, Sn, Pb, etc. Alloyed by adding, alloyed by adding In, Zn, Cd, Sn, Bi, etc., Ga, Ag, Zn, Sn, In
And the like, a metal such as Au, Al, In, Ag, or a conductive paste containing Ag, Au, Cu, or the like as a conductive component. As a method of bonding the element chip and the lead member, a conventional die bonding device is used. That is, after forming an adhesive layer such as solder or metal on the electrode portion of the element chip or the adhesive surface of the element chip of the lead member by a vapor deposition method, a coating method, a plating method, or the like, the electrode portion and the lead member are brought into close contact with each other. While adhering, the lead member is heated to a temperature equal to or higher than the melting point of the adhesive material to adhere.

【0013】また本発明においては発光素子チップの電
極部とリード部材を配線する際にはワイヤーボンダー法
を用いることが特徴である。ダイボンディング法により
素子チップをリード部材に固定した後に、ワイヤーボン
ディング装置にセットして加熱および、あるいは超音波
を印加することにより電極部とリード部材とを接続す
る。このとき用いるワイヤーの材料としては、Au、A
g、Cu、Al、等の金属、Au−Si、Al−Si、
Al−Mg、Al−Si−Mg、Al−Ni等の合金が
あり、どの材料を使用するかは発光素子チップの電極部
の材料やワイヤーボンディングの作業性を考慮して選べ
ばよい。なかでも、AuやAl−Siが作業性がよいと
いうことで好ましい。ワイヤ−の太さは、発光素子チッ
プの電極部の大きさやワイヤーボンディングの作業性を
考慮して選べばよく、通常は20〜300μmφであ
る。また、ワイヤ−の酸化を防ぐために、不活性ガス中
でワイヤーボンディングを行うことも好ましい方法であ
る。
Further, the present invention is characterized in that a wire bonder method is used when wiring the electrode member of the light emitting element chip and the lead member. After the element chip is fixed to the lead member by the die bonding method, it is set in a wire bonding device and heated and / or ultrasonic waves are applied to connect the electrode portion and the lead member. The material of the wire used at this time is Au, A
g, Cu, Al, and other metals, Au-Si, Al-Si,
There are alloys such as Al-Mg, Al-Si-Mg, and Al-Ni. Which material to use may be selected in consideration of the material of the electrode portion of the light emitting element chip and the workability of wire bonding. Among them, Au and Al-Si are preferable because they have good workability. The thickness of the wire may be selected in consideration of the size of the electrode portion of the light emitting element chip and the workability of wire bonding, and is usually 20 to 300 μmφ. Further, it is also a preferable method to perform wire bonding in an inert gas in order to prevent oxidation of the wire.

【0014】その後、リード部材と素子チップを封止材
料でモールディングしてLEDを作製する。このモール
ディング工程は1段階で行ってもよいし、まず素子チッ
プをリード部材に固定してから集光レンズを形成しても
よいが特にこれらの方法に限定されるものでない。本発
明における封止材料としては発光素子チップの発光波長
範囲での光透過率が80%以上の透光性材料を使用する
ことが好ましい。この透光性材料としては、メタクリル
系樹脂、エポキシ系樹脂、ポリカーボネート系樹脂、ポ
リスチレン系樹脂、ポレオレフィン系樹脂および低融点
ガラスの少なくとも一種を使用することができる。封止
方法としては、たとえば所望形状の金型にこれらの透光
性材料の原料または加熱溶融体を注形して金型内で固化
させる方法を用いることができる。この固化の方法とし
て、モノマーやオリゴマーの熱または光による重合固
化、加熱溶融体では冷却固化、化学反応等を挙げること
ができる。この透光性材料には必要があれば、色調調整
や視感度補正のための色素、顔料、蛍光体などを、樹脂
の安定化のための酸化防止剤、安定剤、成形加工のため
の潤滑剤、滑剤を添加することも可能である。
After that, the lead member and the element chip are molded with a sealing material to produce an LED. This molding step may be performed in one step, or the element chip may be first fixed to the lead member and then the condenser lens may be formed, but the method is not particularly limited to these methods. As the sealing material in the present invention, it is preferable to use a translucent material having a light transmittance of 80% or more in the emission wavelength range of the light emitting element chip. As the translucent material, at least one of methacrylic resin, epoxy resin, polycarbonate resin, polystyrene resin, polyolefin resin, and low melting point glass can be used. As a sealing method, for example, a method of casting a raw material of these translucent materials or a heating melt into a mold of a desired shape and solidifying in the mold can be used. Examples of the solidification method include polymerization and solidification of monomers and oligomers by heat or light, cooling and solidification of a heated melt, and chemical reaction. If necessary, this translucent material should contain dyes, pigments, phosphors, etc. for color tone adjustment and visibility correction, antioxidants for stabilizing resins, stabilizers, and lubrication for molding. It is also possible to add agents and lubricants.

【0015】以上説明した各方法を用いて作製したLE
Dの例を図4に示すがこれに限定されるものではない。
素子チップ20は、絶縁基板上にn型半導体層、p型お
よびi型半導体層から選ばれた2種以上の組合せからな
る発光層を少なくとも一つ有し、かつ半導体の所定の部
位に、発光層に電圧を印加するための電極を有するプレ
−ナ構造の素子チップである。まず、リ−ド部材28の
接着面に蒸着法でハンダを蒸着した後、リ−ド部材28
の接着面に素子チップ20を載せハンダの融点以上に加
熱して接着する。その後、各電極とリ−ド部材とをワイ
ヤーボンディング法を用いてAu線により接続する。そ
の後、透明樹脂により封止してLED30を作製する。
LE manufactured by using each method described above
An example of D is shown in FIG. 4, but is not limited to this.
The element chip 20 has at least one light emitting layer composed of a combination of two or more selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer on an insulating substrate, and emits light at a predetermined portion of the semiconductor. It is an element chip having a planar structure having electrodes for applying a voltage to a layer. First, after solder is vapor-deposited on the adhesive surface of the lead member 28 by vapor deposition, the lead member 28 is
The element chip 20 is placed on the bonding surface of No. 1 and is heated to a temperature not lower than the melting point of the solder for bonding. Then, each electrode and lead member are connected by an Au wire using a wire bonding method. After that, the LED 30 is manufactured by sealing with a transparent resin.

【0016】以下、一例として透明絶縁性基板としてA
2 3 を使用してMBE法を用いてGaN薄膜を成膜
し、LEDを作製する方法について説明するが、とくに
これに限定されるものではない。装置としては、図1に
示すような真空容器1内に、蒸発用ルツボ(クヌードセ
ンセル)2、3および4、ガスセル7、基板加熱ホルダ
ー5を備えたガスソースMBE装置を使用した。
Hereinafter, as an example, a transparent insulating substrate A
A method for forming an LED by forming a GaN thin film using the MBE method using l 2 O 3 will be described, but the method is not particularly limited thereto. As the apparatus, a gas source MBE apparatus provided with an evaporation crucible (Knudsen cell) 2, 3 and 4, a gas cell 7 and a substrate heating holder 5 in a vacuum container 1 as shown in FIG. 1 was used.

【0017】蒸発用ルツボ2にはGa金属を入れ、基板
面において1013〜1019/cm2・secになる温度
に加熱した。アンモニアの導入にはガス導入管8を用
い、アンモニアをガスセル7内から基板6に直接吹き付
けるようにした。アンモニアの導入量は基板表面におい
て1016〜1020/cm2 ・secになるように供給し
た。蒸発用ルツボ3にはIn、Al等を入れ、所定の組
成の化合物半導体、および所定のキャリア密度を有する
半導体となるように温度および時間を制御して成膜を行
なう。蒸発用ルツボ4にはMg、Zn、Be、Sb、S
i、Ge、C、Sn、Hg、As、P等を入れ、所定の
供給量になるように温度および供給時間を制御すること
によりドーピングを行ない、n型およびi型あるいはp
型半導体層を成膜する。
Ga metal was placed in the evaporation crucible 2 and heated to a temperature of 10 13 to 10 19 / cm 2 · sec on the substrate surface. A gas introduction pipe 8 was used to introduce ammonia, and ammonia was blown directly from the gas cell 7 onto the substrate 6. Ammonia was supplied so that the amount of ammonia introduced was 10 16 to 10 20 / cm 2 · sec on the substrate surface. In, Al, etc. are put in the evaporation crucible 3 and a film is formed by controlling temperature and time so that a compound semiconductor having a predetermined composition and a semiconductor having a predetermined carrier density are obtained. The evaporation crucible 4 has Mg, Zn, Be, Sb, S
i, Ge, C, Sn, Hg, As, P, etc. are added, and doping is performed by controlling the temperature and the supply time so as to obtain a predetermined supply amount.
A type semiconductor layer is formed.

【0018】基板6にはサファイアR面を使用し、20
0〜900℃に加熱した。サファイアR面基板は、オフ
角が0.8度以下のものが好ましい。まず、基板6を真
空容器1内で750℃で加熱した後、各ルツボを所定の
成長温度に設定し、まず蒸発用ルツボ3を開き、0.1
〜30オングストローム/secの成長速度で0.05
〜2μmの厚みのn型GaN薄膜を作製する。さらにそ
の後、Znをチャージした蒸発用ルツボ4のシャッター
を開き、0.1〜30オングストローム/secの成長
速度で0.01〜1μmの厚みでi型あるいはp型Ga
N薄膜を成膜して発光層を形成する。この成膜時には常
にガスセルを加熱し基板表面にアンモニアを供給する。
A sapphire R surface is used for the substrate 6, and 20
Heated to 0-900 ° C. The off-angle of the sapphire R-plane substrate is preferably 0.8 degrees or less. First, after heating the substrate 6 in the vacuum container 1 at 750 ° C., each crucible is set to a predetermined growth temperature, and the evaporation crucible 3 is first opened to
0.05 at a growth rate of ~ 30 Å / sec
An n-type GaN thin film having a thickness of ˜2 μm is prepared. After that, the shutter of the evaporation crucible 4 charged with Zn is opened, and the i-type or p-type Ga is grown at a growth rate of 0.1 to 30 Å / sec and a thickness of 0.01 to 1 μm.
An N thin film is formed to form a light emitting layer. During this film formation, the gas cell is always heated to supply ammonia to the surface of the substrate.

【0019】以上のような方法で成膜した発光層を有す
るGaN薄膜を用いてLEDを作製する工程を図3
(a)から図3(h)にしたがって説明する。GaN薄
膜表面にレジストを塗布する。レジストの膜厚はエッチ
ングしたいGaN薄膜の厚みによって変えればよく0.
1〜3μmとするのが好ましい。スピンコーターの条件
は2500rpm、30secである。塗布後に90℃
に加熱されたクリーンオーブン内で30分間プレベーク
する(a)。 その後、素子パターン形成用マスクを用
いてUV露光・現像を行った(b)。Arをガスとして
用いてイオンミリング法によりi層あるいはp層のGa
N薄膜19を除去する(c)。イオンミリング終了後、
アセトンを用いてレジストを除去する。 なお、各工程
でのイオンミリングを行う時間はエッチングを行う膜厚
によって決めることができる。
FIG. 3 shows a process of manufacturing an LED using a GaN thin film having a light emitting layer formed by the above method.
It will be described with reference to FIGS. A resist is applied on the surface of the GaN thin film. The thickness of the resist may be changed depending on the thickness of the GaN thin film to be etched.
It is preferably 1 to 3 μm. The spin coater conditions are 2500 rpm and 30 sec. 90 ° C after coating
Prebak in a clean oven heated to 30 minutes (a). Then, UV exposure and development were performed using the element pattern forming mask (b). Ga of i-layer or p-layer is formed by ion milling using Ar as gas.
The N thin film 19 is removed (c). After the end of ion milling,
The resist is removed using acetone. The time for performing ion milling in each step can be determined by the film thickness for etching.

【0020】以上の工程の後、管状炉内に試料をセット
してアンモニアを雰囲気として500℃で30分間熱処
理した。熱処理後、再度レジストを塗布し、プレベーク
を行い、続いてn層電極形成用マスクを用いてUV露光
・現像を行った後(d)、真空蒸着法によりn型GaN
層18の電極としてAlを3000オングストロームの
厚さに蒸着し、リフトオフにより電極パターン25を形
成した(g)。ついで再度レジストを塗布し、プレベー
クを行い、i層電極形成用マスクを用いてUV露光・現
像を行った後(f)、真空蒸着法によりp型あるいはi
型GaN層19の電極としてAuを3000オングスト
ロームの厚さに蒸着し、リフトオフにより電極パターン
26を形成した(g)。その後、Ar流中で300℃、
1時間の加熱処理を行った。
After the above steps, the sample was set in a tubular furnace and heat-treated at 500 ° C. for 30 minutes in an atmosphere of ammonia. After the heat treatment, a resist is applied again, prebaking is performed, UV exposure and development are subsequently performed using a mask for forming an n-layer electrode (d), and then n-type GaN is formed by a vacuum deposition method.
As an electrode of the layer 18, Al was vapor-deposited to a thickness of 3000 angstrom, and an electrode pattern 25 was formed by lift-off (g). Then, the resist is applied again, pre-baked, subjected to UV exposure and development using the mask for forming the i-layer electrode (f), and then p-type or i-type by the vacuum deposition method.
Au was vapor-deposited to a thickness of 3000 angstrom as an electrode of the type GaN layer 19, and the electrode pattern 26 was formed by lift-off (g). After that, 300 ° C in Ar flow,
Heat treatment was performed for 1 hour.

【0021】以上のようにして作製した発光素子チップ
のn型GaN側の電極をハンダによりリード部材28に
接着し、i型GaN側の電極はワイヤーボンダー装置を
用いて30μmφAu線17でもう1方のリード部材2
7にボンディングした。その後、発光素子チップを透明
エポキシ樹脂29により封止した(h)。エポキシ硬化
後、リード部材を折り曲げ、再度透明エポキシ樹脂によ
りモールディングを施し、図4に示すような5mmφL
ED30を作製した。
The n-type GaN-side electrode of the light-emitting element chip manufactured as described above is bonded to the lead member 28 by soldering, and the i-type GaN-side electrode is the other side of 30 μmφAu wire 17 using a wire bonder device. Lead member 2
Bonded to 7. Then, the light emitting element chip was sealed with a transparent epoxy resin 29 (h). After curing the epoxy, bend the lead member and mold it again with transparent epoxy resin.
ED30 was produced.

【0022】[0022]

【実施例】以下,実施例によりさらに詳細に説明する。EXAMPLES The present invention will be described in more detail below with reference to examples.

【0023】[0023]

【実施例1】透明絶縁性基板としてAl2 3 R面を使
用し、MBE法によりGaN薄膜を成膜し、LEDを作
製した例について説明する。図1に示すような真空容器
1内に、蒸発用ルツボ2、3、4、ガスセル7、および
基板加熱ホルダー5、さらにガスセル7にガスを供給す
るためのガス導入管8を備えたMBE装置を用いた。
Example 1 An example in which an Al 2 O 3 R surface is used as a transparent insulating substrate and a GaN thin film is formed by the MBE method to fabricate an LED will be described. An MBE apparatus provided with an evaporation crucible 2, 3, 4, a gas cell 7, a substrate heating holder 5, and a gas introduction pipe 8 for supplying a gas to the gas cell 7 in a vacuum container 1 as shown in FIG. Using.

【0024】蒸発用ルツボ2にはGa金属を入れ、10
50℃に加熱した。ガスとしてはアンモニアを使用し、
ガス導入管8を通してガスセル7に5cc/minの速
度で供給した。アンモニアガスは基板6に直接供給する
ような構造とした。基板6としては、オフ角が0.5度
のサファイアR面を使用する。真空容器内の圧力は、成
膜時において2×10-6Torrであった。
Ga metal was put in the evaporation crucible 2 and
Heated to 50 ° C. Ammonia is used as gas,
It was supplied to the gas cell 7 through the gas introduction pipe 8 at a rate of 5 cc / min. Ammonia gas was directly supplied to the substrate 6. As the substrate 6, a sapphire R surface having an off angle of 0.5 degree is used. The pressure in the vacuum container was 2 × 10 −6 Torr during film formation.

【0025】まず、基板6を900℃で30分間加熱
し、ついで750℃の温度に保持し成膜を行う。成膜は
アンモニアを300℃に加熱したガスセル7から供給し
ながらGaのルツボのシャッターを開けて行い、1.5
オングストローム/secの成膜速度で膜厚0.5μm
のn型GaN薄膜を作製した。さらにMgをチャージし
て300℃に保たれた蒸発用ルツボ4のシャッターを開
けMgドープのGaN薄膜を1.5オングストローム/
secの成膜速度で膜厚0.05μmの厚さで成膜して
発光層を形成した。この作製した薄膜のRHEEDパタ
ーンはストリーク状で結晶性および平坦性がよく、抵抗
を測定したところ、10MΩ以上の抵抗があり絶縁状態
であった。
First, the substrate 6 is heated at 900 ° C. for 30 minutes, and then the temperature is maintained at 750 ° C. to form a film. The film formation was performed by opening the shutter of the Ga crucible while supplying ammonia from the gas cell 7 heated to 300 ° C.
0.5 μm film thickness at film forming rate of Angstrom / sec
Of n-type GaN thin film was prepared. Furthermore, the shutter of the evaporation crucible 4 which was charged with Mg and kept at 300 ° C. was opened, and the Mg-doped GaN thin film was 1.5 angstrom /
A light emitting layer was formed by forming a film with a thickness of 0.05 μm at a film forming rate of sec. The RHEED pattern of the produced thin film was streaky and had good crystallinity and flatness. When the resistance was measured, there was a resistance of 10 MΩ or more and it was in an insulating state.

【0026】発光層上にスピンコーターを用いて250
0rpm、30secの条件でレジストを塗布し、90
℃のクリーンオーブン中で30分間プレベークした。ベ
ーク後、素子パターン形成用のマスクを用いてUV露光
し、現像した。次いで、加速電圧500V、圧力2×1
ー4Torrの条件のArで15分間イオンミリングを
行い素子パターン形成を行った。その後、アセトンを用
いてレジストを除去した。次に、再度スピンコーターを
用いて2500rpm、30secの条件でレジストを
塗布し、90℃のクリーンオーブン中で30分間プレベ
ークした。ベーク後、i層除去用のマスクを用いてUV
露光し、現像した。続いて、加速電圧500V、圧力2
×10ー4Torrの条件のAr雰囲気中で1分間イオン
ミリングを行い不必要なi層を除去した。その後、アセ
トンでレジストを除去した。続いて、管状炉にセットし
て10cc/minのアンモニアガス流中で500℃、
30分間の熱処理を行った。さらに、スピンコーターを
用いて2500rpm、30secの条件でレジストを
塗布し、90℃のクリーンオーブン中で30分間プレベ
ークした。ベーク後、n型GaN層の電極形成用のマス
クを用いてUV露光し、現像した。つぎに、真空蒸着機
に装着し2×10ー6Torrの真空中でAl金属を0.
2μmの厚さで真空蒸着した。その後、アセトンでリフ
トオフして電極パターンを形成した。ついで、i型Ga
N層の電極形成用のマスクを用いてUV露光し、現像し
た。続いて、真空蒸着機に装着し2×10ー6Torrの
真空中でAu金属を0.2μmの厚さで真空蒸着した。
その後、アセトンでリフトオフして電極パターンを形成
し、Ar流中で300℃で1時間加熱処理を行い、素子
チップの構造を完成させた。作製した素子チップの側面
図および上面図を図5(a)、(b)に示す。
250 using a spin coater on the light emitting layer
Apply resist under the conditions of 0 rpm and 30 sec, and
Prebaked in clean oven at 30 ° C. for 30 minutes. After baking, UV exposure was performed using a mask for element pattern formation, and development was performed. Next, acceleration voltage 500V, pressure 2 × 1
0 over 4 Torr conditions the element pattern formation is performed for 15 minutes ion milling in Ar were carried out. Then, the resist was removed using acetone. Next, the resist was applied again using a spin coater under the conditions of 2500 rpm and 30 sec, and prebaked in a clean oven at 90 ° C. for 30 minutes. After baking, UV is applied using a mask for removing the i layer.
Exposed and developed. Then, acceleration voltage 500V, pressure 2
Ion milling was carried out for 1 minute in an Ar atmosphere under the condition of × 10 -4 Torr to remove the unnecessary i layer. Then, the resist was removed with acetone. Then, set in a tubular furnace and 500 ° C. in an ammonia gas flow of 10 cc / min,
Heat treatment was performed for 30 minutes. Further, a resist was applied using a spin coater under the conditions of 2500 rpm and 30 sec, and prebaked in a clean oven at 90 ° C. for 30 minutes. After baking, it was exposed to UV using a mask for forming an electrode of the n-type GaN layer and developed. Next, 0 Al metal in a vacuum of 2 × 10 over 6 Torr mounted in a vacuum deposition machine.
It was vacuum-deposited to a thickness of 2 μm. Then, liftoff was performed with acetone to form an electrode pattern. Then, i-type Ga
UV exposure was performed and development was performed using a mask for forming an N layer electrode. Subsequently, it was mounted on a vacuum vapor deposition machine and Au metal was vacuum vapor deposited to a thickness of 0.2 μm in a vacuum of 2 × 10 −6 Torr.
After that, liftoff was performed with acetone to form an electrode pattern, and heat treatment was carried out at 300 ° C. for 1 hour in an Ar flow to complete the structure of the element chip. A side view and a top view of the manufactured element chip are shown in FIGS. 5 (a) and 5 (b).

【0027】各チップのカッティングはダイシングソー
を用いて行った。1素子チップは0.5mm×0.5m
mとした。このうちの1チップを取り出しn型GaN層
電極をAgペーストによりリード部材にダイボンディン
グした。さらにi型GaN層電極とリード部材とをワイ
ヤーボンディング装置を用いて30μmφAu線で接続
した。この接続後の断面図を図6に示す。上記の方法で
作製した発光素子を透明エポキシ樹脂で封止して、エポ
キシ硬化後、リード部材を折り曲げ、再度透明エポキシ
樹脂で封止して図7に示すようなLEDを作製した。
The cutting of each chip was performed using a dicing saw. One element chip is 0.5 mm x 0.5 m
m. One of the chips was taken out and the n-type GaN layer electrode was die-bonded to the lead member with Ag paste. Further, the i-type GaN layer electrode and the lead member were connected with a 30 μmφAu wire using a wire bonding device. A cross-sectional view after this connection is shown in FIG. The light emitting device manufactured by the above method was sealed with a transparent epoxy resin, the epoxy resin was cured, the lead member was bent, and the transparent epoxy resin was sealed again to manufacture an LED as shown in FIG. 7.

【0028】同様の方法で100個のLEDを作製した
ところ、96個のLEDで発光が確認された。このLE
Dの発光強度を測定したところ10V,20mAで50
mcdであり、青色の発光が観測された。
When 100 LEDs were manufactured by the same method, light emission was confirmed with 96 LEDs. This LE
When the emission intensity of D was measured, it was 50 V at 10 V and 20 mA.
mcd, and blue light emission was observed.

【0029】[0029]

【比較例1】実施例1と同様の方法によりAl2 3
板上に成膜した発光層を有するGaN薄膜を用いて素子
化を行った。素子作製過程も実施例1と同様の方法によ
り行い、n型GaN層、i型GaN層の両電極ともAg
ペーストにより、リード部材にダイボンディングを行っ
た後、透明エポキシ樹脂で封止してLEDを作製した。
同様の方法で100個のLEDを作製したところ、Ag
ペーストにより正負の電極がつながってしまい、28個
のLEDでしか発光するものは得られなかった。
COMPARATIVE EXAMPLE 1 A device was formed by using a GaN thin film having a light emitting layer formed on an Al 2 O 3 substrate by the same method as in Example 1. The device manufacturing process was also performed in the same manner as in Example 1, and both electrodes of the n-type GaN layer and the i-type GaN layer were Ag.
The lead member was die-bonded with a paste and then sealed with a transparent epoxy resin to produce an LED.
When 100 LEDs were made by the same method, Ag
The positive and negative electrodes were connected by the paste, and only 28 LEDs were able to emit light.

【0030】[0030]

【実施例2】透明絶縁性基板としてAl2 3 R面を使
用し、MBE法によりGa1ーx In x N薄膜を成膜し2
色発光のLEDを作製した例について説明する。図2に
示すような真空容器1内に、蒸発用ルツボ2、3、4、
ガスセル7、および基板加熱ホルダー5、さらにガスセ
ル7にガスを供給するためのガス導入管8を備えたMB
E装置を用いた。
Example 2 Al as a transparent insulating substrate2O3Use R side
Used by the MBE method1-xIn xForm N thin film 2
An example of producing a color-emitting LED will be described. In Figure 2
In the vacuum container 1 as shown, the evaporation crucibles 2, 3, 4,
Gas cell 7, substrate heating holder 5, and gas
MB equipped with a gas introduction pipe 8 for supplying gas to
Equipment E was used.

【0031】蒸発用ルツボ2にはGa金属を入れ、10
20℃に加熱し、蒸着用ルツボ3にはIn金属を入れ1
000℃に加熱した。ガスとしてはアンモニアを使用
し、ガス導入管8を通してガスセル7に5cc/min
の速度で供給した。アンモニアガスは基板6に直接供給
するような構造とした。基板6としては、オフ角が0.
5度のサファイアR面を使用する。
Ga metal is put in the evaporation crucible 2 and 10
Heat to 20 ° C and put In metal into the evaporation crucible 3 1
Heated to 000 ° C. Ammonia is used as the gas, and 5 cc / min is supplied to the gas cell 7 through the gas introduction pipe 8.
Was fed at the rate of. Ammonia gas was directly supplied to the substrate 6. The substrate 6 has an off angle of 0.
Use a 5 degree sapphire R surface.

【0032】真空容器内の圧力は、成膜時において2×
10-6Torrであった。まず、基板6を900℃で3
0分間加熱し、ついで750℃の温度に保持し成膜を行
う。成膜はアンモニアを300℃に加熱したガスセル7
から供給しながらGaのルツボのシャッターを開けて行
い、1.5オングストローム/secの成膜速度で膜厚
0.5μm のn型GaN薄膜を作製した。さらにMgを
チャージして300℃に保たれた蒸発用ルツボ4のシャ
ッターを開けMgをドーピングしたi型GaN薄膜を
1.5オングストローム/secの成膜速度で膜厚0.
05μmの厚さで成膜して第1の発光層を形成した。次
に基板温度を700℃に下げて30分間温度を安定させ
た後、GaとInのルツボのシャッターを開けて1.5
オングストローム/secの成長速度で膜厚0.5μm
のn型Ga0.8 In0.2N薄膜を成長し、さらにその上
に蒸着ルツボ2,3および4のシャッターを開けてMg
をドーピングしたi型Ga0.8 In0.2 N薄膜を1.5
オングストローム/secの成長速度で膜厚0.05μ
mの厚さで成膜して第2の発光層を形成した。 成膜し
た薄膜上にスピンコーターを用いて2500rpm、3
0secの条件でレジストを塗布し、90℃のクリーン
オーブン中で30分間プレベークした。ベーク後、素子
パターン形成用のマスクを用いてUV露光し、現像し
た。続いて、加速電圧500V、圧力2×10ー4Tor
rの条件のArで25分間イオンミリングを行い素子パ
ターン形成を行った。その後、アセトンを用いてレジス
トを除去した。次に、再度スピンコーターを用いて25
00rpm、30secの条件でレジストを塗布し、9
0℃のクリーンオーブン中で30分間プレベークした。
ベーク後、フォトマスクを用いてUV露光し、現像し
た。つぎに、加速電圧500V、圧力2×10ー4Tor
rの条件のAr雰囲気中で15分間イオンミリングを行
い不必要なi型Ga0.8 In0.2 N層、n型Ga0.8
0.2 N層、i型GaN層を除去した。次に、再度スピ
ンコーターを用いて2500rpm、30secの条件
でレジストを塗布し、90℃のクリーンオーブン中で3
0分間プレベークした。ベーク後、フォトマスクを用い
てUV露光し、現像した。ついで、加速電圧500V、
圧力2×10ー4Torrの条件のAr雰囲気中で13分
間イオンミリングを行い不必要なi型Ga0.8 In0.2
N層、n型Ga0.8 In 0.2 N層を除去した。さらに再
度スピンコーターを用いて2500rpm、30sec
の条件でレジストを塗布し、90℃のクリーンオーブン
中で30分間プレベークした。ベーク後、フォトマスク
を用いてUV露光し、現像した。続いて、イオンミリン
グを用い不必要なi型Ga0.8 In0.2 N層を除去し
た。その後、アセトンでレジストを除去した。この素子
チップを管状炉にセットして10cc/minのアンモ
ニアガス流中で500℃、30分間の熱処理を行った。
さらに、スピンコーターを用いて2500rpm、30
secの条件でレジストを塗布し、90℃のクリーンオ
ーブン中で30分間プレベークした。ベーク後、n型G
aN層およびn型Ga0.8 In0.2 N層の電極形成用の
マスクを用いてUV露光し、現像した。次に、真空蒸着
機に装着し2×10ー6Torrの真空中でAl金属を
0.2μmの厚さで真空蒸着した。その後、アセトンで
リフトオフして電極パターンを形成した。ついで、i型
GaN層およびi型Ga0.8 In0.2 N層の電極形成用
のマスクを用いてUV露光し、現像した。続いて、真空
蒸着機に装着し2×10ー6Torrの真空中でAu金属
を0.2μmの厚さで真空蒸着した。その後、アセトン
でリフトオフして電極パターンを形成し、Ar流中で3
00℃で1時間加熱処理を行い、素子チップの構造を完
成させた。作製した素子チップの側面図および上面図を
図8(a)、(b)に示す。
The pressure in the vacuum container is 2 × during film formation.
10-6It was Torr. First, the substrate 6 is heated at 900 ° C. for 3
After heating for 0 minutes, the temperature is kept at 750 ° C to form a film.
U The film is formed by a gas cell 7 in which ammonia is heated to 300 ° C.
Opening the shutter of the Ga crucible while supplying from
The film thickness is 1.5 angstrom / sec.
An n-type GaN thin film of 0.5 μm was prepared. Further Mg
The evaporation crucible 4 that was charged and kept at 300 ° C
And open the Mg-doped i-type GaN thin film.
The film thickness is 0.1 at a film forming rate of 1.5 angstrom / sec.
A film having a thickness of 05 μm was formed to form a first light emitting layer. Next
Then, lower the substrate temperature to 700 ℃ and stabilize the temperature for 30 minutes.
After opening, open the shutter of the crucible of Ga and In, and 1.5
0.5 μm film thickness at a growth rate of Angstrom / sec
N-type Ga0.8In0.2N thin film is grown and further on
Open the vapor deposition crucibles 2, 3 and 4 shutters and
I-type Ga doped with0.8In0.2N thin film 1.5
Film thickness 0.05μ at growth rate of Angstrom / sec
A film having a thickness of m was formed to form a second light emitting layer. Film formation
2500 rpm for 3 minutes using a spin coater
Apply the resist under the condition of 0 sec and clean at 90 ℃
Prebaked in oven for 30 minutes. Element after baking
UV exposure and development using a mask for pattern formation
It was Then, acceleration voltage 500V, pressure 2 × 10-4Tor
Perform ion milling for 25 minutes with Ar under the condition of r
A turn was formed. Then, use acetone to register
Removed. Then, again using the spin coater 25
Apply the resist under the conditions of 00 rpm and 30 sec.
Prebaked in a 0 ° C. clean oven for 30 minutes.
After baking, UV exposure using a photomask and development
It was Next, acceleration voltage 500V, pressure 2 × 10-4Tor
Ion milling for 15 minutes in Ar atmosphere under r condition
Unnecessary unnecessary i-type Ga0.8In0.2N layer, n-type Ga0.8I
n0.2The N layer and the i-type GaN layer were removed. Then spin again
Condition of 2500 rpm, 30 sec using a coater
Apply the resist with and clean in a clean oven at 90 ° C for 3
Prebaked for 0 minutes. After baking, use a photomask
UV exposed and developed. Then, acceleration voltage 500V,
Pressure 2 × 10-413 minutes in Ar atmosphere under Torr conditions
Unnecessary i-type Ga by ion milling0.8In0.2
N layer, n-type Ga0.8In 0.2The N layer was removed. Further again
Degree spin coater 2500rpm, 30sec
Apply the resist under the conditions of 90 ° C clean oven
Prebaked for 30 minutes in. Photo mask after baking
Was exposed to UV and developed. Next, Ion Mirin
Unnecessary i-type Ga0.8In0.2Remove the N layer
It was Then, the resist was removed with acetone. This element
Set the tip in the tubular furnace and set the
Heat treatment was performed at 500 ° C. for 30 minutes in a near gas flow.
Furthermore, using a spin coater, 2500 rpm, 30
Apply the resist under the condition of sec and clean at 90 ° C.
Prebaked in oven for 30 minutes. N type G after baking
aN layer and n-type Ga0.8In0.2For forming N layer electrode
UV exposure was performed using a mask and development was performed. Next, vacuum deposition
2x10 attached to the machine-6Al metal in a vacuum of Torr
It was vacuum-deposited to a thickness of 0.2 μm. Then with acetone
The electrode pattern was formed by lifting off. Then, i type
GaN layer and i-type Ga0.8In0.2For forming N layer electrode
UV exposure was carried out using the above mask and developed. Then, the vacuum
Mounted on a vapor deposition machine, 2 x 10-6Au metal in vacuum at Torr
Was vacuum-deposited to a thickness of 0.2 μm. Then acetone
Lift off with to form an electrode pattern, and
Complete the element chip structure by heat treatment at 00 ° C for 1 hour.
I made it. A side view and a top view of the manufactured element chip
8 (a) and 8 (b).

【0033】各チップのカッティングはダイシングソー
を用いて行った。1素子チップは1mm×1mmとし
た。このうちの1チップを取り出しn型GaN層および
n型Ga0.8 In0.2 N層の電極をAgペーストにより
リード部材にダイボンディングした。さらにi型GaN
層電極とリード部材、i型Ga0.8 In0.2 N層電極と
リード部材とをワイヤーボンディング装置を用いて30
μmφAu線で接続した。この接続後の上面図を図9に
示す。上記の方法で作製した発光素子を透明エポキシ樹
脂で封止して、エポキシ硬化後、リード部材を折り曲
げ、再度透明エポキシ樹脂で封止して図10に示すよう
なLEDを作製した。
The cutting of each chip was performed using a dicing saw. One element chip was 1 mm × 1 mm. One of the chips was taken out and the electrodes of the n-type GaN layer and the n-type Ga 0.8 In 0.2 N layer were die-bonded to the lead member with Ag paste. Furthermore, i-type GaN
The layer electrode and the lead member, and the i-type Ga 0.8 In 0.2 N layer electrode and the lead member were bonded using a wire bonding device.
The connection was made with a μmφAu wire. A top view after this connection is shown in FIG. The light emitting device manufactured by the above method was sealed with a transparent epoxy resin, the epoxy was cured, and then the lead member was bent and sealed with the transparent epoxy resin again to manufacture an LED as shown in FIG.

【0034】同様の方法で100個のLEDを作製した
ところ、89個のLEDで発光が確認された。このLE
Dの発光強度を測定したところリード部材66とリード
部材67では10V,18mAで40mcdの青色の発
光が、リード部材66とリード部材68では、8V、2
0mAで60mcdの緑色の発光が観測された。
When 100 LEDs were manufactured by the same method, light emission was confirmed with 89 LEDs. This LE
When the emission intensity of D was measured, the lead member 66 and the lead member 67 emitted blue light of 10 V and 40 mcd at 18 mA, and the lead member 66 and the lead member 68 emitted 8 V, 2
A green emission of 60 mcd was observed at 0 mA.

【0035】[0035]

【発明の効果】本発明は透明絶縁性基板上に発光層を形
成したプレーナ型の素子チップ構造において、同一平面
上に形成された電極の一つをリード部材にダイボンディ
ング法により直接接続し、他の少なくとも一つの電極を
他のリード部材にワイヤーボンディング法によりワイヤ
−で接続することで、安定した高性能のLEDを供給す
ることが可能になる。
According to the present invention, in a planar type device chip structure in which a light emitting layer is formed on a transparent insulating substrate, one of the electrodes formed on the same plane is directly connected to a lead member by a die bonding method, By connecting at least one other electrode to another lead member with a wire by a wire bonding method, it becomes possible to supply a stable and high-performance LED.

【図面の簡単な説明】[Brief description of drawings]

【図1】 薄膜作製に用いたMBE装置の概略図であ
る。
FIG. 1 is a schematic diagram of an MBE apparatus used for thin film production.

【図2】(a)(b) 本発明による方法で作製したL
EDの上面図ならびに断面図である。
2 (a) (b) L prepared by the method according to the present invention
It is a top view and sectional drawing of ED.

【図3】(a)〜(h) LEDの作製工程を示した断
面図である。
3A to 3H are cross-sectional views showing a manufacturing process of an LED.

【図4】 本発明による方法で作製したLEDの断面図
である。
FIG. 4 is a cross-sectional view of an LED manufactured by the method according to the present invention.

【図5】 (a)実施例1で作製した素子チップの上面
図である。 (b)実施例1で作製した素子チップの断面図である。
5 (a) is a top view of the element chip manufactured in Example 1. FIG. (B) It is sectional drawing of the element chip produced in Example 1.

【図6】 実施例1での素子チップをリード部材に実装
したときの断面図である。
FIG. 6 is a cross-sectional view when the element chip of Example 1 is mounted on a lead member.

【図7】 実施例1で作製したLEDの断面図である。FIG. 7 is a cross-sectional view of the LED manufactured in Example 1.

【図8】 (a)実施例2で作製した素子チップの上面
図である。 (b)実施例2で作製した素子チップの断面図である。
8 (a) is a top view of the element chip manufactured in Example 2. FIG. (B) It is sectional drawing of the element chip produced in Example 2.

【図9】 実施例2での素子チップをリード部材に実装
したときの上面図である。
FIG. 9 is a top view of the element chip of Example 2 mounted on a lead member.

【図10】 実施例2で作製したLEDの断面図であ
る。
FIG. 10 is a cross-sectional view of the LED manufactured in Example 2.

【図11】 従来の方法で作製されたLEDの断面図で
ある。
FIG. 11 is a cross-sectional view of an LED manufactured by a conventional method.

【図12】 従来の方法で作製されたフリップチップ方
式のLEDの断面図である。
FIG. 12 is a cross-sectional view of a flip-chip type LED manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

1 真空容器 2 蒸発用ルツボ 3 蒸発用ルツボ 4 蒸発用ルツボ 5 基板加熱ホルダー 6 基板 7 ガスセル 8 ガス導入管 9 流量調節バルブ 10 クライオパネル 11 コールドトラップ 12 油拡散ポンプ 13 油回転ポンプ 14 ミラー部 15 リード部材(1) 16 リード部材(2) 17 金属ワイヤー 18 n型半導体層 19 p型あるいはi型半導体層 20 素子チップ 21 リード部材(3) 22 リード部材(4) 23 レジスト 24 透明絶縁性基板 25 n型半導体層電極 26 p型あるいはi型半導体層電極 27 リード部材(5) 28 リード部材(6) 29 透明樹脂 30 LED 31 n型GaN半導体層電極 32 i型GaN半導体層電極 33 i型GaN半導体層 34 n型GaN半導体層 35 サファイア基板 36 Auワイヤー 37 リード部材(7) 38 リード部材(8) 39 GaN発光素子チップ 40 GaNMIS型LED 41 n型Ga0.8 In0.2 N半導体層 42 i型Ga0.8 In0.2 N半導体層 43 i型Ga0.8 In0.2 N半導体層電極 44 n型GaN半導体層およびn型Ga0.8 In0.2
N半導体層電極 45 リード部材(9) 46 リード部材(10) 47 リード部材(11) 48 GaN、Ga0.8 In0.2 N発光素子チップ 49 2色発光のLED 50 リード部材(12) 51 リード部材(13) 52 リードフレーム 53 リード部材(14) 54 リード部材(15)
DESCRIPTION OF SYMBOLS 1 Vacuum container 2 Evaporating crucible 3 Evaporating crucible 4 Evaporating crucible 5 Substrate heating holder 6 Substrate 7 Gas cell 8 Gas introduction pipe 9 Gas flow control valve 10 Cryopanel 11 Cold trap 12 Oil diffusion pump 13 Oil rotary pump 14 Mirror part 15 Lead Member (1) 16 Lead member (2) 17 Metal wire 18 n-type semiconductor layer 19 p-type or i-type semiconductor layer 20 Element chip 21 Lead member (3) 22 Lead member (4) 23 Resist 24 Transparent insulating substrate 25 n Type semiconductor layer electrode 26 p-type or i-type semiconductor layer electrode 27 lead member (5) 28 lead member (6) 29 transparent resin 30 LED 31 n-type GaN semiconductor layer electrode 32 i-type GaN semiconductor layer electrode 33 i-type GaN semiconductor layer 34 n-type GaN semiconductor layer 35 sapphire substrate 36 Au wafer Yer 37 lead members (7) 38 lead member (8) 39 GaN light-emitting element chips 40 GaNMIS type LED 41 n-type Ga 0.8 In 0.2 N semiconductor layer 42 i-type Ga 0.8 In 0.2 N semiconductor layer 43 i-type Ga 0.8 In 0.2 N Semiconductor layer electrode 44 n-type GaN semiconductor layer and n-type Ga 0.8 In 0.2
N semiconductor layer electrode 45 lead member (9) 46 lead member (10) 47 lead member (11) 48 GaN, Ga 0.8 In 0.2 N light emitting element chip 49 two-color LED 50 lead member (12) 51 lead member (13) ) 52 lead frame 53 lead member (14) 54 lead member (15)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 透明絶縁性基板上にn型半導体層、p型
およびi型半導体層から選ばれた2種以上の組合せから
なる発光層を少なくとも一つ有し、かつ半導体層の所定
の部位に発光層に電圧を印加するための電極を有するプ
レーナ構造の素子チップにおいて、一つの電極がリード
部材と直接に接続され、かつ他の少なくとも一つの電極
が他のリ−ド部材とワイヤ−により接続されていること
を特徴とする発光ダイオード。
1. A transparent insulating substrate having at least one light-emitting layer composed of a combination of two or more selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer, and a predetermined portion of the semiconductor layer. In an element chip having a planar structure having an electrode for applying a voltage to the light emitting layer, one electrode is directly connected to the lead member, and at least another electrode is connected to another lead member and a wire. A light emitting diode characterized by being connected.
【請求項2】 素子チップの一つの電極がリ−ド部材に
直接に接続し、他の電極は該リ−ド部材の切り欠き部ま
たは孔部を通してワイヤ−で他のリ−ド部材と接続され
ていることを特徴とする請求項1記載の発光ダイオ−
ド。
2. One electrode of the element chip is directly connected to the lead member, and the other electrode is connected to the other lead member by a wire through a notch or a hole of the lead member. The light emitting diode according to claim 1, characterized in that
De.
JP22411092A 1992-08-24 1992-08-24 Light emitting diode Withdrawn JPH0677537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22411092A JPH0677537A (en) 1992-08-24 1992-08-24 Light emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22411092A JPH0677537A (en) 1992-08-24 1992-08-24 Light emitting diode

Publications (1)

Publication Number Publication Date
JPH0677537A true JPH0677537A (en) 1994-03-18

Family

ID=16808695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22411092A Withdrawn JPH0677537A (en) 1992-08-24 1992-08-24 Light emitting diode

Country Status (1)

Country Link
JP (1) JPH0677537A (en)

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US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
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