JPH0669546A - Light-emitting diode - Google Patents

Light-emitting diode

Info

Publication number
JPH0669546A
JPH0669546A JP22262792A JP22262792A JPH0669546A JP H0669546 A JPH0669546 A JP H0669546A JP 22262792 A JP22262792 A JP 22262792A JP 22262792 A JP22262792 A JP 22262792A JP H0669546 A JPH0669546 A JP H0669546A
Authority
JP
Japan
Prior art keywords
electrode
layer
light emitting
type
lead member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP22262792A
Other languages
Japanese (ja)
Inventor
Hiromasa Gotou
広将 後藤
Hideaki Imai
秀秋 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP22262792A priority Critical patent/JPH0669546A/en
Publication of JPH0669546A publication Critical patent/JPH0669546A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To obtain an LED provided with a good light-emitting characteristic by using a wire bonding method when all electrodes for an element chip using an insulating substrate are connected to individual lead members. CONSTITUTION:Individual chips are cut by using a dicing saw, one chip is taken out, the side of a reflection film 32 is die-bonded to a lead member 43 by using a Pb-Sn solder, electrodes for an n-type GaN layer 30 and an n-type Ga0.8In0.2N layer 41 are connected by 30mum phi Au wires 35 by using a wire bonding apparatus. Then, an i-type GaN layer electrode 27 is connected to a lead member 44 and an i-type Ga0.8In0.2N layer electrode 38 is connected to a lead member 43 respectively by 30mum phi Au wires 35 by using the wire bonding apparatus, and a manufactured light-emitting element 46 is sealed with a transparent epoxy resin. Consequently, all electrodes formed inside the same plane can be connected individually to lead members divided into the same number as the number of electrodes by using a wire bonding method. Thereby, an LED whose performance is stable can be supplied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、絶縁性基板を用いた発
光素子チップをリードフレームに実装した発光ダイオー
ドに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode in which a light emitting element chip using an insulating substrate is mounted on a lead frame.

【０００２】[0002]

【従来の技術】従来、実用化されている発光ダイオード
（ＬＥＤ）に実装されている素子チップはＧａＡｓ、Ｉ
ｎＰなどの導電性基板を用いていることから正負の電極
部は素子チップの表と裏に形成されていた。従来のリー
ドフレームに素子チップを実装し樹脂で封止したＬＥＤ
の断面図を図１２に示す。上述したように導電性基板を
用いて作製した素子チップは表と裏に電極を有する構造
をとっているため、この素子チップ２４をリードフレー
ム４９に接着する場合には片方の電極をリードフレーム
のミラー部５０にハンダあるいは導電性ペーストにより
接着し、もう片方の電極はワイヤーボンディング法によ
ってリード部材４８に接続するような構造をとってい
た。 このリード部材４７、４８に素子チップを実装し
た後にエポキシ樹脂などで封止してＬＥＤ２５を形成し
ていた。 近年では、透明絶縁性基板を用いたフリップ
チップ方式の素子チップによるＬＥＤが提案されてい
る。（特開平４ー１０６７０）この透明絶縁性基板上に
発光層を形成した発光素子チップを用いて作製したＬＥ
Ｄとしては、図１３に示すような構造であり、素子チッ
プ２４の電極１９、２０は正負の電極とも発光層側に位
置し、リード部材５１、５２との接続は、ハンダあるい
は導電性ペーストにより行われていた。2. Description of the Related Art Conventionally, element chips mounted on a light emitting diode (LED) which has been put into practical use are GaAs and I.
Since a conductive substrate such as nP is used, the positive and negative electrode parts are formed on the front and back of the element chip. LED with element chip mounted on conventional lead frame and sealed with resin
FIG. 12 shows a cross-sectional view of FIG. As described above, the element chip manufactured using the conductive substrate has a structure having electrodes on the front and back sides. Therefore, when adhering this element chip 24 to the lead frame 49, one of the electrodes is connected to the lead frame. The structure is such that it is adhered to the mirror portion 50 with solder or a conductive paste, and the other electrode is connected to the lead member 48 by a wire bonding method. After mounting the element chips on the lead members 47 and 48, the LED 25 is formed by sealing with an epoxy resin or the like. In recent years, an LED with a flip-chip type element chip using a transparent insulating substrate has been proposed. (JP-A-4-10670) LE manufactured by using a light emitting element chip in which a light emitting layer is formed on this transparent insulating substrate.
D has a structure as shown in FIG. 13, the electrodes 19 and 20 of the element chip 24 are located on the light emitting layer side with both positive and negative electrodes, and the connection with the lead members 51 and 52 is made by soldering or conductive paste. It was done.

【０００３】[0003]

【発明が解決しようとする課題】上述したように発光素
子チップに導電性基板を用いたときには、基板に電流を
流すことができるので、正負の電極は基板側に１つ、発
光層側に１つ形成することが可能である。リードフレー
ムに接続する際には基板側の電極をリード部材にダイボ
ンディングし、発光層側の電極は他のリード部材にワイ
ヤーボンディングするという方法でＬＥＤを作製してい
た。しかし、透明絶縁性基板を素子チップに用いた場合
には、発光層側に正負一対の電極を有するフリップチッ
プ方式をとるため、素子チップとリード部材の接続は上
述した接続方法をとることができない。このため、発光
層側に形成された２種の電極をリードフレームに接続す
るためには、２本のリード部材の素子チップとの接続面
は平坦にして、この平坦面に素子チップの電極面をハン
ダあるいは導電性ペーストにより接着する工程をとる。
しかしこの方法では、同一面内に２種の電極を形成しな
ければならないため１ｍｍ角以下の素子チップサイズで
は電極サイズは２００μｍ以下としなけらばならず、ハ
ンダあるいは導電性ペーストによる接着工程において２
種の電極部が接触してしまうという問題があった。ま
た、素子チップサイズに対するハンダあるいは導電性ペ
ーストにより接着される電極面積が広いため、より効率
よく発光させるために用いられるミアンダ状、ネット状
あるいはクシ状のような複雑な電極パターンを形成する
ことはできなかった。あるいは、１つのＬＥＤから２色
以上の発光を得る多色発光ダイオードを作製する場合に
は、３カ所以上の電極部を必要とするため電極面積はさ
らに小さくしなければならず、ハンダあるいは導電性ペ
ーストによる電極とリード部材との接続は不可能であっ
た。また、従来提案されているＬＥＤに用いる発光素子
チップは透明な絶縁性基板を使用しており、発光した光
を基板を通して取り出す構造のために基板による光の吸
収があるため発光効率が低下するという問題点もあっ
た。As described above, when a conductive substrate is used for the light emitting element chip, a current can be passed through the substrate, so that one positive and negative electrode is provided on the substrate side and one is provided on the light emitting layer side. It is possible to form one. When connecting to a lead frame, an LED was produced by a method in which an electrode on the substrate side was die-bonded to a lead member and an electrode on the light emitting layer side was wire-bonded to another lead member. However, when the transparent insulating substrate is used for the element chip, the flip chip method having a pair of positive and negative electrodes on the light emitting layer side is adopted, and therefore the element chip and the lead member cannot be connected by the above-described connection method. . Therefore, in order to connect the two kinds of electrodes formed on the light emitting layer side to the lead frame, the connecting surfaces of the two lead members with the element chip should be flat, and the electrode surface of the element chip should be placed on this flat surface. A step of bonding with a solder or a conductive paste.
However, in this method, two kinds of electrodes must be formed in the same plane, so that the electrode size must be 200 μm or less for the element chip size of 1 mm square or less.
There is a problem that the seed electrode portions come into contact with each other. In addition, since the electrode area adhered by solder or conductive paste with respect to the element chip size is large, it is not possible to form a complicated electrode pattern such as meander shape, net shape, or comb shape used for more efficient light emission. could not. Alternatively, when manufacturing a multi-color light emitting diode that emits light of two or more colors from one LED, the electrode area must be further reduced because three or more electrode portions are required, and the solder or conductive It was impossible to connect the electrode and the lead member with the paste. In addition, a light-emitting element chip used for an LED that has been conventionally proposed uses a transparent insulating substrate, and since light is emitted by the substrate due to the structure of extracting the emitted light through the substrate, the luminous efficiency is reduced. There were also problems.

【０００４】本発明は、前記問題点を解決して簡単に再
現よく発光特性の良好なＬＥＤを提供しようとするもの
である。The present invention is intended to solve the above-mentioned problems and to provide an LED which has good emission characteristics in a simple and reproducible manner.

【０００５】[0005]

【課題を解決するための手段】本発明者らは前記問題点
を解決するために鋭意研究を重ねた結果、絶縁性基板を
用いた素子チップの全ての電極と各リード部材とを接続
する際にワイヤーボンディング法を用いることで、再現
よく良好な特性を有するＬＥＤを得ることができるよう
になったものである。As a result of intensive studies to solve the above problems, the present inventors have found that when connecting all the electrodes of an element chip using an insulating substrate to each lead member. By using the wire bonding method for the above, an LED having good characteristics with good reproducibility can be obtained.

【０００６】すなわち、本発明は絶縁性基板上にｎ型半
導体層、ｐ型およびｉ型半導体層から選ばれた２種以上
の組み合わせからなる発光層を少なくとも一つ有し、か
つ半導体層の所定の部位に発光層に電圧を印加するため
の電極を有するプレーナ構造の素子チップにおいて、電
極とリード部材との接続が全てワイヤ−である構造を特
徴とする発光ダイオードを提供するものである。That is, the present invention has at least one light emitting layer composed of a combination of two or more selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer on an insulating substrate, and has a predetermined semiconductor layer. In a planar structure element chip having an electrode for applying a voltage to a light emitting layer at the position of (3), a light emitting diode characterized by a structure in which all connection between an electrode and a lead member is a wire.

【０００７】本発明における絶縁性基板としては表面が
平坦であればよく、透明でもよく不透明でもよい。絶縁
性基板として代表的なものとしては、サファイア（Ａｌ
2 Ｏ 3 ）、石英（ＳｉＯ2 ）、酸化マグネシウム（Ｍｇ
Ｏ）、チタン酸ストロンチウム（ＳｒＴｉＯ3 ）、フッ
化カルシウム（ＣａＦ2 ）、フッ化マグネシウム（Ｍｇ
Ｆ2 ）、酸化チタン（ＴｉＯ2 ）などがある。しかし、
基板上に直接形成する半導体薄膜の格子定数がこの絶縁
性基板の格子定数に極力合ったたものを用いるのがよ
い。この絶縁性基板と基板上に直接形成する半導体薄膜
との格子不整合は１０％以下とするのが好ましく、さら
に好ましくは５％以下とするのがよい。このために該透
明絶縁性基板を所定の角度だけオフしたものを使用する
ことも好ましいものである。例えばＧａＮの場合はサフ
ァイアＲ面を９．２゜オフした基板を用いることが好ま
しいものとなる。また絶縁性基板と半導体薄膜との格子
不整合が非常に大きい場合には、この絶縁性基板と半導
体薄膜との間にバッファ層を設けてもよい。バッファ層
としてはアモルファス状の物質、例えばＡｌＮ、Ｇａ
Ｎ、Ｓｉ、ＳｉＣなど、あるいは単結晶物質として、例
えばＡｌＮ、ＺｎＯ、ＳｉＣ等を設けることができる。The surface of the insulating substrate of the present invention is
It may be flat and may be transparent or opaque. Insulation
Sapphire (Al
2O 3), Quartz (SiO2), Magnesium oxide (Mg
O), strontium titanate (SrTiO3),
Calcium oxide (CaF2), Magnesium fluoride (Mg
F2), Titanium oxide (TiO2)and so on. But,
The lattice constant of the semiconductor thin film formed directly on the substrate is
It is better to use one that matches the lattice constant of the flexible substrate as much as possible.
Yes. This insulating substrate and a semiconductor thin film formed directly on the substrate
The lattice mismatch with is preferably 10% or less.
In particular, it is preferably 5% or less. Because of this
Use a light insulating substrate that has been turned off by a specified angle.
It is also preferable. For example, in the case of GaN,
It is preferable to use a substrate with the R-plane off by 9.2 °.
It will be new. In addition, the lattice of the insulating substrate and the semiconductor thin film
If the mismatch is very large, use this insulating substrate and semiconductor.
A buffer layer may be provided between the thin film and the body thin film. Buffer layer
Is an amorphous substance such as AlN or Ga
Examples of N, Si, SiC, etc., or single crystal materials
For example, AlN, ZnO, SiC or the like can be provided.

【０００８】本発明において絶縁性基板上に発光層を形
成する方法としては、ＭＢＥ（Ｍｏｌｅｃｕｌａｒ Ｂ
ｅａｍ Ｅｐｉｔａｘｙ）法、ＣＢＥ（Ｃｈｅｍｉｃａ
ｌＢｅａｍ Ｅｐｉｔａｘｙ）法、ＭＯＭＢＥ（Ｍｅｔ
ａｌ Ｏｒｇａｎｉｃ ＭＢＥ）法、ＣＶＤ（Ｃｈｅｍ
ｉｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ）法、
ＭＯＣＶＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ ＣＶＤ）法
等の半導体成長装置を用いることができる。上記した薄
膜作製方法により絶縁性基板上に発光層を形成する。こ
の発光層はＭＩＳ構造、ｐｎ接合を有するシングルヘテ
ロ構造およびダブルヘテロ構造、あるいは量子井戸構造
あるいは超格子構造のいずれであってもよい。In the present invention, a method of forming a light emitting layer on an insulating substrate includes MBE (Molecular B).
electron epitaxy) method, CBE (Chemica)
lBeam Epitaxy method, MONBE (Met
al Organic MBE method, CVD (Chem)
ical Vapor Deposition) method,
A semiconductor growth apparatus such as a MOCVD (Metal Organic CVD) method can be used. The light emitting layer is formed on the insulating substrate by the above-described thin film manufacturing method. This light emitting layer may have any of a MIS structure, a single hetero structure having a pn junction and a double hetero structure, a quantum well structure or a superlattice structure.

【０００９】本発明における発光層とは、ｎ型半導体
層、ｐ型およびｉ型半導体層から選ばれた２種以上の組
み合わせからなる発光層のことである。また、これらの
発光層を形成する半導体は、ＩＩＩーＶ族化合物半導
体、ＩＩーＶＩ族化合物半導体のどちらでもよいが、Ｉ
ＩＩーＶ族化合物半導体であるＧａＮ系半導体は絶縁性
基板であるサファイア、ＣａＦ2 、ＭｇＯ等に結晶性の
良好な薄膜の成長が可能であり特に好ましいものであ
る。The light emitting layer in the present invention is a light emitting layer composed of a combination of two or more kinds selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer. The semiconductor forming these light emitting layers may be either a III-V group compound semiconductor or a II-VI group compound semiconductor.
A GaN-based semiconductor, which is a II-V group compound semiconductor, is particularly preferable because it can grow a thin film having good crystallinity on an insulating substrate such as sapphire, CaF 2 , and MgO.

【００１０】本発明での発光素子チップは絶縁性基板を
用いるために発光層側の同一平面内に正負一対の電極を
形成する必要があり、発光層のエッチングを行わなけれ
ばならない。この発光素子チップ作製のために行うエッ
チング方法としては発光層の種類により、ウエットエッ
チング法、ドライエッチング法のどちらを用いてもよ
い。エッチング後に熱処理を行うことも好ましいことで
あり、この熱処理を行うことによりエッチングにより受
けた膜質の劣化を回復することができ、界面抵抗を下げ
て低電圧で発光に必要な電流を得ることができる。熱処
理を行う装置としては管状炉、ランプアニール炉等の雰
囲気を制御できる炉であればよい。Since the light emitting element chip of the present invention uses the insulating substrate, it is necessary to form a pair of positive and negative electrodes in the same plane on the light emitting layer side, and the light emitting layer must be etched. Either an wet etching method or a dry etching method may be used as an etching method for manufacturing the light emitting element chip, depending on the type of the light emitting layer. It is also preferable to perform heat treatment after etching, and by performing this heat treatment, deterioration of the film quality that has been caused by etching can be recovered, and the interface resistance can be lowered to obtain the current necessary for light emission at low voltage. . The apparatus for heat treatment may be a furnace capable of controlling the atmosphere such as a tubular furnace or a lamp annealing furnace.

【００１１】本発明における発光素子チップの電極形成
方法としては、ＭＢＥ法、真空蒸着法、電子ビーム蒸着
法、スパッタ法等がある。電極材料としてはｎ型半導体
とｐ型あるいはｉ型半導体それぞれにオーミック接触が
得られるものが好ましく、金属単体でもよく、２種以上
の金属を混合して合金化したものを用いてもよい。この
オーミック接触を得るための条件はｎ型半導体側の電極
としては半導体の仕事関数よりも小さな仕事関数を有す
る金属がよく、ｐ型半導体側の電極としては半導体の仕
事関数よりも大きな仕事関数を有する金属を用いるのが
よい。例えば、ＩＩＩーＶ族化合物半導体であるＧａＮ
の場合には、ｎ型ＧａＮ層にはＡｌ、Ｉｎ、Ｔｉ、Ｐ
ｂ、Ｓｂ、Ｎｂ、Ｚｒ、Ｍｎ等を電極に用いることがよ
く、ｉ型あるいはｐ型ＧａＮ層にはＡｕ、Ｐｔ、Ｇｅ、
Ａｓ、Ｉｒ、Ｒｅ、Ｒｈ、Ｐｄ、Ｎｉ、Ｗ等を電極に用
いることで良好なオーミック接触が得られる。また、こ
のオーミック電極形成後に素子チップをリード部材に接
着する際に、接着性を向上させるためや、電極部の耐熱
性を向上するためにオーミック電極上にＮｉ、Ｔｉ、Ａ
ｕ、Ｗ等の金属を積層することも好ましい。The electrode forming method of the light emitting element chip in the present invention includes MBE method, vacuum evaporation method, electron beam evaporation method, sputtering method and the like. As the electrode material, a material that can obtain ohmic contact with each of the n-type semiconductor and the p-type or i-type semiconductor is preferable, and a single metal may be used, or a material obtained by mixing two or more kinds of metals and alloying them may be used. The condition for obtaining the ohmic contact is preferably a metal having a work function smaller than that of the semiconductor for the electrode on the n-type semiconductor side, and a work function larger than that of the semiconductor for the electrode on the p-type semiconductor side. It is preferable to use the metal which has. For example, GaN which is a III-V compound semiconductor
In this case, the n-type GaN layer has Al, In, Ti, P
It is preferable to use b, Sb, Nb, Zr, Mn, or the like for the electrode, and Au, Pt, Ge, or the like for the i-type or p-type GaN layer.
Good ohmic contact can be obtained by using As, Ir, Re, Rh, Pd, Ni, W or the like for the electrode. Further, when the element chip is adhered to the lead member after forming the ohmic electrode, Ni, Ti, A is formed on the ohmic electrode in order to improve the adhesiveness and to improve the heat resistance of the electrode portion.
It is also preferable to stack metals such as u and W.

【００１２】電極形成後にＡｒ、Ｎ2 、Ｈｅ等の不活性
ガス流中あるいは該半導体の構成元素を含むガス流中で
半導体の分解温度以下で熱処理することも好ましく、こ
れにより電極と半導体との界面抵抗を下げることが可能
になり、良好なダイオード特性を得ることができる。本
発明におけるＬＥＤは電極側から光を取り出す構造をと
るため電極形状を工夫することが好ましい。発光した光
を電極側から取り出すために該ｐ型あるいはｉ型半導体
層の表面を覆う電極面積は５０％以下、好ましくは４０
％以下、さらに好ましくは３０％以下とすることであ
る。そのために、電極はｐ型あるいはｉ型半導体層の表
面上にパターンを形成することが必要で、パターンの例
としては図４に示すネット状、図５に示すクシ状、図６
に示すミアンダ状とすることができるが、さらにはこれ
らのパターンの組合せや渦状、島状等があるが、特にこ
れらに限定されるものではない。電極の幅と電極間の距
離はｐ型あるいはｉ型半導体層の電気抵抗や印加する電
圧の大きさにより変えればよく、電極の幅を狭くして、
電極間の距離を小さくすれば、光の取り出し効率が向上
する。電極の幅をサブミクロン程度とし、かつ電極間も
サブミクロン程度の間隔とすることによりｐ型あるいは
ｉ型半導体層の表面に均一に電圧を印加するとともに光
の取り出し効率も大きくすることができる。After the electrode is formed, it is also preferable to perform heat treatment at a temperature not higher than the decomposition temperature of the semiconductor in a flow of an inert gas such as Ar, N 2 or He or in a gas flow containing the constituent elements of the semiconductor. The interface resistance can be lowered, and good diode characteristics can be obtained. Since the LED of the present invention has a structure in which light is taken out from the electrode side, it is preferable to devise the electrode shape. The electrode area covering the surface of the p-type or i-type semiconductor layer in order to extract the emitted light from the electrode side is 50% or less, preferably 40%.
% Or less, and more preferably 30% or less. Therefore, it is necessary for the electrode to form a pattern on the surface of the p-type or i-type semiconductor layer, and examples of the pattern include a net shape shown in FIG. 4, a comb shape shown in FIG.
The meandering shape shown in FIG. 2 can be used, and further, there are combinations of these patterns, a spiral shape, an island shape, and the like, but are not particularly limited thereto. The width of the electrodes and the distance between the electrodes may be changed according to the electric resistance of the p-type or i-type semiconductor layer and the magnitude of the applied voltage.
If the distance between the electrodes is reduced, the light extraction efficiency is improved. By setting the width of the electrodes to about submicron and the distance between the electrodes to be about submicron, it is possible to uniformly apply a voltage to the surface of the p-type or i-type semiconductor layer and increase the light extraction efficiency.

【００１３】また、本発明においては、基板上の発光層
が形成されていない面上に図１１に示すような少なくと
も一種の金属反射層を設けることも好ましいものとな
る。この金属層はｎ型半導体層およびｐ型あるいはｉ型
半導体層を組み合わせてなる発光層において発光して基
板を通して出てくる光を反射して電極側から取り出すこ
とを可能とするものである。これにより、発光素子の光
の取り出し効率を高めることができる。金属反射層とし
て使われる材料としてはＡｌ、Ｉｎ、Ｃｕ、Ａｇ、Ｐ
ｔ、Ｉｒ、Ｐｄ、Ｒｈ、Ｗ、Ｍｏ、Ｔｉ、Ｎｉ等の金属
の単体あるいはそれらの合金がある。金属反射層は、一
層だけでもよいが、リードフレームに実装するときの耐
ハンダ性、耐熱性や耐ボンディング性を向上せしめるた
めにＮｉ、Ｗ、Ｍｏ等の高融点の金属を積層した構造と
することも好ましいものとなる。In the present invention, it is also preferable to provide at least one kind of metal reflection layer as shown in FIG. 11 on the surface of the substrate on which the light emitting layer is not formed. This metal layer emits light in a light emitting layer formed by combining an n-type semiconductor layer and a p-type or i-type semiconductor layer, and makes it possible to reflect the light emitted through the substrate and take it out from the electrode side. Thereby, the light extraction efficiency of the light emitting element can be improved. Materials used for the metal reflection layer include Al, In, Cu, Ag, P
There are simple metals such as t, Ir, Pd, Rh, W, Mo, Ti and Ni or alloys thereof. The metal reflection layer may be a single layer, but it has a structure in which refractory metals such as Ni, W and Mo are laminated in order to improve solder resistance, heat resistance and bonding resistance when mounted on a lead frame. This is also preferable.

【００１４】本発明におけるリードフレームの形状は素
子チップをリード部材に固定するための接続部と、素子
チップのそれぞれの部位に電圧を印加するための各電極
と他のリード部材をワイヤ−によってそれぞれ接続でき
る構造であればよく発光素子チップの電極形状により変
えることができる。リードフレームは発光を有効に集光
するためにミラー面を設けることが望ましい。The shape of the lead frame in the present invention is such that a connecting portion for fixing the element chip to the lead member, each electrode for applying a voltage to each portion of the element chip, and another lead member are respectively connected by wires. Any structure that can be connected can be used and can be changed depending on the electrode shape of the light emitting element chip. It is desirable that the lead frame be provided with a mirror surface in order to collect the emitted light effectively.

【００１５】本発明における発光素子チップをリード部
材にダイボンディングを行う際の接着の材料としては、
一般的に使われているものが使用できる。例えばＡｕー
Ｓｉ、ＰｂーＳｎ合金系ハンダや、このハンダに少量の
Ｂｉ、Ｓｂ、Ａｇ、Ｃｄ、Ｚｎ、Ｉｎ等の金属を添加し
たもの、ＢｉにＮａ、Ｔｌ、Ｃｄ、Ｓｎ、Ｐｂ等を添加
し合金化したもの、ＩｎにＺｎ、Ｃｄ、Ｓｎ、Ｂｉ等を
添加し合金化したもの、ＧａにＡｇ、Ｚｎ、Ｓｎ、Ｉｎ
等を添加し合金化したもの、Ａｕ、Ａｌ、Ｉｎ、Ａｇ等
の金属あるいはＡｇ、Ａｕ、Ｃｕ等を含んだ導電性ペー
ストがある。素子チップとリード部材とを接着する方法
としては、従来のダイボンディング装置を用いた方法が
ある。即ち、接着層を素子チップの該電極部、もしくは
リード部材の素子チップの接着面に蒸着法、塗布法ある
いはメッキ法等により形成した後、該電極部と該リード
部材を密着させながらリード部材を接着材料の融点以上
に加熱して接着を行う。As an adhesive material for die-bonding the light emitting element chip of the present invention to the lead member,
What is generally used can be used. For example, Au-Si, Pb-Sn alloy-based solder, a small amount of metal such as Bi, Sb, Ag, Cd, Zn, and In added to this solder, Bi, Na, Tl, Cd, Sn, Pb, etc. Alloyed by adding, alloyed by adding In, Zn, Cd, Sn, Bi, etc., Ga, Ag, Zn, Sn, In
There is a conductive paste containing a metal such as Au, Al, In or Ag, or a metal containing Ag, Au, Cu or the like. As a method for adhering the element chip and the lead member, there is a method using a conventional die bonding apparatus. That is, after forming an adhesive layer on the electrode portion of the element chip or on the adhesive surface of the element chip of the lead member by a vapor deposition method, a coating method, a plating method, or the like, the lead member is attached while closely adhering the electrode portion and the lead member. Bonding is performed by heating the adhesive material to its melting point or higher.

【００１６】また本発明における発光素子チップの電極
部とリード部材を配線する際にはワイヤーボンダー法を
用いることが特徴である。ダイボンディング法により素
子チップをリード部材に固定した後に、ワイヤーボンデ
ィング装置にセットして加熱および、あるいは超音波を
印加することにより電極部とリード部材とを接続する。
このとき用いるワイヤーの材料としては、Ａｕ、Ａｇ、
Ｃｕ、Ａｌ等の金属、Ａｕ−Ｓｉ、Ａｌ−Ｓｉ、Ａｌ−
Ｍｇ、Ａｌ−Ｓｉ−Ｍｇ、Ａｌ−Ｎｉ等の合金があり、
どの材料を使用するかは発光素子チップの電極部の材料
やワイヤ−ボンディングの作業性を考慮して選べばよ
い。なかでも、ＡｕやＡｌ−Ｓｉが作業性がよいという
ことで好ましい。ワイヤ−の太さは、発光素子チップの
電極部の大きやワイヤ−ボンディングの作業性を考慮し
て選べばよく、通常は２０〜３００μｍφである。ま
た、ワイヤ−の酸化を防ぐために、不活性ガス中でワイ
ヤ−ボンディングを行うことも好ましい方法である。A feature of the present invention is that a wire bonder method is used when wiring the electrode portion of the light emitting element chip and the lead member. After the element chip is fixed to the lead member by the die bonding method, it is set in a wire bonding device and heated and / or ultrasonic waves are applied to connect the electrode portion and the lead member.
The material of the wire used at this time is Au, Ag,
Cu, Al and other metals, Au-Si, Al-Si, Al-
There are alloys such as Mg, Al-Si-Mg, and Al-Ni,
The material to be used may be selected in consideration of the material of the electrode portion of the light emitting element chip and the workability of wire bonding. Among them, Au and Al-Si are preferable because they have good workability. The thickness of the wire may be selected in consideration of the size of the electrode portion of the light emitting element chip and the workability of wire bonding, and is usually 20 to 300 μmφ. It is also a preferable method to perform wire bonding in an inert gas in order to prevent the wire from being oxidized.

【００１７】本発明における封止材料としては発光素子
チップの発光波長範囲での光透過率が８０％以上の透光
性材料を使用することが好ましい。この透光性材料とし
ては、メタクリル系樹脂、エポキシ系樹脂、ポリカーボ
ネート系樹脂、ポリスチレン系樹脂、ポレオレフィン系
樹脂あるは低融点ガラスの少なくとも一種を使用するこ
とができる。封止方法としては、たとえば所望形状の金
型にこれらの透光性材料の原料または加熱溶融体を注形
して金型内で固化させる方法を用いることができる。こ
の固化の方法として、モノマーやオリゴマーの熱または
光による重合固化、加熱溶融体では冷却固化、化学反応
等を挙げることができる。この透光性材料には必要があ
れば、色調調整や視感度補正のための色素、顔料、蛍光
体などを、樹脂の安定化のための酸化防止剤、安定剤、
成形加工のための潤滑剤、滑剤を添加することも可能で
ある。As the sealing material in the present invention, it is preferable to use a translucent material having a light transmittance of 80% or more in the emission wavelength range of the light emitting element chip. As the translucent material, at least one of methacrylic resin, epoxy resin, polycarbonate resin, polystyrene resin, polyolefin resin or low melting glass can be used. As a sealing method, for example, a method of casting a raw material of these translucent materials or a heating melt into a mold of a desired shape and solidifying in the mold can be used. Examples of the solidification method include polymerization and solidification of monomers and oligomers by heat or light, cooling and solidification of a heated melt, and chemical reaction. If necessary, this translucent material may contain dyes, pigments, phosphors, etc. for color tone adjustment and visibility correction, antioxidants, stabilizers for resin stabilization,
It is also possible to add a lubricant and a lubricant for molding.

【００１８】以上説明した各方法を用いて作製したＬＥ
Ｄの例を図３に示すが、これに限定されるものではな
い。素子チップ２４は、絶縁基板上にｎ型半導体層、ｐ
型およびｉ型半導体から選ばれた２種以上の組み合わせ
からなる発光層を少なくとも一つ有し、かつそれぞれの
半導体層の所定の部位に、発光層に電圧を印加するため
の電極を有するプレ−ナ構造の素子チップである。この
素子チップの基板面あるいはリ−ド部材２２の接着面に
蒸着法でハンダを蒸着した後、リ−ド部材２２の接着面
に素子チップ２４を載せハンダの融点以上に加熱して接
着する。その後、各電極とそれぞれのリ−ド部材とをワ
イヤ−ボンディング法を用いて金線により接続する。そ
の後、透光性材料により封止してＬＥＤ２５を作製す
る。LE manufactured by using each method described above
An example of D is shown in FIG. 3, but is not limited to this. The element chip 24 includes an n-type semiconductor layer, p
Of at least one light-emitting layer made of a combination of two or more selected from n-type and i-type semiconductors, and an electrode for applying a voltage to the light-emitting layer at a predetermined portion of each semiconductor layer. It is an element chip with a rectangular structure. After the solder is vapor-deposited on the substrate surface of the element chip or the adhesive surface of the lead member 22 by the vapor deposition method, the element chip 24 is placed on the adhesive surface of the lead member 22 and heated to a temperature higher than the melting point of the solder for adhesion. After that, each electrode and each lead member are connected by a gold wire using a wire bonding method. After that, the LED 25 is manufactured by sealing with a translucent material.

【００１９】以下、一例として絶縁性基板としてＡｌ2
Ｏ3 を使用してＭＢＥ法を用いてＧａＮ薄膜を成膜しＬ
ＥＤを作製する方法について説明するが、とくにこれに
限定されるものではない。装置としては、図１に示すよ
うな真空容器１内に、蒸発用ルツボ（クヌードセンセ
ル）２、３および４、ガスセル７、基板加熱ホルダー５
を備えたガスソースＭＢＥ装置を使用した。In the following, as an example, an insulating substrate made of Al 2
A GaN thin film is formed using the MBE method using O 3.
A method of manufacturing the ED will be described, but the method is not particularly limited to this. As an apparatus, a vacuum vessel 1 as shown in FIG. 1 is provided with an evaporation crucible (Knudsen cell) 2, 3 and 4, a gas cell 7, and a substrate heating holder 5.
A gas source MBE apparatus equipped with

【００２０】蒸発用ルツボ２にはＧａ金属を入れ、基板
面において１０13〜１０19／ｃｍ2・ｓｅｃになる温度
に加熱した。アンモニアの導入にはガス導入管８を用
い、アンモニアをガスセル７内から基板６に直接吹き付
けるようにした。アンモニアの導入量は基板表面におい
て１０16〜１０20／ｃｍ2 ・ｓｅｃになるように供給し
た。蒸発用ルツボ３にはＩｎ、Ａｌ等を入れ、所定の組
成の化合物半導体、および所定のキャリア密度を有する
半導体となるように温度および時間を制御して成膜を行
なう。蒸発用ルツボ４にはＭｇ、Ｚｎ、Ｂｅ、Ｓｂ、Ｓ
ｉ、Ｇｅ、Ｃ、Ｓｎ、Ｈｇ、Ａｓ、Ｐ等を入れ、所定の
供給量になるように温度および供給時間を制御すること
によりドーピングを行ない、ｎ型およびｉ型あるいはｐ
型半導体層を成膜する。Ga metal was placed in the evaporation crucible 2 and heated to a temperature of 10 13 to 10 19 / cm 2 · sec on the substrate surface. A gas introduction pipe 8 was used to introduce ammonia, and ammonia was blown directly from the gas cell 7 onto the substrate 6. Ammonia was supplied so that the amount of ammonia introduced was 10 16 to 10 20 / cm 2 · sec on the substrate surface. In, Al, etc. are put in the evaporation crucible 3 and a film is formed by controlling temperature and time so that a compound semiconductor having a predetermined composition and a semiconductor having a predetermined carrier density are obtained. The evaporation crucible 4 has Mg, Zn, Be, Sb, S
i, Ge, C, Sn, Hg, As, P, etc. are added, and doping is performed by controlling the temperature and the supply time so as to obtain a predetermined supply amount.
A type semiconductor layer is formed.

【００２１】基板６にはサファイアＲ面を使用し、２０
０〜９００℃に加熱した。サファイアＲ面基板は、オフ
角が０．８度以下のものが好ましい。まず、基板６を真
空容器１内で７５０℃で加熱した後、各ルツボを所定の
成長温度に設定し、まず蒸発用ルツボ３を開き、０．１
〜３０オングストローム／ｓｅｃの成長速度で０．０５
〜２μｍの厚みのｎ型ＧａＮ薄膜を作製する。さらにそ
の後、Ｚｎをチャージした蒸発用ルツボ４のシャッター
を開き、０．１〜３０オングストローム／ｓｅｃの成長
速度で０．０１〜１μｍの厚みでｉ型あるいはｐ型Ｇａ
Ｎ薄膜を成膜して発光層を形成する。この成膜時には常
にガスセルを加熱し基板表面にアンモニアを供給する。A sapphire R surface is used for the substrate 6, and 20
Heated to 0-900 ° C. The off-angle of the sapphire R-plane substrate is preferably 0.8 degrees or less. First, after heating the substrate 6 in the vacuum container 1 at 750 ° C., each crucible is set to a predetermined growth temperature, and the evaporation crucible 3 is first opened to
0.05 at a growth rate of ~ 30 Å / sec
An n-type GaN thin film having a thickness of ˜2 μm is prepared. After that, the shutter of the evaporation crucible 4 charged with Zn is opened, and the i-type or p-type Ga is grown at a growth rate of 0.1 to 30 Å / sec and a thickness of 0.01 to 1 μm.
An N thin film is formed to form a light emitting layer. During this film formation, the gas cell is always heated to supply ammonia to the surface of the substrate.

【００２２】以上のような方法で成膜した発光層を有す
るＧａＮ薄膜を用いてＬＥＤを作製する工程を図２
（ａ）から図２（ｈ）にしたがって説明する。真空蒸着
法を用いてＡｌ2 Ｏ3 側に金属反射膜１７を蒸着する
（ａ）。ＧａＮ薄膜表面にレジストを塗布する。レジス
トの膜厚はエッチングしたいＧａＮ薄膜の厚みによって
変えればよく０．１〜３μｍとするのが好ましい。スピ
ンコーターの条件は２５００ｒｐｍ、３０ｓｅｃであ
る。塗布後に９０℃に加熱されたクリーンオーブン内で
３０分間プレベークする（ｂ）。その後、素子パターン
形成用マスクを用いてＵＶ露光・現像を行った（ｃ）。
Ａｒをガスとして用いてイオンミリング法によりｉ層あ
るいはｐ層のＧａＮ薄膜１４を除去する（ｄ）。イオン
ミリング終了後、アセトンを用いてレジストを除去す
る。FIG. 2 shows a process of manufacturing an LED using a GaN thin film having a light emitting layer formed by the above method.
A description will be given from (a) to FIG. 2 (h). The metal reflection film 17 is deposited on the Al 2 O 3 side by using the vacuum deposition method (a). A resist is applied on the surface of the GaN thin film. The thickness of the resist may be changed depending on the thickness of the GaN thin film to be etched, and is preferably 0.1 to 3 μm. The spin coater conditions are 2500 rpm and 30 sec. After application, pre-baking is carried out for 30 minutes in a clean oven heated to 90 ° C (b). After that, UV exposure and development were performed using a device pattern forming mask (c).
The i-layer or p-layer GaN thin film 14 is removed by ion milling using Ar as a gas (d). After the ion milling is completed, the resist is removed using acetone.

【００２３】なお、各工程でのイオンミリングを行う時
間はエッチングを行う膜厚によって決めることができ
る。以上の工程の後、管状炉内に試料をセットしてアン
モニアを雰囲気として５００℃で３０分間熱処理した。
熱処理後、再度レジストを塗布し、プレベークを行い、
続いてｎ層電極形成用マスクを用いてＵＶ露光・現像を
行った後（ｅ）、真空蒸着法によりｎ型ＧａＮ層１５の
電極としてＡｌを３０００オングストロームの厚さに蒸
着し、リフトオフにより電極パターン１９を形成した
（ｆ）。ついで再度レジストを塗布し、プレベークを行
い、ｉ層電極形成用マスクを用いてＵＶ露光・現像を行
った後（ｇ）、真空蒸着法によりｐ型あるいはｉ型Ｇａ
Ｎ層１４の電極としてＡｕを３０００オングストローム
の厚さに蒸着し、リフトオフにより電極パターン２０を
形成した（ｈ）。その後、Ａｒ流中で３００℃、１時間
の加熱処理を行った。The time for performing ion milling in each step can be determined by the film thickness for etching. After the above steps, the sample was set in a tubular furnace and heat-treated at 500 ° C. for 30 minutes in an atmosphere of ammonia.
After heat treatment, apply resist again and pre-bak,
Then, UV exposure and development are performed using a mask for forming an n-layer electrode (e), then Al is deposited as an electrode of the n-type GaN layer 15 to a thickness of 3000 Å by a vacuum deposition method, and an electrode pattern is formed by lift-off. 19 was formed (f). Then, the resist is applied again, pre-baked, UV exposed and developed using the mask for forming the i-layer electrode (g), and then p-type or i-type Ga is formed by the vacuum deposition method.
Au was vapor-deposited to a thickness of 3000 Å as an electrode of the N layer 14 and lifted off to form an electrode pattern 20 (h). After that, heat treatment was performed at 300 ° C. for 1 hour in Ar flow.

【００２４】以上のようにして作製した発光素子チップ
の金属反射膜をハンダによりリード部材２２に接着し、
ｎ型ＧａＮ層、ｉ型ＧａＮ層の電極をワイヤーボンダー
装置を用いて３０μｍφＡｕ線２３でそれぞれリード部
材２１、リード部材２２にボンディングした。その後、
発光素子チップを透明エポキシ樹脂によりモールディン
グを施し、図３に示す様な５ｍｍφＬＥＤ２５を作製し
た。The metal reflection film of the light emitting device chip manufactured as described above is bonded to the lead member 22 by soldering,
The electrodes of the n-type GaN layer and the i-type GaN layer were bonded to the lead member 21 and the lead member 22 with a 30 μmφAu wire 23 using a wire bonder device, respectively. afterwards,
The light emitting element chip was molded with a transparent epoxy resin to prepare a 5 mmφ LED 25 as shown in FIG.

【００２５】[0025]

【実施例】以下，実施例によりさらに詳細に説明する。EXAMPLES The present invention will be described in more detail below with reference to examples.

【００２６】[0026]

【実施例１】絶縁性基板としてＡｌ2 Ｏ3 Ｒ面を使用
し、ＭＢＥ法によりＧａＮ薄膜を成膜し、ミアンダ状の
電極構造を有する素子チップを用いてＬＥＤを作製した
例について説明する。図１に示すような真空容器１内
に、蒸発用ルツボ２、４、ガスセル７、および基板加熱
ホルダー５、さらにガスセル７にガスを供給するための
ガス導入管８を備えたＭＢＥ装置を用いた。Example 1 An example in which an Al 2 O 3 R surface is used as an insulating substrate, a GaN thin film is formed by the MBE method, and an LED is manufactured using an element chip having a meandering electrode structure will be described. An MBE apparatus provided with an evaporation crucible 2, 4, a gas cell 7, a substrate heating holder 5, and a gas introduction pipe 8 for supplying gas to the gas cell 7 was used in a vacuum container 1 as shown in FIG. .

【００２７】蒸発用ルツボ２にはＧａ金属を入れ、１０
５０℃に加熱した。ガスとしてはアンモニアを使用し、
ガス導入管８を通してガスセル７に５ｃｃ／ｍｉｎの速
度で供給した。アンモニアガスは基板６に直接供給する
ような構造とした。基板６としては、オフ角が０．５度
のサファイアＲ面を使用する。真空容器内の圧力は、成
膜時において２×１０-6Ｔｏｒｒであった。Ga metal was put in the evaporation crucible 2 and 10
Heated to 50 ° C. Ammonia is used as gas,
It was supplied to the gas cell 7 through the gas introduction pipe 8 at a rate of 5 cc / min. Ammonia gas was directly supplied to the substrate 6. As the substrate 6, a sapphire R surface having an off angle of 0.5 degree is used. The pressure in the vacuum container was 2 × 10 −6 Torr during film formation.

【００２８】まず、基板６を９００℃で３０分間加熱
し、ついで７５０℃の温度に保持し成膜を行う。成膜は
アンモニアを３００℃に加熱したガスセル７から供給し
ながらＧａのルツボのシャッターを開けて行い、１．５
オングストローム／ｓｅｃの成膜速度で膜厚０．５μm
のｎ型ＧａＮ薄膜を作製した。さらにＭｇをチャージし
て３００℃に保たれた蒸発用ルツボ４のシャッターを開
けＭｇドープのＧａＮ薄膜を１．５オングストローム／
ｓｅｃの成膜速度で膜厚０．０５μｍの厚さで成膜して
発光層を形成した。この作製した薄膜のＲＨＥＥＤパタ
ーンはストリーク状で結晶性および平坦性が良好であ
り、抵抗を測定したところ、１０ＭΩ以上の抵抗があり
絶縁状態であった。First, the substrate 6 is heated at 900 ° C. for 30 minutes, and then the temperature is maintained at 750 ° C. to form a film. The film formation was performed by opening the shutter of the Ga crucible while supplying ammonia from the gas cell 7 heated to 300 ° C.
0.5 μm film thickness at film forming rate of Angstrom / sec
Of n-type GaN thin film was prepared. Furthermore, the shutter of the evaporation crucible 4 which was charged with Mg and kept at 300 ° C. was opened, and the Mg-doped GaN thin film was 1.5 angstrom /
A light emitting layer was formed by forming a film with a thickness of 0.05 μm at a film forming rate of sec. The RHEED pattern of the produced thin film was streaky and had good crystallinity and flatness, and the resistance was measured and found to be 10 MΩ or more and in an insulating state.

【００２９】発光層が形成されている基板面の反対面に
真空蒸着法を用いて２×１０ー6Ｔｏｒｒの真空中でＡｌ
を３０００オングストロームの厚みで蒸着し反射膜を形
成した。続いて発光層上にスピンコーターを用いて２５
００ｒｐｍ、３０ｓｅｃの条件でレジストを塗布し、９
０℃のクリーンオーブン中で３０分間プレベークした。
ベーク後、素子パターン形成用のマスクを用いてＵＶ露
光し、現像した。続いて、加速電圧５００Ｖ、圧力２×
１０ー4Ｔｏｒｒの条件のＡｒで１５分間イオンミリング
を行い素子パターン形成を行った。その後、アセトンを
用いてレジストを除去した。次に、再度スピンコーター
を用いて２５００ｒｐｍ、３０ｓｅｃの条件でレジスト
を塗布し、９０℃のクリーンオーブン中で３０分間プレ
ベークした。ベーク後、ｉ層除去用のマスクを用いてＵ
Ｖ露光し、現像した。続いて、加速電圧５００Ｖ、圧力
２×１０ー4Ｔｏｒｒの条件のＡｒ雰囲気中で１分間イオ
ンミリングを行い不必要なｉ層を除去した。その後、ア
セトンでレジストを除去した。次いで、管状炉にセット
して１０ｃｃ／ｍｉｎのアンモニアガス流中で５００
℃、３０分間の熱処理を行った。さらに、スピンコータ
ーを用いて２５００ｒｐｍ、３０ｓｅｃの条件でレジス
トを塗布し、９０℃のクリーンオーブン中で３０分間プ
レベークした。ベーク後、ｎ型ＧａＮ層の電極形成用の
マスクを用いてＵＶ露光し、現像した。続いて、真空蒸
着機に装着し２×１０ー6Ｔｏｒｒの真空中でＡｌ金属を
０．２μｍの厚さで真空蒸着した。その後、アセトンで
リフトオフして電極パターンを形成した。ついで、ｉ型
ＧａＮ層の電極形成用のマスクを用いてＵＶ露光し、現
像した。続いて、真空蒸着機に装着し２×１０ー6Ｔｏｒ
ｒの真空中でＡｕ金属を０．２μｍの厚さで真空蒸着し
た。その後、アセトンでリフトオフして電極パターンを
形成した。この作製した発光素子をＡｒ流中で３００℃
で１時間加熱処理を行い、ミアンダ状の電極構造を有す
る素子チップを完成させた。作製した素子チップの側面
図および上面図を図７（ａ）、（ｂ）に示した。Al in a vacuum of 2 × 10 −6 Torr was formed on the surface opposite to the surface of the substrate on which the light emitting layer was formed by vacuum evaporation.
Was evaporated to a thickness of 3000 Å to form a reflective film. Then, using a spin coater on the light emitting layer, 25
Apply the resist under the conditions of 00 rpm and 30 sec.
Prebaked in a 0 ° C. clean oven for 30 minutes.
After baking, UV exposure was performed using a mask for element pattern formation, and development was performed. Then, acceleration voltage 500V, pressure 2 ×
Ion milling was performed for 15 minutes with Ar under the condition of 10 −4 Torr to form a device pattern. Then, the resist was removed using acetone. Next, the resist was applied again using a spin coater under the conditions of 2500 rpm and 30 sec, and prebaked in a clean oven at 90 ° C. for 30 minutes. After baking, U is removed using a mask for removing the i layer.
V exposed and developed. Subsequently, ion milling was performed for 1 minute in an Ar atmosphere under the conditions of an acceleration voltage of 500 V and a pressure of 2 × 10 −4 Torr to remove an unnecessary i layer. Then, the resist was removed with acetone. Then, it was set in a tubular furnace and 500 in an ammonia gas flow of 10 cc / min.
Heat treatment was performed at 30 ° C. for 30 minutes. Further, a resist was applied using a spin coater under the conditions of 2500 rpm and 30 sec, and prebaked in a clean oven at 90 ° C. for 30 minutes. After baking, it was exposed to UV using a mask for forming an electrode of the n-type GaN layer and developed. Then, it was mounted on a vacuum vapor deposition machine, and Al metal was vacuum vapor deposited to a thickness of 0.2 μm in a vacuum of 2 × 10 −6 Torr. Then, liftoff was performed with acetone to form an electrode pattern. Then, UV exposure was performed and development was performed using a mask for forming an electrode of the i-type GaN layer. Then, it is attached to a vacuum vapor deposition machine and 2 × 10 -6 Tor
Au metal was vacuum-deposited to a thickness of 0.2 μm in a vacuum of r. Then, liftoff was performed with acetone to form an electrode pattern. The manufactured light emitting device was heated at 300 ° C. in Ar flow.
Was heat-treated for 1 hour to complete an element chip having a meandering electrode structure. A side view and a top view of the manufactured element chip are shown in FIGS. 7 (a) and 7 (b).

【００３０】各チップのカッティングはダイシングソー
を用いて行った。１素子チップは０．５ｍｍ×０．５ｍ
ｍとした。このうちの１チップを取り出し反射膜側をＡ
ｇペーストによりリード部材にダイボンディングした。
さらにｎ型ＧａＮ層電極、ｉ型ＧａＮ層電極とそれぞれ
のリード部材とをワイヤーボンディング装置を用いて３
０μｍφＡｕ線で接続した。上記の方法で作製した発光
素子を透明エポキシ樹脂で封止して図８に示すようなＬ
ＥＤを作製した。The cutting of each chip was performed using a dicing saw. One element chip is 0.5 mm x 0.5 m
m. Take one of these chips and set the reflective film side to A
The lead member was die-bonded with the g paste.
Further, the n-type GaN layer electrode, the i-type GaN layer electrode, and the respective lead members are connected to each other by using a wire bonding device.
The connection was made with a 0 μmφAu wire. The light emitting device manufactured by the above method is sealed with a transparent epoxy resin, and L as shown in FIG.
An ED was made.

【００３１】同様の方法で１００個のＬＥＤを作製した
ところ、９９個のＬＥＤで発光が確認された。このＬＥ
Ｄの発光強度を測定したところ８Ｖ，２０ｍＡで６０ｍ
ｃｄであり、青色の発光が観測された。When 100 LEDs were produced by the same method, light emission was confirmed with 99 LEDs. This LE
When the emission intensity of D was measured, it was 60 m at 8 V and 20 mA.
cd, and blue light emission was observed.

【００３２】[0032]

【比較例１】実施例１と同様の方法によりＡｌ2 Ｏ3 基
板上に成膜した発光層を有するＧａＮ薄膜を用いて素子
化を行った。素子作製過程も実施例１と同様の方法によ
り行い、ｎ型ＧａＮ層、ｉ型ＧａＮ層の両電極ともＡｇ
ペーストにより、リード部材にダイボンディングを行っ
た後、透明エポキシ樹脂で封止してＬＥＤを作製した。
同様の方法で１００個のＬＥＤを作製したところ、Ａｇ
ペーストにより正負の電極がつながってしまい、９個の
ＬＥＤでしか発光するものは得られなかった。COMPARATIVE EXAMPLE 1 A device was formed by using a GaN thin film having a light emitting layer formed on an Al 2 O 3 substrate by the same method as in Example 1. The device manufacturing process was also performed in the same manner as in Example 1, and both electrodes of the n-type GaN layer and the i-type GaN layer were Ag.
The lead member was die-bonded with a paste and then sealed with a transparent epoxy resin to produce an LED.
When 100 LEDs were made by the same method, Ag
The positive and negative electrodes were connected to each other by the paste, and only 9 LEDs were able to emit light.

【００３３】[0033]

【実施例２】絶縁性基板としてＡｌ2 Ｏ3 Ｒ面を使用
し、ＭＢＥ法によりＧａ1ーx Ｉｎx Ｎ薄膜を成膜し２色
発光のＬＥＤを作製した例について説明する。図２に示
すような真空容器１内に、蒸発用ルツボ２、３、４、ガ
スセル７、および基板加熱ホルダー５、さらにガスセル
７にガスを供給するためのガス導入管８を備えたＭＢＥ
装置を用いた。Example 2 An example in which an Al 2 O 3 R surface is used as an insulating substrate and a Ga 1 -x In x N thin film is formed by the MBE method to manufacture a two-color emitting LED will be described. An MBE having an evaporation crucible 2, 3, 4, a gas cell 7, a substrate heating holder 5, and a gas introduction pipe 8 for supplying a gas to the gas cell 7 in a vacuum container 1 as shown in FIG.
The device was used.

【００３４】蒸発用ルツボ２にはＧａ金属を入れ、１０
２０℃に加熱し、蒸着用ルツボ３にはＩｎ金属を入れ１
０００℃に加熱した。ガスとしてはアンモニアを使用
し、ガス導入管８を通してガスセル７に５ｃｃ／ｍｉｎ
の速度で供給した。アンモニアガスは基板６に直接供給
するような構造とした。基板６としては、オフ角が０．
５度のサファイアＲ面を使用する。Ga metal was put in the evaporation crucible 2 and
Heat to 20 ° C and put In metal into the evaporation crucible 3 1
Heated to 000 ° C. Ammonia is used as the gas, and 5 cc / min is supplied to the gas cell 7 through the gas introduction pipe 8.
Was fed at the rate of. Ammonia gas was directly supplied to the substrate 6. The substrate 6 has an off angle of 0.
Use a 5 degree sapphire R surface.

【００３５】真空容器内の圧力は、成膜時において２×
１０-6Ｔｏｒｒであった。まず、基板６を９００℃で３
０分間加熱し、ついで７００℃の温度に保持し成膜を行
う。成膜はアンモニアを３００℃に加熱したガスセル７
から供給しながらＧａとＩｎのルツボのシャッターを開
けて行い、１．５オングストローム／ｓｅｃの成膜速度
で膜厚０．５μm のｎ型Ｇａ0.8 Ｉｎ0.2 Ｎ薄膜を作製
した。さらにＭｇをチャージして３００℃に保たれた蒸
発用ルツボ４のシャッターを開けＭｇをドーピングした
ｉ型Ｇａ0.8 Ｉｎ0.2 Ｎ薄膜を１．５オングストローム
／ｓｅｃの成膜速度で膜厚０．０５μｍの厚さで成膜し
て第１の発光層を形成した。次に基板温度を７５０℃に
上げて３０分間温度を安定させた後、Ｇａのルツボのシ
ャッターを開けて１．５オングストローム／ｓｅｃの成
長速度で膜厚０．５μｍのｎ型ＧａＮ薄膜を成長し、さ
らにその上に蒸着ルツボ２および４のシャッターを開け
てＭｇをドーピングしたｉ型ＧａＮ薄膜を１．５オング
ストローム／ｓｅｃの成長速度で膜厚０．０５μｍの厚
さで成膜して第２の発光層を形成した。The pressure in the vacuum container is 2 × during film formation.
It was 10 −6 Torr. First, the substrate 6 is heated at 900 ° C. for 3
A film is formed by heating for 0 minutes and then maintaining the temperature at 700 ° C. The film is formed by a gas cell 7 in which ammonia is heated to 300 ° C.
From the crucible of Ga and In, the n-type Ga 0.8 In 0.2 N thin film having a film thickness of 0.5 μm was formed at a film forming rate of 1.5 Å / sec. Further, the shutter of the evaporation crucible 4 which was charged with Mg and kept at 300 ° C. was opened, and the Mg-doped i-type Ga 0.8 In 0.2 N thin film was formed to a film thickness of 0.05 μm at a film forming rate of 1.5 Å / sec. A film having a thickness was formed to form a first light emitting layer. Next, after raising the substrate temperature to 750 ° C. and stabilizing the temperature for 30 minutes, the shutter of the Ga crucible was opened to grow an n-type GaN thin film with a film thickness of 0.5 μm at a growth rate of 1.5 Å / sec. Further, the shutters of the evaporation crucibles 2 and 4 were opened, and an Mg-doped i-type GaN thin film was formed to a thickness of 0.05 μm at a growth rate of 1.5 angstrom / sec. A light emitting layer was formed.

【００３６】発光層が形成されている基板面の反対面に
真空蒸着法を用いて２×１０ー6Ｔｏｒｒの真空中でＡｌ
を３０００オングストロームの厚さで蒸着し反射膜を形
成した。続いて、発光層上にスピンコーターを用いて２
５００ｒｐｍ、３０ｓｅｃの条件でレジストを塗布し、
９０℃のクリーンオーブン中で３０分間プレベークし
た。ベーク後、素子パターン形成用のマスクを用いてＵ
Ｖ露光し、現像した。続いて、加速電圧５００Ｖ、圧力
２×１０ー4Ｔｏｒｒの条件のＡｒで２５分間イオンミリ
ングを行い素子パターン形成を行った。その後、アセト
ンを用いてレジストを除去した。次に、再度スピンコー
ターを用いて２５００ｒｐｍ、３０ｓｅｃの条件でレジ
ストを塗布し、９０℃のクリーンオーブン中で３０分間
プレベークした。ベーク後、フォトマスクを用いてＵＶ
露光し、現像した。続いて、加速電圧５００Ｖ、圧力２
×１０ー4Ｔｏｒｒの条件のＡｒ雰囲気中で１５分間イオ
ンミリングを行い不必要なｉ型ＧａＮ層、ｎ型ＧａＮ
層、ｉ型Ｇａ0.8 ＩｎO.2 Ｎ層を除去した。次に、再度
スピンコーターを用いて２５００ｒｐｍ、３０ｓｅｃの
条件でレジストを塗布し、９０℃のクリーンオーブン中
で３０分間プレベークした。ベーク後、フォトマスクを
用いてＵＶ露光し、現像した。ついで、加速電圧５００
Ｖ、圧力２×１０ー4Ｔｏｒｒの条件のＡｒ雰囲気中で１
３分間イオンミリングを行い不必要なｉ型ＧａＮ層、ｎ
型ＧａＮ層を除去した。さらに再度スピンコーターを用
いて２５００ｒｐｍ、３０ｓｅｃの条件でレジストを塗
布し、９０℃のクリーンオーブン中で３０分間プレベー
クした。ベーク後、フォトマスクを用いてＵＶ露光し、
現像した。続いて、イオンミリングを用い不必要なｉ型
ＧａＮ層を除去した。その後、アセトンでレジストを除
去した。ついで、管状炉にセットして１０ｃｃ／ｍｉｎ
のアンモニアガス流中で５００℃、３０分間の熱処理を
行った。さらに、スピンコーターを用いて２５００ｒｐ
ｍ、３０ｓｅｃの条件でレジストを塗布し、９０℃のク
リーンオーブン中で３０分間プレベークした。ベーク
後、ｎ型ＧａＮ層およびｎ型Ｇａ0.8 Ｉｎ0.2 Ｎ層の電
極形成用のマスクを用いてＵＶ露光し、現像した。続い
て、真空蒸着機に装着し２×１０ー6Ｔｏｒｒの真空中で
Ａｌ金属を０．２μｍの厚さで真空蒸着した。その後、
アセトンでリフトオフして電極パターンを形成した。つ
いで、ｉ型ＧａＮ層およびｉ型Ｇａ 0.8 Ｉｎ0.2 Ｎ層の
電極形成用のマスクを用いてＵＶ露光し、現像した。続
いて、真空蒸着機に装着し２×１０ー6Ｔｏｒｒの真空中
でＡｕ金属を０．２μｍの厚さで真空蒸着した。その
後、アセトンでリフトオフして電極パターンを形成し
た。この作製した発光素子をＡｒ流中で３００℃で１時
間加熱処理を行い、素子チップの構造を完成させた。作
製した素子チップの側面図および上面図を図９（ａ）、
（ｂ）に示す。On the opposite surface of the substrate surface on which the light emitting layer is formed
2 x 10 using the vacuum deposition method-6Al in a vacuum of Torr
Is deposited to a thickness of 3000 Å to form a reflective film.
I made it. Then, using a spin coater on the light emitting layer, 2
Apply the resist under the conditions of 500 rpm, 30 sec,
Pre-bak for 30 minutes in a 90 ° C clean oven
It was After baking, U using a mask for element pattern formation
V exposed and developed. Then, acceleration voltage 500V, pressure
2 x 10-4Ion millimeter for 25 minutes with Ar under Torr conditions
Element pattern formation was performed. Then aceto
The resist was removed by using a mask. Then spin the spin again
Register at 2500 rpm for 30 sec.
Stroke applied, clean oven at 90 ℃ for 30 minutes
Prebaked. After baking, UV using a photomask
Exposed and developed. Then, acceleration voltage 500V, pressure 2
× 10-4Ion for 15 minutes in Ar atmosphere under Torr conditions
Unnecessary i-type GaN layer and n-type GaN
Layer, i-type Ga0.8InO.2The N layer was removed. Then again
2500 rpm for 30 seconds using a spin coater
Apply the resist under the conditions and in a 90 ° C clean oven
And prebaked for 30 minutes. After baking, use a photomask
UV exposed and developed. Then, acceleration voltage 500
V, pressure 2 × 10-41 in Ar atmosphere under Torr conditions
Ion milling is performed for 3 minutes to remove unnecessary i-type GaN layer, n
The type GaN layer was removed. Use the spin coater again
The resist at 2500 rpm for 30 seconds.
Cloth and pre-bake in a 90 ° C clean oven for 30 minutes
I'm sorry. After baking, UV exposure using a photomask,
Developed. Then, using ion milling, unnecessary i-type
The GaN layer was removed. Then, remove the resist with acetone.
I left. Then, set it in a tubular furnace and set it to 10 cc / min.
Heat treatment at 500 ℃ for 30 minutes in the ammonia gas flow
went. Furthermore, 2500 rpm using a spin coater
The resist is applied under the conditions of m, 30 sec and 90 ° C.
Prebaked for 30 minutes in a lean oven. Bake
Then, the n-type GaN layer and the n-type Ga0.8In0.2N layer power
UV exposure was performed using a mask for pole formation and development was performed. Continued
And attach it to the vacuum vapor deposition machine, and 2 x 10-6In the vacuum of Torr
Al metal was vacuum deposited to a thickness of 0.2 μm. afterwards,
The electrode pattern was formed by lifting off with acetone. One
Then, the i-type GaN layer and the i-type Ga 0.8In0.2N layers
UV exposure was performed using a mask for electrode formation and development. Continued
And attach it to the vacuum vapor deposition machine, 2 × 10-6Torr in vacuum
Au metal was vacuum-deposited to a thickness of 0.2 μm. That
After that, lift off with acetone to form an electrode pattern.
It was The manufactured light emitting device was heated at 300 ° C. for 1 hour in Ar flow.
A heat treatment was performed for a period of time to complete the structure of the element chip. Product
A side view and a top view of the manufactured element chip are shown in FIG.
It shows in (b).

【００３７】各チップのカッティングはダイシングソー
を用いて行った。１素子チップは１ｍｍ×１ｍｍとし
た。このうちの１チップを取り出し反射膜側をＰｂーＳ
ｎハンダでリード部材にダイボンディングした。その後
ｎ型ＧａＮ層およびｎ型Ｇａ0. 8 Ｉｎ0.2 Ｎ層の電極を
ワイヤーボンディング装置を用いて３０μｍφＡｕ線で
接続した。さらにｉ型ＧａＮ層電極とリード部材、ｉ型
Ｇａ0.8 Ｉｎ0.2 Ｎ層電極とリード部材とをワイヤーボ
ンディング装置を用いて３０μｍφＡｕ線で接続した。
上記の方法で作製した発光素子を透明エポキシ樹脂で封
止して、図１０に示すようなＬＥＤを作製した。The cutting of each chip was performed using a dicing saw. One element chip was 1 mm × 1 mm. Take one chip out of these and put Pb-S on the reflective film side.
It was die-bonded to the lead member with n solder. Followed by the electrodes of the n-type GaN layer and n-type Ga 0. 8 In 0.2 N layer connected by 30μmφAu line using a wire bonding device. Further, the i-type GaN layer electrode and the lead member, and the i-type Ga 0.8 In 0.2 N layer electrode and the lead member were connected with a 30 μmφAu wire using a wire bonding device.
The light emitting device manufactured by the above method was sealed with a transparent epoxy resin to manufacture an LED as shown in FIG.

【００３８】同様の方法で１００個のＬＥＤを作製した
ところ、９５個のＬＥＤで発光が確認された。このＬＥ
Ｄの発光強度を測定したところリード部材６６とリード
部材６７では１０Ｖ，１８ｍＡで４０ｍｃｄの青色の発
光が、リード部材６６とリード部材６８では、８Ｖ、２
０ｍＡで６０ｍｃｄの緑色の発光が観測された。When 100 LEDs were manufactured by the same method, light emission was confirmed with 95 LEDs. This LE
When the emission intensity of D was measured, the lead member 66 and the lead member 67 emitted blue light of 10 V and 40 mcd at 18 mA, and the lead member 66 and the lead member 68 emitted 8 V, 2
A green emission of 60 mcd was observed at 0 mA.

【００３９】[0039]

【発明の効果】本発明は絶縁性基板上に発光層を形成し
たプレーナ型の素子チップ構造において、同一平面内に
形成された全ての電極を該電極数と同じ数に分割したリ
ード部材にワイヤーボンディング法によりワイヤ−でお
のおの接続することで、安定した性能のＬＥＤを供給す
ることが可能になる。According to the present invention, in a planar type device chip structure in which a light emitting layer is formed on an insulating substrate, all the electrodes formed in the same plane are divided into the same number as the number of the electrodes, and the lead members are wired. By connecting each with a wire by the bonding method, it becomes possible to supply an LED with stable performance.

【図面の簡単な説明】[Brief description of drawings]

【図１】 薄膜作製に用いたＭＢＥ装置の概略図であ
る。FIG. 1 is a schematic diagram of an MBE apparatus used for thin film production.

【図２】 （ａ）〜（ｈ） ＬＥＤの作製工程を示した
断面図である。2A to 2H are cross-sectional views showing a manufacturing process of an LED.

【図３】 本発明による方法で作製したＬＥＤの断面図
である。FIG. 3 is a cross-sectional view of an LED manufactured by the method according to the present invention.

【図４】 ネット状電極を形成した発光素子の上面図で
ある。FIG. 4 is a top view of a light emitting device having a net-shaped electrode.

【図５】 クシ状電極を形成した発光素子の上面図であ
る。FIG. 5 is a top view of a light emitting device having a comb-shaped electrode.

【図６】 ミアンダ状電極を形成した発光素子の上面図
である。FIG. 6 is a top view of a light emitting device having a meandering electrode formed thereon.

【図７】 （ａ） 実施例１で作製した素子チップの断
面図である。 （ｂ） 実施例１で作製した素子チップの上面図であ
る。7 (a) is a cross-sectional view of the element chip manufactured in Example 1. FIG. (B) It is a top view of the element chip produced in Example 1.

【図８】 実施例１で作製したＬＥＤの断面図である。FIG. 8 is a cross-sectional view of the LED manufactured in Example 1.

【図９】 （ａ） 実施例２で作製した素子チップの断
面図である。 （ｂ） 実施例２で作製した素子チップの上面図であ
る。9 (a) is a cross-sectional view of an element chip manufactured in Example 2. FIG. (B) It is a top view of the element chip produced in Example 2.

【図１０】 実施例２で作製したＬＥＤの断面図であ
る。FIG. 10 is a cross-sectional view of the LED manufactured in Example 2.

【図１１】 発光層の形成されていない側の基板面に金
属層が形成された構造からなる発光素子の断面図であ
る。FIG. 11 is a cross-sectional view of a light emitting device having a structure in which a metal layer is formed on a surface of a substrate on which a light emitting layer is not formed.

【図１２】 従来の方法で作製されたＬＥＤの断面図で
ある。FIG. 12 is a cross-sectional view of an LED manufactured by a conventional method.

【図１３】 従来の方法で作製されたフリップチップ方
式のＬＥＤの断面図である。FIG. 13 is a cross-sectional view of a flip-chip type LED manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

１ 真空容器 ２ 蒸発用ルツボ ３ 蒸発用ルツボ ４ 蒸発用ルツボ ５ 基板加熱ホルダー ６ 基板 ７ ガスセル ８ ガス導入管 ９ 流量調節バルブ １０ クライオパネル １１ コールドトラップ １２ 油拡散ポンプ １３ 油回転ポンプ １４ ｐ型あるいはｉ型半導体層 １５ ｎ型半導体層 １６ 絶縁性基板 １７ 金属反射膜 １８ レジスト １９ ｎ型半導体層電極 ２０ ｐ型あるいはｉ型半導体層電極 ２１ リード部材（１） ２２ リード部材（２） ２３ 金属ワイヤー ２４ 素子チップ ２５ ＬＥＤ ２６ 電極 ２７ ｉ型ＧａＮ層電極 ２８ ｎ型ＧａＮ層電極 ２９ ｉ型ＧａＮ層 ３０ ｎ型ＧａＮ層 ３１ サファイア基板 ３２ Ａｌ反射膜 ３３ リード部材（３） ３４ リード部材（４） ３５ Ａｕワイヤー ３６ ＧａＮ発光素子チップ ３７ ＧａＮＭＩＳ型ＬＥＤ ３８ ｉ型Ｇａ0.8 Ｉｎ0.2 Ｎ層電極 ３９ ｎ型ＧａＮ層およびｎ型Ｇａ0.8 Ｉｎ0.2 Ｎ層電
極 ４０ ｉ型Ｇａ0.8 Ｉｎ0.2 Ｎ層 ４１ ｎ型Ｇａ0.8 Ｉｎ0.2 Ｎ層 ４２ リード部材（５） ４３ リード部材（６） ４４ リード部材（７） ４５ ＧａＮ、Ｇａ0.8 Ｉｎ0.2 Ｎ発光素子チップ ４６ ２色発光ＬＥＤ ４７ リード部材（８） ４８ リード部材（９） ４９ リードフレーム ５０ ミラー面 ５１ リード部材（１０） ５２ リード部材（１１）1 Vacuum Container 2 Evaporating Crucible 3 Evaporating Crucible 4 Evaporating Crucible 5 Evaporating Crucible 5 Substrate Heating Holder 6 Substrate 7 Gas Cell 8 Gas Introducing Tube 9 Flow Control Valve 10 Cryopanel 11 Cold Trap 12 Oil Diffusion Pump 13 Oil Rotary Pump 14 p-type or i Type semiconductor layer 15 n type semiconductor layer 16 insulating substrate 17 metal reflective film 18 resist 19 n type semiconductor layer electrode 20 p-type or i type semiconductor layer electrode 21 lead member (1) 22 lead member (2) 23 metal wire 24 element Chip 25 LED 26 Electrode 27 i-type GaN layer electrode 28 n-type GaN layer electrode 29 i-type GaN layer 30 n-type GaN layer 31 sapphire substrate 32 Al reflective film 33 lead member (3) 34 lead member (4) 35 Au wire 36 GaN light emitting device chip 37 GaN MIS type LED 8 i-type Ga 0.8 In 0.2 N layer electrode 39 n-type GaN layer and n-type Ga 0.8 In 0.2 N layer electrode 40 i-type Ga 0.8 In 0.2 N layer 41 n-type Ga 0.8 In 0.2 N layer 42 lead member (5) 43 Lead member (6) 44 Lead member (7) 45 GaN, Ga 0.8 In 0.2 N light emitting element chip 46 two-color light emitting LED 47 lead member (8) 48 lead member (9) 49 lead frame 50 mirror surface 51 lead member (10) ) 52 Lead member (11)

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 絶縁性基板上にｎ型半導体層、ｐ型およ
びｉ型半導体層から選ばれた２種以上の組み合わせから
なる発光層を少なくとも一つ有し、かつ半導体層の所定
の部位に発光層に電圧を印加するための電極を有するプ
レーナ構造の素子チップにおいて、電極とリード部材と
の接続配線が全てワイヤ−である構造を特徴とする発光
ダイオード。1. An insulating substrate having at least one light-emitting layer composed of a combination of two or more selected from an n-type semiconductor layer, a p-type semiconductor layer and an i-type semiconductor layer, and at a predetermined portion of the semiconductor layer. A light emitting diode having a planar structure element chip having electrodes for applying a voltage to a light emitting layer, characterized in that all connection wirings between electrodes and lead members are wires.
JP22262792A 1992-08-21 1992-08-21 Light-emitting diode Withdrawn JPH0669546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22262792A JPH0669546A (en) 1992-08-21 1992-08-21 Light-emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22262792A JPH0669546A (en) 1992-08-21 1992-08-21 Light-emitting diode

Publications (1)

Publication Number Publication Date
JPH0669546A true JPH0669546A (en) 1994-03-11

Family

ID=16785420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22262792A Withdrawn JPH0669546A (en) 1992-08-21 1992-08-21 Light-emitting diode

Country Status (1)

Country Link
JP (1) JPH0669546A (en)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945963A (en) * 1995-07-31 1997-02-14 Eiko Eng:Kk Gan based semiconductor device
JPH09298313A (en) * 1996-04-30 1997-11-18 Rohm Co Ltd Semiconductor light emitting element and manufacture thereof
JPH1041254A (en) * 1996-07-24 1998-02-13 Sony Corp Ohmic electrode and forming method thereof
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JP2001119075A (en) * 1996-12-27 2001-04-27 Nichia Chem Ind Ltd Light emitting diode and led display comprising it
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JP2000036619A (en) * 1998-05-13 2000-02-02 Toyoda Gosei Co Ltd Iii nitride compound semiconductor light emitting element
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US7355212B2 (en) 2000-06-30 2008-04-08 Kabushiki Kaisha Toshiba Light emitting element
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