JPH0669546A - Light-emitting diode - Google Patents

Light-emitting diode

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Publication number
JPH0669546A
JPH0669546A JP22262792A JP22262792A JPH0669546A JP H0669546 A JPH0669546 A JP H0669546A JP 22262792 A JP22262792 A JP 22262792A JP 22262792 A JP22262792 A JP 22262792A JP H0669546 A JPH0669546 A JP H0669546A
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Japan
Prior art keywords
light
electrode
type
layer
lead member
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Withdrawn
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JP22262792A
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Japanese (ja)
Inventor
Hiromasa Gotou
Hideaki Imai
秀秋 今井
広将 後藤
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Asahi Chem Ind Co Ltd
旭化成工業株式会社
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Application filed by Asahi Chem Ind Co Ltd, 旭化成工業株式会社 filed Critical Asahi Chem Ind Co Ltd
Priority to JP22262792A priority Critical patent/JPH0669546A/en
Publication of JPH0669546A publication Critical patent/JPH0669546A/en
Application status is Withdrawn legal-status Critical

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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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Abstract

PURPOSE:To obtain an LED provided with a good light-emitting characteristic by using a wire bonding method when all electrodes for an element chip using an insulating substrate are connected to individual lead members. CONSTITUTION:Individual chips are cut by using a dicing saw, one chip is taken out, the side of a reflection film 32 is die-bonded to a lead member 43 by using a Pb-Sn solder, electrodes for an n-type GaN layer 30 and an n-type Ga0.8In0.2N layer 41 are connected by 30mum phi Au wires 35 by using a wire bonding apparatus. Then, an i-type GaN layer electrode 27 is connected to a lead member 44 and an i-type Ga0.8In0.2N layer electrode 38 is connected to a lead member 43 respectively by 30mum phi Au wires 35 by using the wire bonding apparatus, and a manufactured light-emitting element 46 is sealed with a transparent epoxy resin. Consequently, all electrodes formed inside the same plane can be connected individually to lead members divided into the same number as the number of electrodes by using a wire bonding method. Thereby, an LED whose performance is stable can be supplied.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、絶縁性基板を用いた発光素子チップをリードフレームに実装した発光ダイオードに関する。 The present invention relates to a light emitting diode light-emitting device chip mounted on the lead frame using an insulating substrate.

【0002】 [0002]

【従来の技術】従来、実用化されている発光ダイオード(LED)に実装されている素子チップはGaAs、I Conventionally, device chip mounted on the practical use has been that light emitting diode (LED) is GaAs, I
nPなどの導電性基板を用いていることから正負の電極部は素子チップの表と裏に形成されていた。 Positive and negative electrode portions since it is a conductive substrate such as nP had been formed on the front and back of the element chip. 従来のリードフレームに素子チップを実装し樹脂で封止したLED Implement element chip to conventional lead frame LED encapsulated with the resin
の断面図を図12に示す。 It shows a cross-sectional view in FIG. 12. 上述したように導電性基板を用いて作製した素子チップは表と裏に電極を有する構造をとっているため、この素子チップ24をリードフレーム49に接着する場合には片方の電極をリードフレームのミラー部50にハンダあるいは導電性ペーストにより接着し、もう片方の電極はワイヤーボンディング法によってリード部材48に接続するような構造をとっていた。 Since element chip fabricated using the conductive substrate as described above which has a structure having electrodes on front and back, the one of the electrodes of the lead frame in the case of bonding the element chip 24 to the lead frame 49 bonded by solder or conductive paste to the mirror unit 50, the other one of the electrodes was taking a structure to connect the lead member 48 by a wire bonding method. このリード部材47、48に素子チップを実装した後にエポキシ樹脂などで封止してLED25を形成していた。 This was to form a LED25 sealed with an epoxy resin after mounting the device chip to the lead member 47, 48. 近年では、透明絶縁性基板を用いたフリップチップ方式の素子チップによるLEDが提案されている。 In recent years, LED by element chip flip-chip method using a transparent insulating substrate it has been proposed. (特開平4ー10670)この透明絶縁性基板上に発光層を形成した発光素子チップを用いて作製したLE (JP-4-10670) LE manufactured using the light-emitting element chips to form a light-emitting layer on the transparent insulating substrate
Dとしては、図13に示すような構造であり、素子チップ24の電極19、20は正負の電極とも発光層側に位置し、リード部材51、52との接続は、ハンダあるいは導電性ペーストにより行われていた。 The D, a structure as shown in FIG. 13, electrodes 19 and 20 of the element chip 24 is located on the light emitting layer side with positive and negative electrodes, the connection between the lead members 51 and 52, by solder or conductive paste It was done.

【0003】 [0003]

【発明が解決しようとする課題】上述したように発光素子チップに導電性基板を用いたときには、基板に電流を流すことができるので、正負の電極は基板側に1つ、発光層側に1つ形成することが可能である。 When using a conductive substrate on the light emitting device chip as described above [0004] Since current can flow to the substrate, the positive and negative electrodes one on the substrate side, the light emitting layer side 1 One can be formed. リードフレームに接続する際には基板側の電極をリード部材にダイボンディングし、発光層側の電極は他のリード部材にワイヤーボンディングするという方法でLEDを作製していた。 And die bonding an electrode on the substrate side to the lead member is to connect to the lead frame, the light emitting layer side of the electrode was fabricated an LED in a way that wire bonding to other lead member. しかし、透明絶縁性基板を素子チップに用いた場合には、発光層側に正負一対の電極を有するフリップチップ方式をとるため、素子チップとリード部材の接続は上述した接続方法をとることができない。 However, when a transparent insulating substrate in the element chip, to take a flip chip method with a pair of positive and negative electrodes in the light emitting layer side, the connection element chip and the lead member can not take the connection methods described above . このため、発光層側に形成された2種の電極をリードフレームに接続するためには、2本のリード部材の素子チップとの接続面は平坦にして、この平坦面に素子チップの電極面をハンダあるいは導電性ペーストにより接着する工程をとる。 Therefore, in order to connect the two electrodes formed on the light emitting layer side to the lead frame, the connection surface between the element chip of the two lead members in the flat, the electrode surfaces of the device chip to the flat surface the take process of bonding by solder or conductive paste.
しかしこの方法では、同一面内に2種の電極を形成しなければならないため1mm角以下の素子チップサイズでは電極サイズは200μm以下としなけらばならず、ハンダあるいは導電性ペーストによる接着工程において2 However, in this method, the electrode size must kicked such as 200μm or less in 1mm angle following elements chip size because they must form the two electrodes in the same plane, in the bonding step by solder or conductive paste 2
種の電極部が接触してしまうという問題があった。 Electrode portions species there is a problem that contact. また、素子チップサイズに対するハンダあるいは導電性ペーストにより接着される電極面積が広いため、より効率よく発光させるために用いられるミアンダ状、ネット状あるいはクシ状のような複雑な電極パターンを形成することはできなかった。 Moreover, since a wide electrode area to be bonded by soldering or conductive paste for device chip size, to form a meander shape, complex electrode patterns, such as a net-shaped or comb-shaped to be used in order to more efficiently luminescence could not. あるいは、1つのLEDから2色以上の発光を得る多色発光ダイオードを作製する場合には、3カ所以上の電極部を必要とするため電極面積はさらに小さくしなければならず、ハンダあるいは導電性ペーストによる電極とリード部材との接続は不可能であった。 Alternatively, in the case of manufacturing a multi-colored LED to obtain the emission of two or more colors from one LED electrode area requires a electrode portion of the above three locations must be further reduced, solder or conductive connection between the electrode and the lead member according paste was impossible. また、従来提案されているLEDに用いる発光素子チップは透明な絶縁性基板を使用しており、発光した光を基板を通して取り出す構造のために基板による光の吸収があるため発光効率が低下するという問題点もあった。 The light-emitting device chip used in the conventional proposed LED is using a transparent insulating substrate, that the light emission efficiency due to absorption of light by the substrate to the structure to extract emitted light through the substrate is reduced there was also a problem.

【0004】本発明は、前記問題点を解決して簡単に再現よく発光特性の良好なLEDを提供しようとするものである。 [0004] The present invention is intended to provide good LED of easily reproduced well emission characteristics to solve the above problems.

【0005】 [0005]

【課題を解決するための手段】本発明者らは前記問題点を解決するために鋭意研究を重ねた結果、絶縁性基板を用いた素子チップの全ての電極と各リード部材とを接続する際にワイヤーボンディング法を用いることで、再現よく良好な特性を有するLEDを得ることができるようになったものである。 The present inventors have SUMMARY OF THE INVENTION As a result of extensive studies to solve the above problems, when connecting all the electrodes and the lead member of the element chip using an insulating substrate to the use of the wire bonding method, in which it has become possible to obtain an LED with good reproducibility good characteristics.

【0006】すなわち、本発明は絶縁性基板上にn型半導体層、p型およびi型半導体層から選ばれた2種以上の組み合わせからなる発光層を少なくとも一つ有し、かつ半導体層の所定の部位に発光層に電圧を印加するための電極を有するプレーナ構造の素子チップにおいて、電極とリード部材との接続が全てワイヤ−である構造を特徴とする発光ダイオードを提供するものである。 Namely, given the present invention has at least one light emitting layer comprising a combination of two or more selected from n-type semiconductor layer, p-type and i-type semiconductor layer on an insulating substrate, and the semiconductor layer in device chip of a planar structure having electrodes for the site of application of voltage to a light-emitting layer, the connection between the electrode and the lead member are all wire - is intended to provide a light emitting diode, wherein of structure.

【0007】本発明における絶縁性基板としては表面が平坦であればよく、透明でもよく不透明でもよい。 [0007] As the insulating substrate in the present invention may be any surface is flat may well opaque be transparent. 絶縁性基板として代表的なものとしては、サファイア(Al Typical examples as the insulating substrate, a sapphire (Al
2 2 O 3 )、石英(SiO 2 )、酸化マグネシウム(Mg 3), quartz (SiO 2), magnesium oxide (Mg
O)、チタン酸ストロンチウム(SrTiO 3 )、フッ化カルシウム(CaF 2 )、フッ化マグネシウム(Mg O), strontium titanate (SrTiO 3), calcium fluoride (CaF 2), magnesium fluoride (Mg
2 )、酸化チタン(TiO 2 )などがある。 F 2), titanium oxide (TiO 2), and the like. しかし、 But,
基板上に直接形成する半導体薄膜の格子定数がこの絶縁性基板の格子定数に極力合ったたものを用いるのがよい。 It is preferable to use those as much as possible matches to the lattice constant of the lattice constant is the insulating substrate of the semiconductor thin film to be formed directly on the substrate. この絶縁性基板と基板上に直接形成する半導体薄膜との格子不整合は10%以下とするのが好ましく、さらに好ましくは5%以下とするのがよい。 It is preferred to this lattice mismatch between the insulating substrate and the semiconductor thin film formed directly on the substrate than 10%, more preferably from to 5% or less. このために該透明絶縁性基板を所定の角度だけオフしたものを使用することも好ましいものである。 It is also preferable to use a material obtained by turning off the transparent insulating substrate by a predetermined angle for this. 例えばGaNの場合はサファイアR面を9.2゜オフした基板を用いることが好ましいものとなる。 For example, in the case of GaN it is assumed preferable to use a substrate which is 9.2 ° off the sapphire R face. また絶縁性基板と半導体薄膜との格子不整合が非常に大きい場合には、この絶縁性基板と半導体薄膜との間にバッファ層を設けてもよい。 In the case the lattice mismatch with the insulating substrate and the semiconductor thin film is very large, a buffer layer may be provided between the insulating substrate and the semiconductor thin film. バッファ層としてはアモルファス状の物質、例えばAlN、Ga The buffer layer amorphous material, for example AlN, Ga
N、Si、SiCなど、あるいは単結晶物質として、例えばAlN、ZnO、SiC等を設けることができる。 N, Si, etc. SiC, or a single crystalline material, for example AlN, ZnO, may be provided SiC.

【0008】本発明において絶縁性基板上に発光層を形成する方法としては、MBE(Molecular B As a method for forming a luminescent layer on an insulating substrate in the present invention, MBE (Molecular B
eam Epitaxy)法、CBE(Chemica eam Epitaxy) method, CBE (Chemica
lBeam Epitaxy)法、MOMBE(Met lBeam Epitaxy) method, MOMBE (Met
al Organic MBE)法、CVD(Chem al Organic MBE) method, CVD (Chem
ical Vapour Deposition)法、 ical Vapour Deposition) method,
MOCVD(Metal Organic CVD)法等の半導体成長装置を用いることができる。 You can use the semiconductor growth apparatus such as MOCVD (Metal Organic CVD) method. 上記した薄膜作製方法により絶縁性基板上に発光層を形成する。 Forming a light emitting layer on an insulating substrate by a thin film manufacturing method described above. この発光層はMIS構造、pn接合を有するシングルヘテロ構造およびダブルヘテロ構造、あるいは量子井戸構造あるいは超格子構造のいずれであってもよい。 The light emitting layer MIS structure, single hetero structure and double heterostructure having a pn junction or may be any of a quantum well structure or a superlattice structure.

【0009】本発明における発光層とは、n型半導体層、p型およびi型半導体層から選ばれた2種以上の組み合わせからなる発光層のことである。 [0009] The light-emitting layer in the present invention, n-type semiconductor layer refers to a p-type and i-type semiconductor composed of two or more kinds selected from layer-emitting layer. また、これらの発光層を形成する半導体は、IIIーV族化合物半導体、IIーVI族化合物半導体のどちらでもよいが、I The semiconductor for forming these light emitting layer, III over V compound semiconductor, but may be either of II over VI compound semiconductor, I
IIーV族化合物半導体であるGaN系半導体は絶縁性基板であるサファイア、CaF 2 、MgO等に結晶性の良好な薄膜の成長が可能であり特に好ましいものである。 GaN-based semiconductor is a II over V group compound semiconductor is one and particularly preferably can be sapphire, crystalline good film growth of the CaF 2, MgO or the like as an insulating substrate.

【0010】本発明での発光素子チップは絶縁性基板を用いるために発光層側の同一平面内に正負一対の電極を形成する必要があり、発光層のエッチングを行わなければならない。 [0010] The light-emitting element chip in the present invention must form a pair of positive and negative electrodes in the light emitting layer side of the same plane in order to use an insulating substrate, it must be performed to etch the light-emitting layer. この発光素子チップ作製のために行うエッチング方法としては発光層の種類により、ウエットエッチング法、ドライエッチング法のどちらを用いてもよい。 The type of the light-emitting layer as an etching method for performing for the light emitting device chip manufacturing, the wet etching method may be used either dry etching method. エッチング後に熱処理を行うことも好ましいことであり、この熱処理を行うことによりエッチングにより受けた膜質の劣化を回復することができ、界面抵抗を下げて低電圧で発光に必要な電流を得ることができる。 And it is also preferable to perform the heat treatment after the etching, it is possible to recover the deterioration of the film quality received by etching by performing the heat treatment, it is possible to obtain a current necessary to lower the interfacial resistance to emit light at a low voltage . 熱処理を行う装置としては管状炉、ランプアニール炉等の雰囲気を制御できる炉であればよい。 The tubular furnace as an apparatus for performing heat treatment may be a furnace capable of controlling the atmosphere in the lamp annealing furnace.

【0011】本発明における発光素子チップの電極形成方法としては、MBE法、真空蒸着法、電子ビーム蒸着法、スパッタ法等がある。 [0011] As an electrode forming method of the light emitting device chip according to the present invention, MBE method, a vacuum deposition method, an electron beam deposition method, a sputtering method, or the like. 電極材料としてはn型半導体とp型あるいはi型半導体それぞれにオーミック接触が得られるものが好ましく、金属単体でもよく、2種以上の金属を混合して合金化したものを用いてもよい。 Preferably those ohmic contact is obtained to the respective n-type semiconductor and the p-type or i-type semiconductor as an electrode material may be a single metal, or may be used after alloying a mixture of two or more metals. このオーミック接触を得るための条件はn型半導体側の電極としては半導体の仕事関数よりも小さな仕事関数を有する金属がよく、p型半導体側の電極としては半導体の仕事関数よりも大きな仕事関数を有する金属を用いるのがよい。 The ohmic contact to obtain the conditions n-type semiconductor side as the electrode often metal having a work function smaller than the work function of the semiconductor, the electrodes of the p-type semiconductor side work function greater than the work function of the semiconductor it is preferable to use a metal having. 例えば、IIIーV族化合物半導体であるGaN For example, GaN is III over V compound semiconductor
の場合には、n型GaN層にはAl、In、Ti、P In the case of, the n-type GaN layer Al, an In, Ti, P
b、Sb、Nb、Zr、Mn等を電極に用いることがよく、i型あるいはp型GaN層にはAu、Pt、Ge、 b, Sb, Nb, Zr, often used Mn or the like to the electrode, i-type or the p-type GaN layer Au, Pt, Ge,
As、Ir、Re、Rh、Pd、Ni、W等を電極に用いることで良好なオーミック接触が得られる。 As, Ir, Re, Rh, Pd, Ni, good ohmic contact by using W or the like to the electrode is obtained. また、このオーミック電極形成後に素子チップをリード部材に接着する際に、接着性を向上させるためや、電極部の耐熱性を向上するためにオーミック電極上にNi、Ti、A Further, when bonding the device chip after the ohmic electrode formed in the lead member, and to improve adhesion, Ni in order to improve the heat resistance of the electrode portion on the ohmic electrodes, Ti, A
u、W等の金属を積層することも好ましい。 u, it is also preferable to laminate a metal such as W.

【0012】電極形成後にAr、N 2 、He等の不活性ガス流中あるいは該半導体の構成元素を含むガス流中で半導体の分解温度以下で熱処理することも好ましく、これにより電極と半導体との界面抵抗を下げることが可能になり、良好なダイオード特性を得ることができる。 [0012] Ar after electrode formation, it is also preferred to heat treatment in the following semiconductor decomposition temperature in a gas stream comprising N 2, the He inert gas stream or the semiconductor constituent element such as, thereby the electrode and the semiconductor it is possible to lower the interfacial resistance, it is possible to obtain a good diode characteristics. 本発明におけるLEDは電極側から光を取り出す構造をとるため電極形状を工夫することが好ましい。 It is preferable to devise the electrode shape for LED takes a structure in which light is extracted from the electrode side in the present invention. 発光した光を電極側から取り出すために該p型あるいはi型半導体層の表面を覆う電極面積は50%以下、好ましくは40 Electrode area covering the surface of the p-type or i-type semiconductor layer in order to extract emitted light from the electrode side is 50% or less, preferably 40
%以下、さらに好ましくは30%以下とすることである。 % Or less, more preferably to 30% or less. そのために、電極はp型あるいはi型半導体層の表面上にパターンを形成することが必要で、パターンの例としては図4に示すネット状、図5に示すクシ状、図6 Therefore, the electrode is necessary to form a pattern on the surface of the p-type or i-type semiconductor layer, a net-like as shown in FIG. 4 as an example of the pattern, a comb-shaped as shown in FIG. 5, FIG. 6
に示すミアンダ状とすることができるが、さらにはこれらのパターンの組合せや渦状、島状等があるが、特にこれらに限定されるものではない。 Can be a meander shape shown in further combination and spiral of these patterns, there are islands or the like, but is not particularly limited thereto. 電極の幅と電極間の距離はp型あるいはi型半導体層の電気抵抗や印加する電圧の大きさにより変えればよく、電極の幅を狭くして、 The distance between the width of the electrode and the electrode may be changed by the magnitude of the voltage of the electrical resistance and the application of the p-type or i-type semiconductor layer, by narrowing the width of the electrode,
電極間の距離を小さくすれば、光の取り出し効率が向上する。 By reducing the distance between electrodes, the light extraction efficiency is improved. 電極の幅をサブミクロン程度とし、かつ電極間もサブミクロン程度の間隔とすることによりp型あるいはi型半導体層の表面に均一に電圧を印加するとともに光の取り出し効率も大きくすることができる。 The width of the electrode is submicron, and the inter-electrode can also be greater extraction efficiency of light with uniformly apply a voltage to the surface of the p-type or i-type semiconductor layer by a distance of submicron.

【0013】また、本発明においては、基板上の発光層が形成されていない面上に図11に示すような少なくとも一種の金属反射層を設けることも好ましいものとなる。 [0013] In the present invention, becomes also preferable to provide at least one metal reflecting layer as shown in FIG. 11 on the surface not emitting layer on the substrate is formed. この金属層はn型半導体層およびp型あるいはi型半導体層を組み合わせてなる発光層において発光して基板を通して出てくる光を反射して電極側から取り出すことを可能とするものである。 The metal layer is to allow the taking out reflected light and emitted in the light-emitting layer comprising a combination of n-type semiconductor layer and a p-type or i-type semiconductor layer emerges through the substrate from the electrode side. これにより、発光素子の光の取り出し効率を高めることができる。 This can increase the light extraction efficiency of the light-emitting element. 金属反射層として使われる材料としてはAl、In、Cu、Ag、P As materials used as the metal reflecting layer is Al, In, Cu, Ag, P
t、Ir、Pd、Rh、W、Mo、Ti、Ni等の金属の単体あるいはそれらの合金がある。 t, is Ir, Pd, Rh, W, Mo, Ti, simple substance or an alloy of these metals such as Ni. 金属反射層は、一層だけでもよいが、リードフレームに実装するときの耐ハンダ性、耐熱性や耐ボンディング性を向上せしめるためにNi、W、Mo等の高融点の金属を積層した構造とすることも好ましいものとなる。 Metal reflective layer is may be only more, and solder resistance were Ni in order of improving heat resistance and bonding properties, W, a refractory metal such as Mo stacked structure when mounted on the lead frame it also becomes preferable.

【0014】本発明におけるリードフレームの形状は素子チップをリード部材に固定するための接続部と、素子チップのそれぞれの部位に電圧を印加するための各電極と他のリード部材をワイヤ−によってそれぞれ接続できる構造であればよく発光素子チップの電極形状により変えることができる。 [0014] The shape of the lead frame of the present invention is a connecting portion for fixing the device chip to the lead member, the electrodes and the other lead member for applying a voltage to the respective portions of the element chip wire - respectively by it can be varied by the electrode shape of the well-emitting element chips if the structure can be connected. リードフレームは発光を有効に集光するためにミラー面を設けることが望ましい。 Lead frame, it is desirable to provide a mirror surface in order to effectively focus the light emission.

【0015】本発明における発光素子チップをリード部材にダイボンディングを行う際の接着の材料としては、 [0015] The light-emitting element chip in the present invention as a material of the adhesive when performing the die-bonded to the lead member,
一般的に使われているものが使用できる。 Those that are commonly used can be used. 例えばAuーSi、PbーSn合金系ハンダや、このハンダに少量のBi、Sb、Ag、Cd、Zn、In等の金属を添加したもの、BiにNa、Tl、Cd、Sn、Pb等を添加し合金化したもの、InにZn、Cd、Sn、Bi等を添加し合金化したもの、GaにAg、Zn、Sn、In For example Au over Si, and Pb over Sn alloy based solder, a small amount of Bi in the solder, Sb, Ag, Cd, Zn, obtained by adding a metal such as In, Na to Bi, Tl, Cd, Sn, and Pb, etc. added that alloyed material obtained by adding alloyed Zn, Cd, Sn, and Bi and the like in an in, Ag to Ga, Zn, Sn, an in
等を添加し合金化したもの、Au、Al、In、Ag等の金属あるいはAg、Au、Cu等を含んだ導電性ペーストがある。 Those added by alloying or the like, there is Au, Al, an In, a metal such as Ag or Ag, Au, conductive paste containing Cu. 素子チップとリード部材とを接着する方法としては、従来のダイボンディング装置を用いた方法がある。 As a method for bonding the device chip and the lead member, there is a method using a conventional die bonding apparatus. 即ち、接着層を素子チップの該電極部、もしくはリード部材の素子チップの接着面に蒸着法、塗布法あるいはメッキ法等により形成した後、該電極部と該リード部材を密着させながらリード部材を接着材料の融点以上に加熱して接着を行う。 That is, the electrode portion of the adhesive layer element chip, or method deposited on the adhesion surface of the element chip lead member, was formed by a coating method or a plating method or the like, the lead member while in close contact with the electrode portion and the lead member performing bonding by heating above the melting point of the adhesive material.

【0016】また本発明における発光素子チップの電極部とリード部材を配線する際にはワイヤーボンダー法を用いることが特徴である。 [0017] When routing electrode portions and the lead member of the light-emitting element chip in the present invention is characterized by using a wire bonder method. ダイボンディング法により素子チップをリード部材に固定した後に、ワイヤーボンディング装置にセットして加熱および、あるいは超音波を印加することにより電極部とリード部材とを接続する。 After fixing the device chip to the lead member by the die bonding method to connect the electrode portions and the lead member by applying heat and or ultrasonic wave was set in a wire bonding apparatus.
このとき用いるワイヤーの材料としては、Au、Ag、 As a material of the wire used in this case, Au, Ag,
Cu、Al等の金属、Au−Si、Al−Si、Al− Cu, metal such as Al, Au-Si, Al-Si, Al-
Mg、Al−Si−Mg、Al−Ni等の合金があり、 Mg, Al-Si-Mg, there are alloys such as Al-Ni,
どの材料を使用するかは発光素子チップの電極部の材料やワイヤ−ボンディングの作業性を考慮して選べばよい。 Or use which material the material of the electrode portion of the light emitting device chip or wire - may be selected in consideration of the workability of the bonding. なかでも、AuやAl−Siが作業性がよいということで好ましい。 Among them, Au or Al-Si preferred that the good workability. ワイヤ−の太さは、発光素子チップの電極部の大きやワイヤ−ボンディングの作業性を考慮して選べばよく、通常は20〜300μmφである。 Wire - The thickness of the size Ya of the electrode portion of the light emitting device chip wire - may be selected in consideration of the workability of the bonding, usually a 20~300Myuemufai. また、ワイヤ−の酸化を防ぐために、不活性ガス中でワイヤ−ボンディングを行うことも好ましい方法である。 Further, the wire - in order to prevent oxidation of the wire in an inert gas - it is also a preferred method for performing bonding.

【0017】本発明における封止材料としては発光素子チップの発光波長範囲での光透過率が80%以上の透光性材料を使用することが好ましい。 [0017] As the sealing material in the present invention is preferred to use a light-transmitting material of the light transmittance of 80% or more in the emission wavelength range of the light-emitting element chips. この透光性材料としては、メタクリル系樹脂、エポキシ系樹脂、ポリカーボネート系樹脂、ポリスチレン系樹脂、ポレオレフィン系樹脂あるは低融点ガラスの少なくとも一種を使用することができる。 As the light-transmitting material, methacrylic resins, epoxy resins, polycarbonate resins, polystyrene resins, polyolefin-based resin may use at least one low-melting glass. 封止方法としては、たとえば所望形状の金型にこれらの透光性材料の原料または加熱溶融体を注形して金型内で固化させる方法を用いることができる。 As the sealing method, it is possible to use a method, for example solidify in the desired shape mold into and Casting the starting material or heat melt these translucent material mold. この固化の方法として、モノマーやオリゴマーの熱または光による重合固化、加熱溶融体では冷却固化、化学反応等を挙げることができる。 As a method for this hardening, polymerization solidification of the monomer or oligomer by heat or light, cooled and solidified in heating the melt, it can be given a chemical reaction or the like. この透光性材料には必要があれば、色調調整や視感度補正のための色素、顔料、蛍光体などを、樹脂の安定化のための酸化防止剤、安定剤、 If necessary for this transparent material, the dye for color tone adjustment or visibility correction, pigments and phosphors, antioxidants for stabilization of resin, stabilizers,
成形加工のための潤滑剤、滑剤を添加することも可能である。 Lubricants for the molding, it is also possible to add a lubricant.

【0018】以上説明した各方法を用いて作製したLE [0018] was prepared using each method described above LE
Dの例を図3に示すが、これに限定されるものではない。 Examples of D shown in FIG. 3, but not limited thereto. 素子チップ24は、絶縁基板上にn型半導体層、p Element chip 24, n-type semiconductor layer on an insulating substrate, p
型およびi型半導体から選ばれた2種以上の組み合わせからなる発光層を少なくとも一つ有し、かつそれぞれの半導体層の所定の部位に、発光層に電圧を印加するための電極を有するプレ−ナ構造の素子チップである。 The light-emitting layer composed of two or more combinations selected from the mold, and the i-type semiconductor having at least one, and a predetermined portion of each of the semiconductor layers, pre having an electrode for applying a voltage to a light-emitting layer - it is an element chip of Na structure. この素子チップの基板面あるいはリ−ド部材22の接着面に蒸着法でハンダを蒸着した後、リ−ド部材22の接着面に素子チップ24を載せハンダの融点以上に加熱して接着する。 Substrate surface or Li of the element chip - after depositing the solder deposition on the adhesion surface of the de member 22, re - adhered by heating to above the melting point of the solder carrying the device chip 24 on the bonding surface of the de member 22. その後、各電極とそれぞれのリ−ド部材とをワイヤ−ボンディング法を用いて金線により接続する。 Thereafter, each electrode and each of the re - connected by gold wire using a bonding method - wire and de member. その後、透光性材料により封止してLED25を作製する。 Thereafter, to prepare the LED25 sealed with translucent material.

【0019】以下、一例として絶縁性基板としてAl 2 [0019] Hereinafter, as an insulating substrate as an example Al 2
3を使用してMBE法を用いてGaN薄膜を成膜しL Use O 3 forming a GaN thin film by using the MBE method L
EDを作製する方法について説明するが、とくにこれに限定されるものではない。 Method for manufacturing the ED be described, but is not particularly limited thereto. 装置としては、図1に示すような真空容器1内に、蒸発用ルツボ(クヌードセンセル)2、3および4、ガスセル7、基板加熱ホルダー5 The apparatus, the vacuum chamber 1 as shown in FIG. 1, the evaporation crucible (Knudsen cells) 2, 3 and 4, the gas cell 7, a substrate heating holder 5
を備えたガスソースMBE装置を使用した。 Using gas source MBE apparatus equipped with.

【0020】蒸発用ルツボ2にはGa金属を入れ、基板面において10 13 〜10 19 /cm 2・secになる温度に加熱した。 [0020] The evaporation crucible 2 containing a Ga metal was heated to a temperature at which 10 13 ~10 19 / cm 2 · sec in the substrate surface. アンモニアの導入にはガス導入管8を用い、アンモニアをガスセル7内から基板6に直接吹き付けるようにした。 The introduction of ammonia was blown directly with a gas inlet tube 8, the ammonia from the gas cell 7 to the substrate 6. アンモニアの導入量は基板表面において10 16 〜10 20 /cm 2・secになるように供給した。 The introduction amount of ammonia was fed so that 10 16 ~10 20 / cm 2 · sec at the substrate surface. 蒸発用ルツボ3にはIn、Al等を入れ、所定の組成の化合物半導体、および所定のキャリア密度を有する半導体となるように温度および時間を制御して成膜を行なう。 In the evaporation crucible 3 placed or Al, a film is formed by controlling the temperature and time such that the semiconductor having a compound semiconductor, and a predetermined carrier density of a given composition. 蒸発用ルツボ4にはMg、Zn、Be、Sb、S The evaporation crucible 4 Mg, Zn, Be, Sb, S
i、Ge、C、Sn、Hg、As、P等を入れ、所定の供給量になるように温度および供給時間を制御することによりドーピングを行ない、n型およびi型あるいはp i, Ge, C, Sn, Hg, As, put P or the like, subjected to doping by controlling the temperature and supply time to a predetermined supply amount, n-type and i-type or p
型半導体層を成膜する。 The formation of the type semiconductor layer.

【0021】基板6にはサファイアR面を使用し、20 [0021] using a sapphire R-plane to the substrate 6, 20
0〜900℃に加熱した。 0 to 900 was heated to ℃. サファイアR面基板は、オフ角が0.8度以下のものが好ましい。 Sapphire R-plane substrate is off-angle is preferably from 0.8 degrees. まず、基板6を真空容器1内で750℃で加熱した後、各ルツボを所定の成長温度に設定し、まず蒸発用ルツボ3を開き、0.1 First, after the substrate 6 was heated at 750 ° C. in the vacuum chamber 1, set each crucible to a predetermined growth temperature, first open the evaporation crucible 3, 0.1
〜30オングストローム/secの成長速度で0.05 At a growth rate of 30 angstroms / sec 0.05
〜2μmの厚みのn型GaN薄膜を作製する。 Manufacturing an n-type GaN thin film having a thickness of ~2Myuemu. さらにその後、Znをチャージした蒸発用ルツボ4のシャッターを開き、0.1〜30オングストローム/secの成長速度で0.01〜1μmの厚みでi型あるいはp型Ga Thereafter, opening the shutter of the evaporation crucible 4 was charged with Zn, in 0.01~1μm thickness at a growth rate of 0.1 to 30 Å / sec i-type or p-type Ga
N薄膜を成膜して発光層を形成する。 By forming a N thin to form a luminescent layer. この成膜時には常にガスセルを加熱し基板表面にアンモニアを供給する。 The constantly supplying ammonia to the heated substrate surface gas cell at the time of film formation.

【0022】以上のような方法で成膜した発光層を有するGaN薄膜を用いてLEDを作製する工程を図2 [0022] A process of manufacturing an LED using a GaN thin film having a light-emitting layer formed in the above manner 2
(a)から図2(h)にしたがって説明する。 (A) from that described with reference to FIG. 2 (h). 真空蒸着法を用いてAl 23側に金属反射膜17を蒸着する(a)。 Depositing a metal reflective film 17 on Al 2 O 3 side by a vacuum evaporation method (a). GaN薄膜表面にレジストを塗布する。 A resist is applied to the GaN thin film surface. レジストの膜厚はエッチングしたいGaN薄膜の厚みによって変えればよく0.1〜3μmとするのが好ましい。 Resist film thickness is preferably as well 0.1~3μm be changed by the thickness of the GaN film to be etched. スピンコーターの条件は2500rpm、30secである。 Conditions of the spin coater is 2500rpm, is 30sec. 塗布後に90℃に加熱されたクリーンオーブン内で30分間プレベークする(b)。 Prebaking for 30 minutes in a clean oven heated to 90 ° C. after application (b). その後、素子パターン形成用マスクを用いてUV露光・現像を行った(c)。 This was followed by UV exposure and development using a device pattern forming mask (c).
Arをガスとして用いてイオンミリング法によりi層あるいはp層のGaN薄膜14を除去する(d)。 The GaN thin film 14 of the i layer or the p layer is removed by ion milling using Ar as the gas (d). イオンミリング終了後、アセトンを用いてレジストを除去する。 After completion of the ion milling, the resist is removed using acetone.

【0023】なお、各工程でのイオンミリングを行う時間はエッチングを行う膜厚によって決めることができる。 [0023] The time to perform the ion milling in each step can be determined by the thickness to be etched. 以上の工程の後、管状炉内に試料をセットしてアンモニアを雰囲気として500℃で30分間熱処理した。 After the above step, ammonia sets the sample was heat treated for 30 minutes at 500 ° C. As the atmosphere in a tubular furnace.
熱処理後、再度レジストを塗布し、プレベークを行い、 After the heat treatment, the re-resist is applied, performs a pre-baking,
続いてn層電極形成用マスクを用いてUV露光・現像を行った後(e)、真空蒸着法によりn型GaN層15の電極としてAlを3000オングストロームの厚さに蒸着し、リフトオフにより電極パターン19を形成した(f)。 After UV exposure and development using a n-layer electrode forming mask followed (e), Al was deposited as an electrode of the n-type GaN layer 15 by vacuum evaporation to a thickness of 3000 Å, the electrode pattern by a lift-off 19 was formed (f). ついで再度レジストを塗布し、プレベークを行い、i層電極形成用マスクを用いてUV露光・現像を行った後(g)、真空蒸着法によりp型あるいはi型Ga Then coated with a resist again, it performs prebaked, after UV exposure and development using i-layer electrode formation mask (g), p-type or i-type Ga by vacuum evaporation
N層14の電極としてAuを3000オングストロームの厚さに蒸着し、リフトオフにより電極パターン20を形成した(h)。 Au as the electrode of the N layer 14 is deposited to a thickness of 3000 Å, to form an electrode pattern 20 by the lift-off (h). その後、Ar流中で300℃、1時間の加熱処理を行った。 Thereafter, 300 ° C. in Ar stream was subjected to heat treatment for 1 hour.

【0024】以上のようにして作製した発光素子チップの金属反射膜をハンダによりリード部材22に接着し、 [0024] The thus the metal reflection film of the light-emitting element chip prepared by the solder adhered to the lead member 22,
n型GaN層、i型GaN層の電極をワイヤーボンダー装置を用いて30μmφAu線23でそれぞれリード部材21、リード部材22にボンディングした。 n-type GaN layer, i-type, respectively an electrode of the GaN layer at 30μmφAu line 23 by a wire bonder lead member 21 was bonded to the lead member 22. その後、 after that,
発光素子チップを透明エポキシ樹脂によりモールディングを施し、図3に示す様な5mmφLED25を作製した。 Subjected to molding the light emitting device chip by a transparent epoxy resin, to prepare a 5mmφLED25 such as shown in FIG.

【0025】 [0025]

【実施例】以下,実施例によりさらに詳細に説明する。 EXAMPLES Hereinafter, will be explained in further detail by way of Examples.

【0026】 [0026]

【実施例1】絶縁性基板としてAl 23 R面を使用し、MBE法によりGaN薄膜を成膜し、ミアンダ状の電極構造を有する素子チップを用いてLEDを作製した例について説明する。 EXAMPLE 1 using the Al 2 O 3 R plane as the insulating substrate, forming a GaN thin film by the MBE method, for example of manufacturing an LED will be described with reference to the device chip having a meander shaped electrode structure. 図1に示すような真空容器1内に、蒸発用ルツボ2、4、ガスセル7、および基板加熱ホルダー5、さらにガスセル7にガスを供給するためのガス導入管8を備えたMBE装置を用いた。 Into the vacuum container 1 as shown in FIG. 1, the evaporation crucible for 2,4, gas cell 7 and a substrate heating holder 5, using the MBE apparatus equipped with a gas introduction pipe 8 for supplying the gas to the further gas cell 7 .

【0027】蒸発用ルツボ2にはGa金属を入れ、10 [0027] containing a Ga metal is in the evaporation crucible 2, 10
50℃に加熱した。 It was heated to 50 ℃. ガスとしてはアンモニアを使用し、 As the gas using ammonia,
ガス導入管8を通してガスセル7に5cc/minの速度で供給した。 It was fed at a rate of 5 cc / min to the gas cell 7 through the gas inlet tube 8. アンモニアガスは基板6に直接供給するような構造とした。 Ammonia gas was structured to supply directly to the substrate 6. 基板6としては、オフ角が0.5度のサファイアR面を使用する。 As the substrate 6, the off angle is to use a sapphire R face of 0.5 degrees. 真空容器内の圧力は、成膜時において2×10 -6 Torrであった。 The pressure in the vacuum chamber was 2 × 10 -6 Torr during film formation.

【0028】まず、基板6を900℃で30分間加熱し、ついで750℃の温度に保持し成膜を行う。 Firstly, the substrate 6 is heated for 30 minutes at 900 ° C., followed by a holding deposited at a temperature of 750 ° C.. 成膜はアンモニアを300℃に加熱したガスセル7から供給しながらGaのルツボのシャッターを開けて行い、1.5 Deposition is carried out by opening the shutter of the crucibles Ga while supplying the gas cell 7 heated ammonia to 300 ° C., 1.5
オングストローム/secの成膜速度で膜厚0.5μm Angstrom / sec film thickness of 0.5μm at a deposition rate of
のn型GaN薄膜を作製した。 The n-type GaN thin film was produced. さらにMgをチャージして300℃に保たれた蒸発用ルツボ4のシャッターを開けMgドープのGaN薄膜を1.5オングストローム/ Further charging the Mg and a GaN thin film of Mg-doped opening the shutter of the evaporation crucible 4 maintained at 300 ° C. and 1.5 Å /
secの成膜速度で膜厚0.05μmの厚さで成膜して発光層を形成した。 To form a light-emitting layer was deposited at a sec deposition rate in thickness of film thickness 0.05 .mu.m. この作製した薄膜のRHEEDパターンはストリーク状で結晶性および平坦性が良好であり、抵抗を測定したところ、10MΩ以上の抵抗があり絶縁状態であった。 RHEED pattern of the produced thin film has good crystallinity and flatness in streak When the resistivity was measured to be insulated has 10MΩ or more resistors.

【0029】発光層が形成されている基板面の反対面に真空蒸着法を用いて2×10 ー6 Torrの真空中でAl [0029] In using a vacuum deposition method on the opposite surfaces of the substrate surface on which the light-emitting layer is formed 2 × 10 over 6 Torr in vacuum Al
を3000オングストロームの厚みで蒸着し反射膜を形成した。 Was to form a deposited reflective film with a thickness of 3000 Angstroms. 続いて発光層上にスピンコーターを用いて25 Then using a spin coater on the light emitting layer 25
00rpm、30secの条件でレジストを塗布し、9 00rpm, resist is applied under the conditions of 30sec, 9
0℃のクリーンオーブン中で30分間プレベークした。 0 was pre-baked in a clean oven for 30 minutes ℃.
ベーク後、素子パターン形成用のマスクを用いてUV露光し、現像した。 After baking, and UV exposure using a mask for element patterned and developed. 続いて、加速電圧500V、圧力2× Subsequently, the acceleration voltage 500V, pressure 2 ×
10 ー4 Torrの条件のArで15分間イオンミリングを行い素子パターン形成を行った。 10 @ 4 Torr conditions Ar in element patterning is performed for 15 minutes ion milling was performed. その後、アセトンを用いてレジストを除去した。 Thereafter, the resist was removed with acetone. 次に、再度スピンコーターを用いて2500rpm、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 Next, a resist is applied 2500 rpm, the condition of 30sec using a spin coater again, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、i層除去用のマスクを用いてU After baking using a mask for the i-layer removal U
V露光し、現像した。 And V exposure, was developed. 続いて、加速電圧500V、圧力2×10 ー4 Torrの条件のAr雰囲気中で1分間イオンミリングを行い不必要なi層を除去した。 Subsequently, the acceleration voltage 500V, to remove unnecessary i layer for 1 minute ion milling in Ar atmosphere under a pressure of 2 × 10 over 4 Torr. その後、アセトンでレジストを除去した。 Thereafter, the resist was removed with acetone. 次いで、管状炉にセットして10cc/minのアンモニアガス流中で500 Then set in a tubular furnace in an ammonia gas stream of 10 cc / min 500
℃、30分間の熱処理を行った。 ℃, heat treatment was carried out for 30 minutes. さらに、スピンコーターを用いて2500rpm、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 Furthermore, 2500 rpm using a spin coater, a resist is applied under the conditions of 30 sec, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、n型GaN層の電極形成用のマスクを用いてUV露光し、現像した。 After baking, and UV exposure using a mask for forming an electrode of the n-type GaN layer, and developed. 続いて、真空蒸着機に装着し2×10 ー6 Torrの真空中でAl金属を0.2μmの厚さで真空蒸着した。 Subsequently, it was vacuum deposited to a thickness of 0.2μm the Al metal in a vacuum of 2 × 10 over 6 Torr mounted in a vacuum deposition machine. その後、アセトンでリフトオフして電極パターンを形成した。 Then, to form an electrode pattern by lift-off in acetone. ついで、i型GaN層の電極形成用のマスクを用いてUV露光し、現像した。 Then UV exposed using a mask for forming an electrode of the i-type GaN layer, and developed. 続いて、真空蒸着機に装着し2×10 ー6 Tor Subsequently, it mounted on a vacuum deposition device 2 × 10 over 6 Tor
rの真空中でAu金属を0.2μmの厚さで真空蒸着した。 Was vacuum deposited to a thickness of 0.2μm and an Au metal in vacuum at r. その後、アセトンでリフトオフして電極パターンを形成した。 Then, to form an electrode pattern by lift-off in acetone. この作製した発光素子をAr流中で300℃ The fabricated light-emitting element in Ar stream 300 ° C.
で1時間加熱処理を行い、ミアンダ状の電極構造を有する素子チップを完成させた。 In for one hour heat treatment, thereby completing the device chip having a meander shaped electrode structure. 作製した素子チップの側面図および上面図を図7(a)、(b)に示した。 Figure 7 a side view and a top view of the fabricated device chip (a), as shown in (b).

【0030】各チップのカッティングはダイシングソーを用いて行った。 [0030] cutting of each chip was carried out using a dicing saw. 1素子チップは0.5mm×0.5m 1 element chip 0.5 mm × 0.5 m
mとした。 It was m. このうちの1チップを取り出し反射膜側をA The reflective film side A retrieves this of 1 chip
gペーストによりリード部材にダイボンディングした。 It was die-bonded to the lead member by g paste.
さらにn型GaN層電極、i型GaN層電極とそれぞれのリード部材とをワイヤーボンディング装置を用いて3 Further n-type GaN layer electrode, and an i-type GaN layer electrode and each of the lead member by a wire bonding device 3
0μmφAu線で接続した。 Connected by 0μmφAu line. 上記の方法で作製した発光素子を透明エポキシ樹脂で封止して図8に示すようなL As shown in FIG. 8 to seal the light emitting element manufactured by the above method with a transparent epoxy resin L
EDを作製した。 To prepare the ED.

【0031】同様の方法で100個のLEDを作製したところ、99個のLEDで発光が確認された。 [0031] were manufactured 100 LED in a similar manner, the light emission was confirmed in 99 the LED. このLE The LE
Dの発光強度を測定したところ8V,20mAで60m It was measured the emission intensity of the D 8V, 60m at 20mA
cdであり、青色の発光が観測された。 A cd, blue light was observed.

【0032】 [0032]

【比較例1】実施例1と同様の方法によりAl 23基板上に成膜した発光層を有するGaN薄膜を用いて素子化を行った。 [Comparative Example 1 was carried out element by using the GaN thin film having a light-emitting layer formed on the Al 2 O 3 substrate in the same manner as in Example 1. 素子作製過程も実施例1と同様の方法により行い、n型GaN層、i型GaN層の両電極ともAg Device fabrication process also performed in the same manner as in Example 1, n-type GaN layer, both electrodes of the i-type GaN layer Ag
ペーストにより、リード部材にダイボンディングを行った後、透明エポキシ樹脂で封止してLEDを作製した。 The paste, after die bonding the lead member, an LED was formed by sealing with a transparent epoxy resin.
同様の方法で100個のLEDを作製したところ、Ag It was manufactured 100 LED in a similar manner, Ag
ペーストにより正負の電極がつながってしまい、9個のLEDでしか発光するものは得られなかった。 Would led positive and negative electrodes by paste was obtained which emits light only at nine the LED.

【0033】 [0033]

【実施例2】絶縁性基板としてAl 23 R面を使用し、MBE法によりGa 1ーx In x N薄膜を成膜し2色発光のLEDを作製した例について説明する。 EXAMPLE 2 Using the Al 2 O 3 R plane as the insulating substrate, MBE method for example of manufacturing the LED of Ga 1 over x an In x N thin film was deposited 2-color light emission will be described by. 図2に示すような真空容器1内に、蒸発用ルツボ2、3、4、ガスセル7、および基板加熱ホルダー5、さらにガスセル7にガスを供給するためのガス導入管8を備えたMBE Into the vacuum container 1 as shown in FIG. 2, with the evaporation crucible 2, 3, 4, the gas cell 7 and the substrate heating holder 5, the gas introduction pipe 8 for supplying gas further gas cell 7, MBE
装置を用いた。 The apparatus was used.

【0034】蒸発用ルツボ2にはGa金属を入れ、10 [0034] containing a Ga metal is in the evaporation crucible 2, 10
20℃に加熱し、蒸着用ルツボ3にはIn金属を入れ1 It was heated to 20 ° C., placed In metal for deposition crucible 3 1
000℃に加熱した。 000 was heated to ℃. ガスとしてはアンモニアを使用し、ガス導入管8を通してガスセル7に5cc/min As the gas using ammonia, 5 cc / min to the gas cell 7 through the gas inlet tube 8
の速度で供給した。 It was fed at a rate of. アンモニアガスは基板6に直接供給するような構造とした。 Ammonia gas was structured to supply directly to the substrate 6. 基板6としては、オフ角が0. As the substrate 6, the off-angle is 0.
5度のサファイアR面を使用する。 Using the 5 degrees of the sapphire R-plane.

【0035】真空容器内の圧力は、成膜時において2× The pressure in the vacuum vessel, 2 × during film formation
10 -6 Torrであった。 Was 10 -6 Torr. まず、基板6を900℃で3 First, 3 of the substrate 6 at 900 ° C.
0分間加熱し、ついで700℃の温度に保持し成膜を行う。 It was heated for 10 minutes, followed by a holding deposited at a temperature of 700 ° C.. 成膜はアンモニアを300℃に加熱したガスセル7 Gas cell film formation was heated ammonia to 300 ° C. 7
から供給しながらGaとInのルツボのシャッターを開けて行い、1.5オングストローム/secの成膜速度で膜厚0.5μm のn型Ga 0.8 In 0.2 N薄膜を作製した。 Performed by opening the shutter of the crucible of Ga and In with supplied to prepare a n-type Ga 0.8 In 0.2 N thin film thickness 0.5μm at a deposition rate of 1.5 Å / sec. さらにMgをチャージして300℃に保たれた蒸発用ルツボ4のシャッターを開けMgをドーピングしたi型Ga 0.8 In 0.2 N薄膜を1.5オングストローム/secの成膜速度で膜厚0.05μmの厚さで成膜して第1の発光層を形成した。 Furthermore by charging the Mg 300 ° C. was hold at a deposition rate of the Mg opening the shutter of the evaporation crucible 4 doped i-type Ga 0.8 In 0.2 N film of 1.5 Å / sec thickness 0.05μm of It was deposited at a thickness to form a first light-emitting layer. 次に基板温度を750℃に上げて30分間温度を安定させた後、Gaのルツボのシャッターを開けて1.5オングストローム/secの成長速度で膜厚0.5μmのn型GaN薄膜を成長し、さらにその上に蒸着ルツボ2および4のシャッターを開けてMgをドーピングしたi型GaN薄膜を1.5オングストローム/secの成長速度で膜厚0.05μmの厚さで成膜して第2の発光層を形成した。 Then After stabilizing for 30 minutes the temperature is raised at a substrate temperature of 750 ° C., at a growth rate of 1.5 Å / sec by opening the shutter of the crucibles Ga to grow a n-type GaN thin film having a film thickness of 0.5μm further on the deposition crucible 2 and the GaN thin film 1.5 Å / sec i-type doped with Mg opening the fourth shutter growth rate to a film thickness 0.05μm was formed to a thickness in a second of its to form a light-emitting layer.

【0036】発光層が形成されている基板面の反対面に真空蒸着法を用いて2×10 ー6 Torrの真空中でAl [0036] In using a vacuum deposition method on the opposite surfaces of the substrate surface on which the light-emitting layer is formed 2 × 10 over 6 Torr in vacuum Al
を3000オングストロームの厚さで蒸着し反射膜を形成した。 Was to form a deposited reflective film in a thickness of 3000 Angstroms. 続いて、発光層上にスピンコーターを用いて2 Then, using a spin coater on the light-emitting layer 2
500rpm、30secの条件でレジストを塗布し、 500rpm, a resist is applied under the conditions of 30sec,
90℃のクリーンオーブン中で30分間プレベークした。 It was pre-baked for 30 minutes in a clean oven of 90 ℃. ベーク後、素子パターン形成用のマスクを用いてU After baking, U using the mask element patterning
V露光し、現像した。 And V exposure, was developed. 続いて、加速電圧500V、圧力2×10 ー4 Torrの条件のArで25分間イオンミリングを行い素子パターン形成を行った。 Subsequently, the acceleration voltage 500V, the element pattern formation performed 25 min the ion milling in Ar conditions of the pressure 2 × 10 over 4 Torr was performed. その後、アセトンを用いてレジストを除去した。 Thereafter, the resist was removed with acetone. 次に、再度スピンコーターを用いて2500rpm、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 Next, a resist is applied 2500 rpm, the condition of 30sec using a spin coater again, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、フォトマスクを用いてUV After baking, UV using a photomask
露光し、現像した。 Exposed, and developed. 続いて、加速電圧500V、圧力2 Subsequently, the acceleration voltage 500V, pressure 2
×10 ー4 Torrの条件のAr雰囲気中で15分間イオンミリングを行い不必要なi型GaN層、n型GaN × 10 over 4 Torr unnecessary i-type GaN layer performs 15 min the ion milling in Ar atmosphere conditions, n-type GaN
層、i型Ga 0.8 In O.2 N層を除去した。 Layer was removed i-type Ga 0.8 In O.2 N layer. 次に、再度スピンコーターを用いて2500rpm、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 Next, a resist is applied 2500 rpm, the condition of 30sec using a spin coater again, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、フォトマスクを用いてUV露光し、現像した。 After baking, and UV exposure using a photomask, and then developed. ついで、加速電圧500 Then, the acceleration voltage 500
V、圧力2×10 ー4 Torrの条件のAr雰囲気中で1 V, in an Ar atmosphere at pressure conditions of 2 × 10 over 4 Torr 1
3分間イオンミリングを行い不必要なi型GaN層、n 3 minutes ion milling was carried out unnecessary i-type GaN layer, n
型GaN層を除去した。 To remove the type GaN layer. さらに再度スピンコーターを用いて2500rpm、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 2500rpm further again by using a spin coater, the resist was applied under the conditions of 30 sec, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、フォトマスクを用いてUV露光し、 After baking, and UV exposure using a photomask,
現像した。 It was developed. 続いて、イオンミリングを用い不必要なi型GaN層を除去した。 Followed by removal of unnecessary i-type GaN layer by ion milling. その後、アセトンでレジストを除去した。 Thereafter, the resist was removed with acetone. ついで、管状炉にセットして10cc/min Then, set in a tubular furnace to 10cc / min
のアンモニアガス流中で500℃、30分間の熱処理を行った。 500 ° C. in an ammonia gas stream, heat treatment was carried out for 30 minutes. さらに、スピンコーターを用いて2500rp In addition, 2500rp by using a spin coater
m、30secの条件でレジストを塗布し、90℃のクリーンオーブン中で30分間プレベークした。 m, a resist is applied under the conditions of 30 sec, and prebaked for 30 minutes in a clean oven at 90 ° C.. ベーク後、n型GaN層およびn型Ga 0.8 In 0.2 N層の電極形成用のマスクを用いてUV露光し、現像した。 After baking using a mask for forming electrodes of n-type GaN layer and n-type Ga 0.8 In 0.2 N layer was UV exposed and developed. 続いて、真空蒸着機に装着し2×10 ー6 Torrの真空中でAl金属を0.2μmの厚さで真空蒸着した。 Subsequently, it was vacuum deposited to a thickness of 0.2μm the Al metal in a vacuum of 2 × 10 over 6 Torr mounted in a vacuum deposition machine. その後、 after that,
アセトンでリフトオフして電極パターンを形成した。 To form an electrode pattern by lift-off in acetone. ついで、i型GaN層およびi型Ga Then, i-type GaN layer and i-type Ga 0.8 In 0.2 N層の電極形成用のマスクを用いてUV露光し、現像した。 And UV exposure using a mask for forming electrodes of 0.8 an In 0.2 N layer, and developed. 続いて、真空蒸着機に装着し2×10 ー6 Torrの真空中でAu金属を0.2μmの厚さで真空蒸着した。 Subsequently, was vacuum deposited to a thickness of 0.2μm and an Au metal in a vacuum of 2 × 10 over 6 Torr mounted in a vacuum deposition machine. その後、アセトンでリフトオフして電極パターンを形成した。 Then, to form an electrode pattern by lift-off in acetone. この作製した発光素子をAr流中で300℃で1時間加熱処理を行い、素子チップの構造を完成させた。 The fabricated light-emitting device for 1 hour heat treatment at 300 ° C. in an Ar stream, thus completing the structure of the element chip. 作製した素子チップの側面図および上面図を図9(a)、 Figure a side view and a top view of the fabricated device chip 9 (a),
(b)に示す。 It is shown in (b).

【0037】各チップのカッティングはダイシングソーを用いて行った。 The cutting of each chip was carried out using a dicing saw. 1素子チップは1mm×1mmとした。 1 device chip was 1 mm × 1 mm. このうちの1チップを取り出し反射膜側をPbーS Pb over S reflective film side retrieves this of 1 chip
nハンダでリード部材にダイボンディングした。 And die-bonded to the lead member with n soldering. その後n型GaN層およびn型Ga 0. 8 In 0.2 N層の電極をワイヤーボンディング装置を用いて30μmφAu線で接続した。 Followed by the electrodes of the n-type GaN layer and n-type Ga 0. 8 In 0.2 N layer connected by 30μmφAu line using a wire bonding device. さらにi型GaN層電極とリード部材、i型Ga 0.8 In 0.2 N層電極とリード部材とをワイヤーボンディング装置を用いて30μmφAu線で接続した。 Further i-type GaN layer electrode and the lead member, and a i-type Ga 0.8 In 0.2 N layer electrode and the lead member are connected by 30μmφAu line using a wire bonding device.
上記の方法で作製した発光素子を透明エポキシ樹脂で封止して、図10に示すようなLEDを作製した。 A light emitting element manufactured by the above method is sealed with transparent epoxy resin, an LED was formed as shown in FIG. 10.

【0038】同様の方法で100個のLEDを作製したところ、95個のLEDで発光が確認された。 [0038] was prepared 100 pieces of LED in a similar manner, the light emission was confirmed in 95 pieces of LED. このLE The LE
Dの発光強度を測定したところリード部材66とリード部材67では10V,18mAで40mcdの青色の発光が、リード部材66とリード部材68では、8V、2 D lead member 66 in the lead member 67 10V where the emission intensity was measured, and the emission of blue 40mcd at 18 mA, the lead member 66 and the lead member 68, 8V, 2
0mAで60mcdの緑色の発光が観測された。 Green light emission of 60mcd was observed at 0 mA.

【0039】 [0039]

【発明の効果】本発明は絶縁性基板上に発光層を形成したプレーナ型の素子チップ構造において、同一平面内に形成された全ての電極を該電極数と同じ数に分割したリード部材にワイヤーボンディング法によりワイヤ−でおのおの接続することで、安定した性能のLEDを供給することが可能になる。 The present invention exhibits the device chip structure of a planar type forming a luminescent layer on an insulating substrate, a wire all the electrodes formed on the same plane to the lead member divided into the same number as the number of the electrode the bonding method wires - in that each connecting, it is possible to supply the LED of stable performance.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 薄膜作製に用いたMBE装置の概略図である。 1 is a schematic view of a MBE apparatus used for thin film preparation.

【図2】 (a)〜(h) LEDの作製工程を示した断面図である。 Is a sectional view showing the FIG. 2 (a) ~ (h) LED manufacturing process.

【図3】 本発明による方法で作製したLEDの断面図である。 It is a cross-sectional view of an LED manufactured by the method according to the invention, FIG.

【図4】 ネット状電極を形成した発光素子の上面図である。 4 is a top view of a light emitting element formed of the net-like electrode.

【図5】 クシ状電極を形成した発光素子の上面図である。 5 is a top view of a light emitting element formed of the comb-shaped electrode.

【図6】 ミアンダ状電極を形成した発光素子の上面図である。 6 is a top view of the light-emitting element forming the meander-shaped electrode.

【図7】 (a) 実施例1で作製した素子チップの断面図である。 7 (a) is a sectional view of the device chips produced in Example 1. (b) 実施例1で作製した素子チップの上面図である。 (B) it is a top view of the device chips produced in Example 1.

【図8】 実施例1で作製したLEDの断面図である。 8 is a cross-sectional view of the LED produced in Example 1.

【図9】 (a) 実施例2で作製した素子チップの断面図である。 9 (a) is a sectional view of the device chips produced in Example 2. (b) 実施例2で作製した素子チップの上面図である。 (B) it is a top view of the device chips produced in Example 2.

【図10】 実施例2で作製したLEDの断面図である。 10 is a cross-sectional view of the LED produced in Example 2.

【図11】 発光層の形成されていない側の基板面に金属層が形成された構造からなる発光素子の断面図である。 11 is a cross-sectional view of a light emitting device comprising a metal layer on the substrate surface on the side not formed with the light-emitting layer was formed structure.

【図12】 従来の方法で作製されたLEDの断面図である。 12 is a cross-sectional view of a LED made in a conventional manner.

【図13】 従来の方法で作製されたフリップチップ方式のLEDの断面図である。 13 is a cross-sectional view of the LED flip chip method, which is produced by the conventional methods.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 真空容器 2 蒸発用ルツボ 3 蒸発用ルツボ 4 蒸発用ルツボ 5 基板加熱ホルダー 6 基板 7 ガスセル 8 ガス導入管 9 流量調節バルブ 10 クライオパネル 11 コールドトラップ 12 油拡散ポンプ 13 油回転ポンプ 14 p型あるいはi型半導体層 15 n型半導体層 16 絶縁性基板 17 金属反射膜 18 レジスト 19 n型半導体層電極 20 p型あるいはi型半導体層電極 21 リード部材(1) 22 リード部材(2) 23 金属ワイヤー 24 素子チップ 25 LED 26 電極 27 i型GaN層電極 28 n型GaN層電極 29 i型GaN層 30 n型GaN層 31 サファイア基板 32 Al反射膜 33 リード部材(3) 34 リード部材(4) 35 Auワイヤー 36 GaN発光素子チップ 37 GaNMIS型LED 1 vacuum chamber 2 the evaporation crucible 3 evaporation crucible 4 evaporation crucible 5 substrate heating holder 6 substrate 7 gas cell 8 gas introduction pipe 9 flow control valve 10 cryopanel 11 cold trap 12 an oil diffusion pump 13 oil rotary pump 14 p-type or i type semiconductor layer 15 n-type semiconductor layer 16 insulating substrate 17 the metal reflective layer 18 resist 19 n-type semiconductor layer electrode 20 p-type or i-type semiconductor layer electrode 21 lead member (1) 22 lead member (2) 23 metal wires 24 element chip 25 LED 26 electrodes 27 i-type GaN layer electrode 28 n-type GaN layer electrode 29 i-type GaN layer 30 n-type GaN layer 31 the sapphire substrate 32 Al reflective film 33 lead member (3) 34 lead member (4) 35 Au wire 36 GaN light-emitting element chips 37 GaNMIS type LED 8 i型Ga 0.8 In 0.2 N層電極 39 n型GaN層およびn型Ga 0.8 In 0.2 N層電極 40 i型Ga 0.8 In 0.2 N層 41 n型Ga 0.8 In 0.2 N層 42 リード部材(5) 43 リード部材(6) 44 リード部材(7) 45 GaN、Ga 0.8 In 0.2 N発光素子チップ 46 2色発光LED 47 リード部材(8) 48 リード部材(9) 49 リードフレーム 50 ミラー面 51 リード部材(10) 52 リード部材(11) 8 i-type Ga 0.8 In 0.2 N layer electrode 39 n-type GaN layer and n-type Ga 0.8 In 0.2 N layer electrode 40 i-type Ga 0.8 In 0.2 N layer 41 n-type Ga 0.8 In 0.2 N layer 42 lead member (5) 43 lead member (6) 44 lead members (7) 45 GaN, Ga 0.8 In 0.2 N light-emitting element chips 46 two-color light emitting LED 47 lead member (8) 48 lead member (9) 49 lead frame 50 mirror surfaces 51 lead member (10 ) 52 lead member (11)

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 絶縁性基板上にn型半導体層、p型およびi型半導体層から選ばれた2種以上の組み合わせからなる発光層を少なくとも一つ有し、かつ半導体層の所定の部位に発光層に電圧を印加するための電極を有するプレーナ構造の素子チップにおいて、電極とリード部材との接続配線が全てワイヤ−である構造を特徴とする発光ダイオード。 1. A n-type semiconductor layer on an insulating substrate, a light emitting layer composed of two or more combinations selected from p-type and i-type semiconductor layer comprises at least one, and a predetermined portion of the semiconductor layer in device chip of a planar structure having electrodes for applying a voltage to a light-emitting layer, the connection wiring between the electrode and the lead member for all wire - emitting diodes, characterized in a structure.
JP22262792A 1992-08-21 1992-08-21 Light-emitting diode Withdrawn JPH0669546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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JP22262792A JPH0669546A (en) 1992-08-21 1992-08-21 Light-emitting diode

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JPH0669546A true JPH0669546A (en) 1994-03-11

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Cited By (13)

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JPH0945963A (en) * 1995-07-31 1997-02-14 Eiko Eng:Kk Gan based semiconductor device
US6222204B1 (en) 1994-07-19 2001-04-24 Sharp Kabushiki Kaisha Electrode structure and method for fabricating the same
US6576930B2 (en) 1996-06-26 2003-06-10 Osram Opto Semiconductors Gmbh Light-radiating semiconductor component with a luminescence conversion element
US6592780B2 (en) 1996-09-20 2003-07-15 Osram Opto Semiconductors Gmbh Wavelength-converting casting composition and white light-emitting semiconductor component
US6613247B1 (en) 1996-09-20 2003-09-02 Osram Opto Semiconductors Gmbh Wavelength-converting casting composition and white light-emitting semiconductor component
JP2005079578A (en) * 2003-08-28 2005-03-24 Agilent Technol Inc Heat-conductivity-improved light emitting device assembly, system including the same, and method for improving heat conductivity
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
WO2007007634A1 (en) * 2005-07-08 2007-01-18 Nec Corporation Electrode structure, semiconductor device and methods for manufacturing those
JP2007081400A (en) * 2005-09-09 2007-03-29 Samsung Electro Mech Co Ltd Nitride semiconductor light emitting element
JP2007201046A (en) * 2006-01-25 2007-08-09 Kyocera Corp Compound semiconductor and light emitting element
US7355212B2 (en) 2000-06-30 2008-04-08 Kabushiki Kaisha Toshiba Light emitting element
US7786493B2 (en) 2006-01-06 2010-08-31 Sony Corporation Light emitting diode, method for manufacturing light emitting diode, integrated light emitting diode, method for manufacturing integrated light emitting diode, light emitting diode backlight, light emitting diode illumination device, light emitting diode display, electronic apparatus, electronic device, and method for manufacturing electronic device
JP2014209656A (en) * 1996-07-29 2014-11-06 日亜化学工業株式会社 Light emitting device and display device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222204B1 (en) 1994-07-19 2001-04-24 Sharp Kabushiki Kaisha Electrode structure and method for fabricating the same
US6429111B2 (en) 1994-07-19 2002-08-06 Sharp Kabushiki Kaisha Methods for fabricating an electrode structure
JPH0945963A (en) * 1995-07-31 1997-02-14 Eiko Eng:Kk Gan based semiconductor device
US6812500B2 (en) 1996-06-26 2004-11-02 Osram Opto Semiconductors Gmbh & Co. Ohg. Light-radiating semiconductor component with a luminescence conversion element
US6576930B2 (en) 1996-06-26 2003-06-10 Osram Opto Semiconductors Gmbh Light-radiating semiconductor component with a luminescence conversion element
JP2014209656A (en) * 1996-07-29 2014-11-06 日亜化学工業株式会社 Light emitting device and display device
US6613247B1 (en) 1996-09-20 2003-09-02 Osram Opto Semiconductors Gmbh Wavelength-converting casting composition and white light-emitting semiconductor component
US6592780B2 (en) 1996-09-20 2003-07-15 Osram Opto Semiconductors Gmbh Wavelength-converting casting composition and white light-emitting semiconductor component
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US7355212B2 (en) 2000-06-30 2008-04-08 Kabushiki Kaisha Toshiba Light emitting element
JP2005079578A (en) * 2003-08-28 2005-03-24 Agilent Technol Inc Heat-conductivity-improved light emitting device assembly, system including the same, and method for improving heat conductivity
JP2013110435A (en) * 2003-08-28 2013-06-06 Intellectual Discovery Co Ltd Light-emitting device/assembly having enhanced heat conductivity, system including the same and method of enhancing heat conductivity
WO2007007634A1 (en) * 2005-07-08 2007-01-18 Nec Corporation Electrode structure, semiconductor device and methods for manufacturing those
JP2007081400A (en) * 2005-09-09 2007-03-29 Samsung Electro Mech Co Ltd Nitride semiconductor light emitting element
US7786493B2 (en) 2006-01-06 2010-08-31 Sony Corporation Light emitting diode, method for manufacturing light emitting diode, integrated light emitting diode, method for manufacturing integrated light emitting diode, light emitting diode backlight, light emitting diode illumination device, light emitting diode display, electronic apparatus, electronic device, and method for manufacturing electronic device
JP2007201046A (en) * 2006-01-25 2007-08-09 Kyocera Corp Compound semiconductor and light emitting element

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