JP2004022774A - Semiconductor device and field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a contact layer used for a semiconductor device, such as the HJFET etc., that can obtain a low contact resistance without passing through any high-temperatrue annealing step. <P>SOLUTION: The ohmic-contacted contact layer of a hetero field effect transistor is constituted of a GaN layer 14 and an Al<SB>y</SB>N<SB>(0<y≤)</SB>layer 15 formed on the layer 14. Then ohmic electrodes 1 and 3 are formed on the contact layer. When the transistor is constituted in this way, the transistor can obtain a low contact resistance without passing through any high-temperature annealing step. In addition, since dependency of the contact resistance on the electrode material is low, the low contact resistance is obtained even when a thermally stable material, such as the WSi etc., having a high melting point is used as an electrode material. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a group III nitride semiconductor layer and an ohmic electrode which is in ohmic contact with the semiconductor layer, and a field effect transistor having the ohmic electrode.
[0002]
[Prior art]
FIG. 8 is a schematic cross-sectional view of a hetero-junction field effect transistor (HJFET) according to the related art. Such a prior art HJFET is reported, for example, by T. Egawa in International Electron Device Meeting Digest (IEDM 99-401 to 404) in 1999.
FIG. 8A shows a cross-sectional structure of a conventional HJFET. In this HJFET, sapphire is used as a substrate, and a GaN buffer layer 111 is formed on a sapphire substrate 110. A GaN channel layer 112 is formed on the GaN buffer layer 111, and an AlGaN electron supply layer 113 is formed thereon. On this electron supply layer 113, an n-type GaN layer 114 is formed. The source electrode 101 and the drain electrode 103 are formed in contact with the n-type GaN layer 114. These electrodes are in ohmic contact with the n-type GaN layer 114. In addition, a gate electrode 102 is formed in contact with the AlGaN supply layer 113 at a recess formed by removing a part of the n-type GaN layer 114 and the AlGaN electron supply layer 113. Has a Schottky contact.
FIG. 8B is an energy band diagram showing a conduction band energy distribution corresponding to the ohmic contact portion of FIG. 8A. The vertical axis indicates energy, and the horizontal axis indicates depth. A depletion layer spreads at the semiconductor interface in contact with the electrode, and a potential barrier for electrons is generated.
[0003]
[Problems to be solved by the invention]
In the semiconductor device having the above structure, since a high potential barrier exists when electrons move from the electrode to the semiconductor, it is difficult to obtain a source / drain electrode having low contact resistance. To reduce the contact resistance, it is effective to perform annealing at a high temperature of 650 ° C. or higher. However, when performing the high-temperature annealing, there is a problem that a great restriction is imposed on the process order. In addition, there is a problem that the electrode metal from which low resistance is obtained is limited to a material containing Al, and is therefore thermally unstable.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art. An object of the present invention is to provide a semiconductor device such as an HJFET which can obtain a low contact resistance without going through an annealing process at a high temperature. It is to be.
[0004]
[Means for Solving the Problems]
According to an embodiment of the present invention, there is provided a semiconductor device having a group III nitride semiconductor layer and an ohmic electrode in ohmic contact with the group III nitride semiconductor layer. is, GaN layer or an n-type _{Al u Ga 1-u} n layer (where, 0 <u ≦ 1) GaN layer or the n-type Toko _{Al u Ga 1-u Al} is formed on the n layer y _{Ga 1- y} N layer (where, 0 <y ≦ 1) is, the ohmic electrode is a semiconductor device characterized by being formed on the _Al y _{Ga 1-y} N layer, is provided.
[0005]
According to another aspect of the present invention, there is provided a channel layer, or an active layer including a channel layer and an electron supply layer, a gate electrode for controlling electron conductivity of the channel layer, a contact layer formed on the layer, and a source electrode and a drain electrode formed in contact with the contact layer, the contact layer, GaN layer or an n-type Al u _Ga 1-u _n layer (where 0 <u ≦ 1) and _Al y _{Ga 1-y} N layer formed thereon (where 0 <field effect transistor characterized by comprising from y ≦ 1) and, is provided.
[0006]
[Action]
With such a structure of the contact layer to be in ohmic contact, an ohmic electrode with low contact resistance can be obtained without going through a high-temperature annealing step. In this configuration, the contact resistance is less dependent on the electrode material, and a low contact resistance can be obtained even when a thermally stable high melting point material such as WSi is used as the electrode material.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the invention will be described with reference to examples.
(First embodiment)
A first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a schematic diagram of an HJFET according to this embodiment, and FIG. 1A shows a cross-sectional structure of the HJFET. This HJFET is formed on a substrate 10 such as sapphire. A buffer layer 11 made of a semiconductor layer is formed on a substrate 10. On this buffer layer 11, a GaN channel layer 12 is formed. An AlGaN electron supply layer 13 is formed on the channel layer, and an n-type GaN layer 14 is formed on the electron supply layer 13. The uppermost AlGaN layer 15 is formed on the n-type GaN layer 14. In addition, a source electrode 1 and a drain electrode 3 are formed in contact with the AlGaN layer 15, all of which are in ohmic contact. The AlGaN layer 15, the n-type GaN layer 14, and a part of the AlGaN electron supply layer 13 are removed, and a Schottky contact gate electrode 2 is formed in contact with the AlGaN supply layer 13 in a recess formed by the removal. ing.
[0008]
FIG. 1B is a characteristic diagram showing a conduction band energy distribution corresponding to the ohmic contact portion in FIG. The vertical axis indicates energy, and the horizontal axis indicates depth. Ohmic contacts in this embodiment is obtained by reaching the GaN layer 14 electrons in the electrode metal is transmitted through the _Al y _{Ga 1-y} N layer 15.
1 (b), the electrode - semiconductor interface of the potential barrier depends on the type of electrode metal and _Al y _{Ga 1-y} N Al composition y. _{Al y Ga 1-y N-} GaN conduction band energy difference is also determined by the Al composition y. The electric field of the Al y _Ga 1-y _N layer is due to the charge generated by piezoelectric polarization and spontaneous polarization, which is also determined by the Al composition y.
For electrons transmitted to the semiconductor from the _electrode, the thickness of the Al y _{Ga 1-y} N layer _is required to be less than the electron wavelength in Al _{y Ga 1-y.} The upper limit value of the thickness of the AlGaN layer determined by this is d ₁ (nm). _Further, it is necessary to GaN of conduction band energy at the interface of the Al y _{Ga 1-y} N layer and the GaN layer is below the Fermi level position, the lower limit of the thickness of the _Al y _{Ga 1-y} N from this condition are determined. This lower limit is d ₂ (nm).
[0009]
Here, h is Planck's constant (= 6.662617 × 10 ⁻³⁴ Js), π is pi (= 3.14159), m ₀ is electron mass (= 9.1095 × 10 ⁻³¹ kg), and ε ₀ is ε ₀ vacuum dielectric constant ^{(= 8.85418 × 10 -12 F /} m), q is the elementary charge ^{(= 1.60219 × 10 -19 C)} , m * is the electron effective mass in the _Al y _{Ga 1-y} N , [Phi _B is the Schottky barrier height, the dielectric constant of ε is _Al y _{Ga 1-y} N, △ Ec is the conduction band energy difference at the interface of the _Al y _{Ga 1-y} N and GaN, sigma is when the polarization charge since _{d 1} is consistent with the electron wavelength in _{Al y Ga 1-y} N,
d ₁ (nm) = h / 2π × (2m * m ₀ Φ _B ) ^-0.5 (1)
Can be written.
_Further, since the thickness of the _Al y _{Ga 1-y} N when the GaN conduction band energy at the interface of the Al y _{Ga 1-y} N layer and the GaN layer coincides with the Fermi level is _{d 2, Al} y Ga Assuming that the electric field strength in _1-yN is E,
qΦ _B -qd ₂ E = △ Ec (2)
Holds. Here, E = σ / (εε ₀ ) (3)
From the relationship,
d ₂ (nm) = εε ₀ × (qΦ _B − △ Ec) / qσ (4)
Is obtained.
[0010]
Anbasha (Ambacher) et the literature Journal of Applied Physics (J. Appl.), 85 vol., No. 6, according to pages _{3222, m *, Φ B,} ε, of △ Ec and σ The dependence of each Al composition on y is as follows.
m * = 0.22 × m ₀ (5)
Φ _B = 1.3 × y + 0.84 (6)
ε = −0.5 × y + 9.5 (7)
ΔEc = 0.7 × y ² + 1.20 × y (8)
σ = 1.89 × 10 ⁻² × y ² + 8.35 × 10 ⁻² × y (9)
Using this relationship, equations (1) and (4) can be rewritten as a function of y.
d ₁ (nm) = 0.42 × (1.3 × y + 0.84) ^−0.5 (10)
d ₂ (nm) = 0.64 × y ⁻¹ −0.06-0.69 × y + 0.14 × y ² (11)
[0011]
Thus, in the configuration of this embodiment, the relationship of _Al y _{Ga 1-y} N layer of Al composition y and thickness d that can achieve ohmic contact,
0.64 × y ⁻¹ −0.06-0.69 × y + 0.14 × y ² ≦ d (nm)
≦ 0.42 × (1.3 × y + 0.84) ^−0.5 (12)
Is set. Equation (12) is a relationship derived from the dependence of m *, Φ _B , ε, △ Ec and σ on the Al composition shown in the literature by Ambacher et al. more If exact relationship is obtained, it is possible to guide the upper limit value and the relationship of the lower limit value and the Al composition of (1) and (4) from the Al y _Ga 1-y _N layer thickness as.
[0012]
The above is the relationship between the Al composition ratio and the thickness derived from the numerical calculation. FIG. 7 shows the result obtained by the experiment. In FIG. 7, the vertical axis represents the contact resistance (Ωcm ² ), and the horizontal axis represents the Al composition y. by growing _Al y _{Ga 1-y} N to produce an epitaxial growth substrate by changing the Al composition and thickness on the n-type GaN layer 14, TLM Al was evaporated on the epitaxial growth substrate (Transmission Line Measurement) pattern Was formed to form an experimental sample, and the contact resistance was measured. When the thickness is 5 nm or less and the Al composition y is 0.5 or more, a low contact resistance of 10 ⁻⁵ Ωcm ² or less is obtained. _Further, corresponding to Al y _{Ga 1-y} is also low contact resistance in a thickness 0.25nm corresponding to one molecular layer of the N are _obtained, Al y _{Ga 1-y} N If there is no layer (y = 0 ) is a high resistance value of the ^{two 10 -3} [Omega] cm, is required one molecular layer or more _{Al y Ga 1-y} N. The thickness d of the _Al y _{Ga 1-y} N layer from the experimental results is that 0.25 ≦ d (nm) ≦ 5 , and, Al composition ratio y is less be in the range of 0.5 ≦ y ≦ 1 Contact resistance can be obtained. Although the experimental results showed the case where Al was used as the ohmic metal, similar results were obtained when Ti / Al, W, WSi, and Mo were used. FIG. 7 shows the result in the case where the annealing is not performed after the vapor deposition. However, by performing the annealing, a lower contact resistance can be obtained.
[0013]
The HJFET is formed as follows. First, a semiconductor layer is grown on a substrate 10 made of (0001) sapphire by, for example, a molecular beam epitaxy (MBE) growth method. The semiconductor layer formed in this manner includes, in order from the substrate side, a buffer layer 11 (thickness: 20 nm) made of undoped AlN, an undoped GaN channel layer 12 (thickness: 2 μm), and an undoped Al _0.2 Ga _0.8 N AlGaN electron supply layer 13 (25 nm thick), n-type GaN layer 14 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , 50 nm thick), AlGaN layer made of undoped Al _0.7 Ga _0.7 N 15 (film thickness 1 nm).
Next, a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa. Subsequently, the source electrode 1 and the drain electrode 3 are formed on the undoped AlGaN layer 15 by depositing a metal such as Ti / Al, for example, and an ohmic contact is made. Here, an example is given in which the Al composition of the AlGaN layer 15 is 0.7 and the film thickness is 1 nm, but the thickness d is 0.25 ≦ d (nm) ≦ 5, and the Al composition ratio y is 0.5 ≦ As described above, a low contact resistance can be obtained if y ≦ 1.
[0014]
Next, for example, a metal such as Ni / Au is vapor-deposited on the AlGaN electron supply layer 13 exposed by etching and removing a part of the AlGaN layer 15, the n-type GaN layer 14, and the AlGaN electron supply layer 13. A gate electrode 2 for key contact is formed. Thus, the HJFET shown in FIG. 1 is manufactured. The substrate material, the manufacturing method, and the layer structure other than the AlGaN layer 15 shown here are examples of specific embodiments, and do not limit the structure of the present invention. This is the same in a second embodiment and later.
[0015]
(Second embodiment)
Next, FIG. 2 for explaining a second embodiment of the present invention with reference to FIG. 2 is a cross-sectional structure of an HJFET according to this embodiment. This embodiment is obtained by replacing the undoped AlGaN layer 15 of the first embodiment with an n-type AlGaN layer 16. That is, this HJFET has a buffer layer 11 made of undoped AlN (thickness: 20 nm), an undoped GaN channel layer 12 (thickness: 2 μm), and an undoped Al ₀ on a substrate made of (0001) sapphire in this order from the substrate side. _.2 AlGaN electron supply layer 13 (25 nm thick) made of Ga _0.8 N, n-type GaN layer 14 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , 50 nm thick), and n-type AlGaN layer 16 It has been done.
In this embodiment, the electric field in the AlGaN layer is further strengthened by the ionized impurities, and the tunnel probability that electrons pass from the electrode to the n-type GaN layer 14 can be increased. Further, an ohmic electrode having a lower resistance can be realized.
[0016]
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG.
FIG. 3 shows a cross-sectional structure of the HJFET according to this embodiment. In this embodiment, the n-type GaN layer 14 constituting the HJFET according to the first embodiment is replaced with an n-type AlGaN layer 17. That is, this HJFET has a buffer layer 11 made of undoped AlN (thickness: 20 nm), an undoped GaN channel layer 12 (thickness: 2 μm), and an undoped Al ₀ on a substrate made of (0001) sapphire in this order from the substrate side. _An AlGaN electron supply layer 13 (thickness: 25 nm) made of _0.2 Ga _0.8 N, an n-type AlGaN layer 17, and an undoped AlGaN layer 15 (thickness: 1 nm) are stacked.
It is appropriate that the Al composition z of the n-type AlGaN layer 17 is approximately 0.1 ≦ z ≦ 0.4, which is almost the same as that of the AlGaN supply layer 13. For example, the Al composition of the n-type AlGaN layer 17 is 0.2 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , the film thickness is 50 nm), and the Al composition of the undoped AlGaN layer 15 is 0.8 (1 nm film thickness). By doing so, the same effect as in the first embodiment can be obtained. Further, by making the undoped AlGaN layer 15 an n-type AlGaN layer, the electric field in the AlGaN layer is further strengthened by the ionized impurities, and the tunneling probability of electrons passing from the electrode to the n-type GaN layer 14 can be increased. In addition, an ohmic electrode having a lower resistance can be realized.
[0017]
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 4 is a cross-sectional structure of the HJFET according to this embodiment. In this embodiment, an n-type AlGaN layer 18 is inserted between the n-type GaN layer 14 and the AlGaN electron supply layer 13 constituting the HJFET according to the first embodiment. That is, this HJFET has a buffer layer 11 made of undoped AlN (thickness: 20 nm), an undoped GaN channel layer 12 (thickness: 2 μm), and an undoped Al ₀ on a substrate made of (0001) sapphire in this order from the substrate side. _.2 AlGaN electron supply layer 13 of Ga _0.8 N (thickness 25 nm), n-type AlGaN layer 18, n-type GaN layer 14 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , thickness 50 nm), undoped Of AlGaN layers 15 (1 nm thick).
[0018]
In this embodiment, in addition to the effects described in the first embodiment, the negative charge induced by the piezo polarization on the electrode side of the electron supply layer 13 is canceled by the ionized positive charge of the n-type impurity, so that the conduction band barrier for electrons is obtained. And the probability of tunneling of electrons from the channel layer 12 to the n-type GaN layer 14 can be increased, so that the resistance during this period can be reduced and the ohmic electrode having a lower contact resistance than the first embodiment can be obtained. Can be realized. Further, by making the undoped AlGaN layer 15 an n-type AlGaN layer, the electric field in the AlGaN layer is further strengthened by the ionized impurities, and the tunneling probability of electrons from the electrode to the n-type GaN layer 14 can be increased. Therefore, it is possible to further reduce the resistance.
[0019]
(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIG.
FIG. 5 is a cross-sectional structure of the HJFET according to this embodiment. This embodiment has a structure in which the gate electrode formed in contact with the AlGaN electron supply layer 13 in the first embodiment is in contact with the n-type GaN layer 14. That is, this HJFET has a buffer layer 11 made of undoped AlN (thickness: 20 nm), an undoped GaN channel layer 12 (thickness: 2 μm), and an undoped Al ₀ on a substrate made of (0001) sapphire in this order from the substrate side. _.2 AlGaN electron supply layer 13 (film thickness 25 nm) made of Ga _0.8 N, n-type GaN layer 14 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , film thickness 50 nm), undoped AlGaN layer 15 (film (Thickness of 1 nm).
In this embodiment, a negative piezo charge is induced on the n-type GaN layer 14 side of the AlGaN electron supply layer 13 below the gate electrode 2. By the action of the piezo charge, the effective Schottky barrier can be increased, and the gate leak current can be suppressed in addition to the effect of the first embodiment. Further, by making the undoped AlGaN layer 15 an n-type AlGaN layer, the electric field in the AlGaN layer is further strengthened by the ionized impurities, and the tunneling probability of electrons from the electrode to the n-type GaN layer 14 can be increased. Therefore, it is possible to further reduce the resistance.
[0020]
(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a cross-sectional structure of the MESFET according to this embodiment. In this MESFET, a buffer layer 11, an undoped GaN buffer 19, an n-type GaN channel layer 20, an n-type GaN layer 14, and an undoped AlGaN layer 15 are sequentially formed on a substrate 10. Then, the source electrode 1 and the drain electrode 3 are formed in contact with the AlGaN layer 15 and have ohmic contact. A gate electrode 2 is formed in a recess formed by removing the AlGaN layer 15 and the n-type GaN layer 14 in contact with the n-type GaN channel layer 20, and has a Schottky contact.
Such a MESFET is manufactured as follows. First, a buffer layer 11 (20 nm thick) made of AlN, an undoped GaN buffer 19 (350 nm thick), an n-type GaN channel are formed on a substrate 10 made of (0001) sapphire in this order from the substrate side by, for example, MBE growth. Layer 20 (n-type impurity concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 150 nm), n-type GaN layer 14 (n-type impurity concentration 5 × 10 ¹⁸ cm ⁻³ , thickness 50 nm), undoped Al _0.7 Ga _{0 A 3N} AlGaN layer 15 (1 nm thick) is grown. Subsequently, a part of the epitaxial layer structure is removed by etching until the undoped GaN buffer 19 is exposed to form an element isolation mesa, and then it is manufactured by the same process as in the first embodiment.
[0021]
In this embodiment, the relationship of _Al y _{Ga 1-y} N layer of Al composition y and thickness d that can achieve ohmic contact, than according to the numerical calculation (12),
0.64 × y ⁻¹ −0.06-0.69 × y + 0.14 × y ² ≦ d (nm) ≦ 0.42 × (1.3 × y + 0.84) ^−0.5
It is. Further, according to the experimental results, from FIG. _7, Al y _{Ga 1-y} N thickness of layer d is the 0.25 ≦ d (nm) ≦ 5 , and, Al proportion y 0.5 ≦ y In the range of ≦ 1, a low contact resistance can be obtained. Further, by making the undoped AlGaN layer 15 an n-type AlGaN layer, the electric field in the AlGaN layer is further strengthened by the ionized impurities, and the tunneling probability of electrons from the electrode to the n-type GaN layer 14 can be increased. Therefore, it is possible to further reduce the resistance. In this embodiment, the structure in which the high-concentration n-type GaN layer 14 is provided between the undoped AlGaN layer 15 and the n-type GaN channel layer 18 is shown. The same effect can be obtained.
[0022]
Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the gist of the present invention. GaN channel in each example _In x _{Ga 1-x} N (where, 0 <x ≦ 1) can be replaced by. Further, the n-type GaN layer 14 in the second, fifth and sixth embodiments can be replaced by an n-type AlGaN layer. Further, in the HJFET of the embodiment, the electron supply layer is disposed on the channel layer. However, the reverse is also possible, and the electron supply layer may be disposed above and below the channel layer.
[0023]
【The invention's effect】
As described above, the semiconductor device of the present invention can achieve low contact resistance without performing high-temperature annealing. Further, in this configuration, the contact resistance is less dependent on the electrode material, and a low contact resistance can be obtained even if a thermally stable high melting point material such as WSi is used as the electrode material.
[Brief description of the drawings]
FIG. 1 is a cross-sectional structure diagram of an HJFET according to a first embodiment of the present invention and a conduction band energy distribution diagram of a contact portion thereof.
FIG. 2 is a sectional structural view of an HJFET according to a second embodiment of the present invention.
FIG. 3 is a sectional structural view of an HJFET according to a third embodiment.
FIG. 4 is a sectional structural view of an HJFET according to a fourth embodiment.
FIG. 5 is a sectional structural view of an HJFET according to a fifth embodiment.
FIG. 6 is a sectional structural view of a MESFET according to a sixth embodiment.
FIG. 7 is a characteristic diagram showing experimental results obtained for the correlation between the Al composition and the film thickness of Al _x Ga ₁ -xN in the contact layer and the contact resistance, for explaining the effect of the present invention.
FIG. 8 is a cross-sectional structure of a conventional HJFET and a conduction band energy distribution diagram of a contact portion thereof.
[Explanation of symbols]
1, 101 Source electrode 2, 102 Gate electrode 3, 103 Drain electrode 10 Substrate 11 Buffer layer 12, 112 GaN channel layer 13, 113 AlGaN electron supply layer 14, 114 n-type GaN layer 15 AlGaN layer 16, 17, 18 n-type AlGaN layer 19 Undoped GaN buffer layer 20 N-type GaN channel layer 110 Sapphire substrate 111 GaN buffer layer

Claims (15)

In a semiconductor device having an ohmic electrode in ohmic contact with said group III nitride semiconductor layer group III nitride semiconductor layer, the group III nitride semiconductor layer, GaN layer or an n-type _{Al u Ga 1-u} N layer (where, 0 <u ≦ 1) Toko GaN layer or the n-type _{Al u Ga 1-u} n layer _Al y _{Ga 1-y} n layer formed on the (where, 0 <y ≦ 1) include cage, the ohmic electrode is a semiconductor device characterized by being formed on the Al y _Ga 1-y _N layer. The thickness of the _Al y _{Ga 1-y} N layer, a wavelength of the _Al y _{Ga 1-y} N layer of the electron and the upper limit, the _Al y _{Ga 1-y} N layer and the conduction band at the interface between the GaN layer The semiconductor device according to claim 1, wherein the lower limit is a thickness at which coincides with the Fermi level. The thickness (d) of the AlyGa1 _-yN layer _satisfies 0.25≤d (nm) ≤5 and 0.5≤y≤1. 13. The semiconductor device according to claim 1. The thickness of the _Al y _{Ga 1-y} N layer (d) is
0.64 × y ⁻¹ −0.06-0.69 × y + 0.14 × y ² ≦ d (nm) ≦ 0.42 × (1.3 × y + 0.84) ^−0.5
The semiconductor device according to claim 1, wherein the following condition is satisfied. It said Al y In _Ga 1-y _N layer, a semiconductor device according to claim 1 which n-type impurities is characterized in that it is doped with either 4. 6. The semiconductor device according to claim 1, wherein the III 窒 化 nitride semiconductor layer includes an AlGaN layer doped with an n-type impurity below the GaN layer. 7. A channel layer, or an active layer including a channel layer and an electron supply layer, a gate electrode for controlling electron conductivity of the channel layer, a contact layer formed on the active layer, and formed in contact with the contact layer It is a source electrode and a drain electrode, the contact layer, GaN layer or an n-type _{Al u Ga 1-u} n layer (where, 0 <u ≦ 1) and _Al was formed thereon y _{Ga 1- y N} layer (where, 0 <y ≦ 1) field effect transistor, characterized in that it contains a. A substrate, a channel layer made of In _x Ga _1-x N (0 ≦ x ≦ 1) formed on the substrate, and Al _z Ga _1-z N formed on the channel layer (where 0 <z ≦ 1), a contact layer formed on the electron supply layer, a gate electrode formed in contact with the electron supply layer, and a source formed in contact with the contact layer and an electrode and a drain electrode, the contact layer, GaN layer or an n-type _{Al u Ga 1-u} n layer (where, 0 <u ≦ 1) and _Al y _{Ga 1-y} n layer formed thereon (Where 0 <y ≦ 1). A substrate, a channel layer made of In _x Ga _1-x N (0 ≦ x ≦ 1) formed on the substrate, and Al _z Ga _1-z N formed on the channel layer (where 0 <z ≦ 1) and the electron supply layer made of a GaN layer formed on the electron supply layer, _{Al y Ga 1-y} N layer formed on the GaN layer (where, 0 <y ≦ 1 a), a gate electrode formed in contact with the GaN layer, the Al y _Ga 1-y _N layer (where 0 <that a y ≦ 1) to the source electrode and a drain electrode formed in contact The field effect transistor characterized by the above-mentioned. A substrate, formed on the substrate the In x _Ga 1-x _{N (where,} 0 ≦ x ≦ 1) and consists of the channel layer, and a contact layer formed on said channel layer, in contact with the channel layer comprising a gate electrode formed, and a source electrode and a drain electrode formed in contact with the contact layer, the contact layer, GaN layer or an n-type Al u _Ga 1-u _n layer (where, 0 <u ≦ 1) and _Al y _{Ga 1-y} N layer formed thereon (where 0 <a field effect transistor, characterized in that it contains y ≦ 1) and. Said Al y _Ga 1-y _N-layer field-effect transistor according to any one of claims 7 to 10, n-type impurities, characterized in that it is doped. 11. The field-effect transistor according to claim 7, wherein the contact layer includes an AlGaN layer inserted below the GaN layer and doped with an n-type impurity. The thickness of the _Al y _{Ga 1-y} N layer, said _Al y _{Ga 1-y} the wavelength of the electrons in the N layer as the upper limit, the _Al y _{Ga 1-y} N layer and the conduction band at the interface between the GaN layer 13. The field-effect transistor according to claim 7, wherein a lower limit of the thickness of the field-effect transistor corresponds to the Fermi level. The thickness of the _Al y _{Ga 1-y} N layer (d) are, 1 ≦ d (nm) is ≦ 5, and claims 7 12, characterized in that a 0.5 ≦ y ≦ 1 The field-effect transistor according to any one of the above. The thickness of the _Al y _{Ga 1-y} N layer (d) is
0.64 × y ⁻¹ −0.06-0.69 × y + 0.14 × y ² ≦ d (nm) ≦ 0.42 × (1.3 × y + 0.84) ^−0.5
13. The field effect transistor according to claim 7, wherein

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