JP2015204425A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture an enhancement FET using a nitride semiconductor easily, with good controllability and reproducibility.SOLUTION: A field effect transistor includes a channel layer 101 composed of a first nitride semiconductor, and a barrier layer 102 composed of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor, and formed on the channel layer 101. The channel layer 101 and barrier layer 102 in a gate formation region 121 have a principal surface of -c plane, and the channel layer 101 and barrier layer 102 in a source formation region 122 and a drain formation region 123 have a principal surface of +c plane.

Description

  The present invention relates to a field effect transistor using a nitride semiconductor and a manufacturing method thereof.

  An example of a field effect transistor (FET) using a nitride semiconductor such as GaN is a heterostructure field effect transistor (HFET). This nitride semiconductor FET is very promising as a next-generation high-temperature / high-output / high-voltage high-frequency transistor, and is actively researched for practical use.

  A nitride semiconductor FET such as a GaN-based HFET using GaN is usually formed in the + c plane ((0001) plane) direction which is the polar plane direction. A nitride semiconductor heterostructure grown in this way has a large polarization charge at the heterointerface. As a result, in the nitride semiconductor FET, carriers that contribute to conduction are generally induced in the channel as channel electrons (two-dimensional electrons) even if the doping process for supplying carriers is not performed.

  Nitride semiconductor FETs having such characteristics have an advantage that a large current can be easily obtained, but in general, the device operation is a so-called depletion type (or normally on) having a negative threshold value. Type) device operation. That is, even when no voltage is applied to the gate electrode (that is, when the gate voltage is zero), the drain current flows by applying the drain voltage, and by applying a negative voltage to the gate electrode, the drain current becomes zero. This is suitable for the transistor operation of becoming (that is, pinching off).

  On the other hand, there is a so-called enhancement type (normally off type) as a device having an operation contrary to the above-described operation. In this state where no voltage is applied to the gate electrode (when the gate voltage is zero), the drain current does not flow even when the drain voltage is applied, and the drain current flows when a positive voltage is applied to the gate electrode. The device operation of the transistor operation is disadvantageous for a general nitride semiconductor FET. Thus, it has been shown that enhancement-type device operation with a positive threshold value can be realized although it is disadvantageous as a general nitride semiconductor FET (see Non-Patent Document 1).

  In power applications, it is essential to realize enhancement type device operation simultaneously with depletion type device operation. For this reason, research on enhancement-type devices is being actively pursued simultaneously with research on depletion-type devices.

  The basic requirement for obtaining an enhancement type operation is that no electrons (carriers) are present under the gate electrode when no voltage is applied to the gate. This is a condition for the threshold value to be positive. In addition, electrons can be present in regions other than the gate electrode. This is a condition for obtaining a drain current in the ON state by applying a positive gate voltage.

  In the most general representative technique for satisfying the above-described conditions, the thickness of the barrier layer semiconductor in a part of the region under the gate electrode region is made smaller than the thickness of the barrier layer semiconductor in the other region. There is a recess gate structure (see Non-Patent Document 2).

M. A. Khan et al., "Enhancement and depletion mode GaN / AlGaN heterostructure field effect transistors", Appl. Phys. Lett., Vol.68, no.4, pp.514-516, 1996. W.B.Lanford et al., "Recessed-gate enhancement-mode GaN HEMT with high threshold voltage", ELECTRONICS LETTERS, vol.41, no.7, 2005. R. Dimitrov et al., “Two-dimensional electron gases in Ga-face and N-face AlGaNOGaN heterostructures grown by plasma-induced molecular beam epitaxy and metalorganic chemical vapor deposition on sapphire”, JOURNAL OF APPLIED PHYSICS, vol.87, no .7, pp.3375-3380, 2000.

  However, in order to deplete electrons in the recess region (region where the thickness of the barrier layer semiconductor is reduced) by the recess gate structure, it is generally necessary to set the barrier layer semiconductor in the region to a very small thickness of 5 nm or less. There is. Further, since the threshold value of the FET strongly depends on the thickness of the barrier layer, a margin in the manufacturing process when realizing a positive threshold value (that is, enhancement type operation) is narrow. For these reasons, there is a problem that it is difficult to manufacture an enhancement type FET using a nitride semiconductor with good controllability and reproducibility.

  The present invention has been made to solve the above problems, and an object of the present invention is to enable enhancement-type FETs using nitride semiconductors to be more easily manufactured with good controllability and reproducibility. And

  A field effect transistor according to the present invention includes a channel layer made of a first nitride semiconductor, a barrier layer formed on the channel layer made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor, A gate electrode formed on the barrier layer, and a source electrode and a drain electrode formed on the barrier layer in the source formation region and the drain formation region sandwiching the gate formation region in which the gate electrode is formed, The channel layer and the barrier layer in the formation region have a main surface as a −c plane, and the channel layer and the barrier layer in the source formation region and the drain formation region have a main surface as a + c plane.

  In the field effect transistor, an impurity layer into which an impurity is introduced may be formed in a partial region of the barrier layer in the stacking direction from the channel layer.

  The field effect transistor includes a lower barrier layer made of a third nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor and formed under the channel layer. The lower barrier layer in the gate formation region has a main surface. The lower barrier layer of the source formation region and the drain formation region may be a −c plane, and the main surface may be a + c plane.

  In the field effect transistor, the gate electrode may be formed on the barrier layer with a gate insulating layer interposed therebetween.

  In the method of manufacturing a field effect transistor according to the present invention, AlN is deposited on a source formation region and a drain formation region sandwiching a gate formation region on a sapphire substrate, and the substrate surface is exposed in the gate formation region of the substrate. A first step of forming an element formation surface comprising an exposed region to be formed, and an AlN layer region formed in the source formation region and the drain formation region, and the main surface of the gate formation region on the element formation surface of the substrate is -C plane, the main surfaces of the source formation region and the drain formation region are + c planes, the second step of epitaxially growing the first nitride semiconductor to form the channel layer, and the main region of the gate formation region on the channel layer The surface is a −c plane, and the main surfaces of the source formation region and the drain formation region are a + c plane, and have a larger band gap energy than the first nitride semiconductor. A third step of epitaxially growing a 2-nitride semiconductor to form a barrier layer; a fourth step of forming a gate electrode on the barrier layer in the gate formation region; and a barrier layer in the source formation region and the drain formation region. A fifth step of forming a source electrode and a drain electrode.

  As described above, according to the present invention, it is possible to obtain an excellent effect that an enhancement type FET using a nitride semiconductor can be more easily manufactured with good controllability and reproducibility.

FIG. 1 is a configuration diagram showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining a potential state in a heterostructure of the channel layer 101 and the barrier layer 102 in each of the gate formation region 121, the source formation region 122, and the drain formation region 123 in Embodiment 1. FIG. FIG. 3 is a configuration diagram showing the configuration of the field effect transistor according to the second embodiment of the present invention. FIG. 4A is a configuration diagram showing a state of each configuration for explaining a partial manufacturing method of the field-effect transistor in the second embodiment of the present invention. FIG. 4B is a configuration diagram showing a state of each configuration for explaining a partial manufacturing method of the field effect transistor according to the second embodiment of the present invention. FIG. 4C is a configuration diagram illustrating a state of each configuration for explaining a partial manufacturing method of the field effect transistor according to the second embodiment of the present invention. FIG. 4D is a configuration diagram illustrating a state of each configuration for explaining a partial manufacturing method of the field effect transistor according to the second embodiment of the present invention. FIG. 5 is a configuration diagram showing the configuration of the field effect transistor according to Embodiment 3 of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. FIG. 1 schematically shows a cross section.

  This field effect transistor includes a channel layer 101 made of a first nitride semiconductor and a barrier layer 102 made of a second nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor and formed on the channel layer 101. Prepare. The field effect transistor also includes a gate electrode 103 formed on the barrier layer 102. In Embodiment 1, the gate electrode 103 is formed over the barrier layer 102 with the gate insulating layer 104 interposed therebetween.

  A source electrode 105 and a drain electrode 106 are provided on the barrier layer 102 in the source formation region 122 and the drain formation region 123 with the gate formation region 121 where the gate electrode 103 is formed therebetween.

  In the above-described configuration, in the first embodiment, the channel layer 101 and the barrier layer 102 in the gate formation region 121 have a main surface as a −c plane ((000-1) plane), and a source formation region 122 and a drain formation region 123. The channel layer 101 and the barrier layer 102 have a main surface as a + c plane. The −c plane of the nitride semiconductor is a nitrogen atom plane (nitrogen atom polar plane), and the + c plane of the nitride semiconductor is a group III atom plane (group III atom polar plane).

  According to Embodiment 1 configured as described above, two-dimensional electrons 131 are formed in channel layer 101 in the vicinity of the heterointerface between channel layer 101 and barrier layer 102 in source formation region 122 and drain formation region 123. become.

  For example, a nitride semiconductor whose surface orientation is a group III atomic plane is formed on a sapphire substrate whose main surface is a (0001) plane by molecular beam epitaxy (MBE) (MBE) method. After the buffer layer is stacked, it can be formed by epitaxially growing a nitride semiconductor such as GaN or AlGaN (see Non-Patent Document 3).

  A nitride semiconductor whose surface orientation is a nitrogen atom plane can be realized by epitaxially growing GaN on a sapphire substrate whose main surface is a (0001) plane by MBE (see Non-Patent Document 3). . Further, not only GaN, but also a nitride semiconductor such as AlGaN may be epitaxially grown with a nitride semiconductor having an Al composition of less than 0.5. The nitride semiconductor having an Al composition of less than 0.5 is a condition for the plane orientation in the surface direction of the nitride semiconductor to be a nitrogen atom plane when grown on the sapphire surface by the MBE method.

  In general, when a nitride semiconductor is epitaxially grown on a sapphire (0001) substrate, a silicon carbide (0001) substrate, or a silicon (111) substrate by metal organic vapor phase epitaxy (MOVPE), The plane orientation of is the group III atomic plane.

  Next, the potential state in the heterostructure of the channel layer 101 and the barrier layer 102 in each of the gate formation region 121, the source formation region 122, and the drain formation region 123 will be described with reference to FIGS. 2A shows the potential shape and the electron distribution state in the heterostructure of the channel layer 101 and the barrier layer 102 in the source formation region 122 and the drain formation region 123. FIG. 2B shows the potential shape in the heterostructure of the channel layer 101 and the barrier layer 102 in the gate formation region 121. FIG.

  As shown in FIG. 2A, the heterointerface between the channel layer 101 and the barrier layer 102 is in a region where the surface orientation of the channel layer 101 and the barrier layer 102 made of a nitride semiconductor is a group III atomic plane. In addition, as a result of the presence of the positive polarization charge 201, two-dimensional electrons 131 are induced in the vicinity of the heterointerface of the channel layer 101.

  On the other hand, as shown in FIG. 2B, the channel layer 101 and the barrier layer 102 are heterogeneous in the region where the surface orientation of the channel layer 101 and the barrier layer 102 made of a nitride semiconductor is a nitrogen atom plane. Since negative polarization charges 202 exist at the interface, two-dimensional electrons are not induced in the vicinity of the heterointerface of the channel layer 101. This state where two-dimensional electrons do not exist (electron depletion) is realized regardless of the thickness of the barrier layer 102.

  As described above, in the first embodiment, the gate formation region 121 is in an electron depletion state, and no electrons exist under the gate electrode 103 (a condition for the threshold to be positive). On the other hand, electrons exist in the source formation region 122 and the drain formation region 123, which are regions other than the gate electrode 103, and a condition for obtaining a drain current is established in an on state by applying a positive gate voltage. As described above, according to the embodiment, a basic state for obtaining an enhancement type operation can be obtained.

  Here, it is a feature of the present invention that a state in which no electrons exist under the gate electrode 103 is generally realized for the barrier layer 102 having an arbitrary thickness. This feature ensures a sufficiently wide manufacturing process margin when fabricating a structure for realizing enhancement-type operation in a field effect transistor using a nitride semiconductor, and is an enhancement-type with good controllability and reproducibility. A field effect transistor can be manufactured.

  Note that an impurity layer (impurity introduction region) is formed by introducing an n-type or p-type impurity into a desired partial region in the stacking direction of the barrier layer 102 from the channel layer 101, thereby forming a desired positive A threshold can be realized. Further, by using the gate insulating layer 104 as in Embodiment Mode 1, an enhancement-type field effect transistor having high characteristics with high gate breakdown voltage and low gate leakage current can be obtained. Note that a Schottky gate electrode structure may be employed without using a gate insulating layer.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIGS. 3 and 4A to 4D. FIG. 3 is a configuration diagram showing the configuration of the field effect transistor according to the second embodiment of the present invention. 4A to 4D are configuration diagrams illustrating states of each configuration for explaining a partial manufacturing method of the field effect transistor according to Embodiment 2 of the present invention. 3 and 4A to 4D schematically show cross sections.

  The field effect transistor includes a substrate 301 made of sapphire whose main surface is (0001), and an AlN layer 302 formed in the source formation region 122 and the drain formation region 123 of the substrate 301. In addition, a channel layer 101 formed on the substrate 301 and the AlN layer 302 and a barrier layer 102 formed on the channel layer 101 are provided. The field effect transistor also includes a gate electrode 103 formed on the barrier layer 102. In Embodiment 1, the gate electrode 103 is formed over the barrier layer 102 with the gate insulating layer 104 interposed therebetween.

  A source electrode 105 and a drain electrode 106 are provided on the barrier layer 102 in the source formation region 122 and the drain formation region 123 with the gate formation region 121 where the gate electrode 103 is formed therebetween. Further, an impurity layer 303 into which an n-type or p-type impurity is introduced is provided in a partial region in the barrier layer 102 stacking direction.

  The above-described channel layer 101, barrier layer 102, gate electrode 103, gate insulating layer 104, source electrode 105, and drain electrode 106 are the same as those in the first embodiment. Also in the second embodiment, the channel layer 101 and the barrier layer 102 in the gate formation region 121 have the main surface as the −c plane, and the channel layer 101 and the barrier layer 102 in the source formation region 122 and the drain formation region 123 are the main surfaces. The surface is a + c plane.

  In Embodiment 2, the source of the substrate 301 is used so that the gate formation region 121 has a nitrogen atom plane (−c plane) and the source formation region 122 and the drain formation region 123 have a group III atom plane (+ c plane). An AlN layer 302 is formed in the formation region 122 and the drain formation region 123. The gate formation region 121 of the substrate 301 is a sapphire surface.

  Note that when the AlN layer 302 is formed, it is desirable that the surface of the AlN layer 302 and the exposed surface of the substrate 301 in the gate formation region 121 be in a flat state that is substantially the same plane. For example, the source formation region 122 and the drain formation region 123 may be thinned by removing the substrate 301 by etching the same thickness as the AlN layer 302, and then forming the AlN layer 302.

  According to the second embodiment, first, in the gate formation region 121, the channel layer 101 is epitaxially grown in contact with the substrate 301. On the other hand, in the source formation region 122 and the drain formation region 123, the channel layer 101 is epitaxially grown on the AlN layer 302. Here, as described above, the position of the uppermost surface of the AlN layer 302 and the position of the uppermost surface of the substrate 301 in the gate formation region 121 are ideally matched, but there is a phase between the two. The difference (step) may be 5 nm or less. If the level difference is 5 nm or less, the level difference formed at the interface between the barrier layer 102 and the channel layer 101 where the channel is formed is 5 nm or less at most. Thus, the transistor characteristics do not deteriorate significantly.

  Next, a method for manufacturing the field effect transistor according to the second embodiment will be described. First, as shown in FIG. 4A, a mask pattern 401 is formed on the substrate 301 in the gate formation region 121. For example, a silicon oxide film is deposited and formed on the substrate 301 by a sputtering method or the like, and the formed silicon oxide film is patterned well by a known lithography technique and etching technique, thereby forming a mask pattern 401 made of silicon oxide. do it.

  Next, using the mask pattern 401 as a mask, the substrate 301 is etched, and as shown in FIG. 4B, the substrate 301 in the source formation region 122 and the drain formation region 123 is thinned, and a convex portion 301a is formed immediately below the mask pattern 401. Form. For example, the substrate 301 in the region where the mask pattern 401 is not formed may be cut by the thickness of the AlN layer 302 to be formed later by a processing method such as a focused ion beam (FIB) method. For example, etching may be performed with a thickness of 10 nm to form a convex portion 301a with a thickness of 10 nm.

  Next, AlN is deposited by MBE to form an AlN film 402 on the substrate 301 and the mask pattern 401 as shown in FIG. 4C. The AlN film 402 is formed to the same thickness as the convex portion 301a. For example, it may be formed to a thickness of 10 nm. Thereafter, the mask pattern 401 is removed (lifted off) to obtain a state in which an AlN layer 302 having a layer thickness of 10 nm is formed in the source formation region 122 and the drain formation region 123 as shown in FIG. 4D. At this time, the position of the uppermost surface 301b of the convex portion 301a and the position of the uppermost surface 302a of the AlN layer 302 coincide with each other to form one plane.

After forming the AlN layer 302 as described above, the channel layer 101 and the barrier layer 102 are formed by epitaxially growing GaN with a thickness of 3 μm by MBE and subsequently epitaxially growing Al _0.3 Ga _0.7 N with a thickness of 20 nm. Form. Here, in the epitaxial growth of Al _0.3 Ga _0.7 N, Mg is doped so as to generate a hole concentration of about 5 × 10 ¹⁸ cm ⁻³ in an 8 nm thick region at a position of 4 to 12 nm in the growth direction from the lower end. Then, the impurity layer 303 is formed.

  After forming the barrier layer 102 as described above, the source electrode 105 and the drain electrode 106 are formed. For example, the source electrode 105 and the drain electrode 106 can be formed by forming a mask pattern having an opening at each electrode position, then depositing an electrode metal by vapor deposition or the like, and then lifting off the mask pattern.

Next, the gate insulating layer 104 is formed between the source electrode 105 and the drain electrode 106. For example, the gate insulating layer 104 having a layer thickness of 25 nm may be formed by depositing Al ₂ O ₃ by atomic layer deposition (ALD). Further, the gate electrode 103 may be formed on the gate insulating film 104 by a lift-off method by depositing a gate electrode metal. The gate length may be 1 μm, for example.

  When the static characteristics evaluation of the field effect transistor actually manufactured in the second embodiment described above was performed, an enhancement type device operation having a threshold value of +3.0 V was confirmed. Further, when the field effect transistor in Embodiment 2 was repeatedly produced by the manufacturing method described above and the static characteristics were evaluated, it was confirmed that enhancement-type operation with the same characteristics was obtained.

[Embodiment 3]
Next, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 is a configuration diagram showing the configuration of the field effect transistor according to Embodiment 3 of the present invention. FIG. 5 schematically shows a cross section.

  The field effect transistor includes a substrate 301 made of sapphire whose main surface is (0001), and an AlN layer 302 formed in the source formation region 122 and the drain formation region 123 of the substrate 301. In addition, a channel layer 101 formed on the substrate 301 and the AlN layer 302 and a barrier layer 102 formed on the channel layer 101 are provided. The field effect transistor also includes a gate electrode 103 formed on the barrier layer 102. In Embodiment 1, the gate electrode 103 is formed over the barrier layer 102 with the gate insulating layer 104 interposed therebetween.

  A source electrode 105 and a drain electrode 106 are provided on the barrier layer 102 in the source formation region 122 and the drain formation region 123 with the gate formation region 121 where the gate electrode 103 is formed therebetween. Further, an impurity layer 303 into which an n-type or p-type impurity is introduced is provided in a partial region in the barrier layer 102 stacking direction. In the third embodiment, the lower barrier layer 501 formed under the channel layer 101 is provided. The lower barrier layer 501 is made of a third nitride semiconductor having a larger band gap energy than the first nitride semiconductor constituting the channel layer 101. The lower barrier layer 501 may be made of the same second nitride semiconductor as the barrier layer 102, for example.

  The above-described channel layer 101, barrier layer 102, gate electrode 103, gate insulating layer 104, source electrode 105, and drain electrode 106 are the same as those in the first embodiment. Also in the third embodiment, the channel layer 101 and the barrier layer 102 in the gate formation region 121 have a main surface as the −c plane, and the channel layer 101 and the barrier layer 102 in the source formation region 122 and the drain formation region 123 The surface is a + c plane. Similarly, the lower barrier layer 501 also has a main surface in the gate formation region 121 as a −c plane and a main surface in the source formation region 122 and the drain formation region 123 as a + c plane.

  In the third embodiment, the gate formation region 121 has a nitrogen atom plane (−c plane), and the source formation region 122 and the drain formation region 123 have a group III atom plane (+ c plane) as described above. As in the second embodiment, an AlN layer 302 is formed in the source formation region 122 and the drain formation region 123 of the substrate 301.

  The field effect transistor in Embodiment 3 has a double hetero structure in which the channel layer 101 is sandwiched between the lower barrier layer 501 and the barrier layer 102. Such a double hetero structure is characterized in that a higher positive threshold is generally obtained as compared with the hetero structure of the second embodiment described above.

  On the other hand, compared with the second embodiment, the third embodiment has a disadvantage that the degree of difficulty of crystal growth of the heterostructure is higher. However, the lower barrier layer 501 in the third embodiment has an advantageous point that transistor characteristics with higher breakdown voltage can be obtained.

Note that the third embodiment can also be manufactured by the manufacturing method described in the second embodiment. In the third embodiment, the thickness of the AlN layer 302 is 10 nm, the lower barrier layer 501 is made of Al _0.05 Ga _0.95 N and the layer thickness is 2 μm, and the channel layer 101 is made of GaN and the layer thickness is 40 nm. The barrier layer 102 is made of Al _0.3 Ga _0.7 N and has a layer thickness of 20 nm. The barrier layer 102 is doped with Mg so that a hole concentration of about 5 × 10 ¹⁸ cm ⁻³ is generated in a region of 8 nm thickness at a position 4 to 12 nm in the growth direction from the lower end, and the impurity layer 303. Form. These were formed by epitaxial growth by the MBE method.

Similarly to Embodiment 2, after the barrier layer 102 is formed, the source electrode 105 and the drain electrode 106 are formed, and then, between the source electrode 105 and the drain electrode 106, Al ₂ O ₃ having a layer thickness of 25 nm. A gate insulating layer 104 made of is formed. Also in the third embodiment, the gate length is 1 μm.

  When the static characteristics evaluation of the field effect transistor actually fabricated in the above-described third embodiment was performed, an enhancement type device operation having a threshold value of +4.0 V was confirmed. Further, when the field effect transistor in Embodiment 3 was repeatedly produced by the manufacturing method described above and the static characteristics were evaluated, it was confirmed that an enhancement-type operation with the same characteristics was obtained.

  As described above, according to the present invention, the field effect has a configuration for enhancement type operation in which no electrons exist under the gate electrode and electrons exist in a region other than the gate electrode. Transistors can be realized with a sufficiently wide manufacturing process margin, and enhancement-type field effect transistors using nitride semiconductors can be more easily manufactured with good controllability and reproducibility. .

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

For example, in Embodiment 2, the barrier layer / channel layer nitride semiconductor material combination is a structure in which the barrier layer is Al _0.3 Ga _0.7 N and the channel layer is GaN. However, the present invention is not limited to this. . For example, the combination of the barrier layer / channel layer is Al _x Ga _1-x N / GaN (0 <X <1), Al _x1 Ga _1-x1 N / In _x2 Ga _1-x2 N (0 <X1 <1, 0 ≦ X2 ≦ 1), Al _X1 Ga _1-X1 N / Al _X2 Ga _1-X2 N (0 <X1 <1, 0 ≦ X2 <0.5, X1> X2), GaN / In _X Ga _1-X N (0 <X ≦ 1), In _X1 Ga _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 <X2 ≦ 1, X1 <X2), In _X Al _1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <0.5), In _X1 Al _1-X1 Any of N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used. If the barrier layer / channel layer is constituted by any combination of these, the band gap of the barrier layer is larger than that of the channel layer, which is the same as in the first embodiment.

In the third embodiment, the combination of the barrier layer / channel layer nitride semiconductor material is a structure in which the barrier layer is Al _0.3 Ga _0.7 N and the channel layer is GaN. However, the present invention is not limited to this. . For example, the combination of the barrier layer / channel layer is Al _x Ga _1-x N / GaN (0 <X <1), Al _x1 Ga _1-x1 N / In _x2 Ga _1-x2 N (0 <X1 <1, 0 ≦ X2 ≦ 1), Al _X1 Ga _1-X1 N / Al _X2 Ga _1-X2 N (0 <X1 <1, 0 ≦ X2 <0.5, X1> X2), GaN / In _X Ga _1-X N (0 <X ≦ 1), In _X1 Ga _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 <X2 ≦ 1, X1 <X2), In _X Al _1-X N / GaN (0 ≦ X <0.5), In _X1 Al _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <0.5, 0 ≦ X2 <0.5), In _X1 Al _1-X1 Any of N / In _X2 Ga _{1 -X2} N (0 ≦ X1 <1, 0 ≦ X2 ≦ 1) may be used. If the barrier layer / channel layer is constituted by any combination of these, the band gap of the barrier layer is larger than that of the channel layer, which is the same as in the second embodiment.

In the third embodiment, the channel layer / lower barrier layer nitride semiconductor material combination is a structure in which the channel layer is GaN and the lower barrier layer is Al _0.05 Ga _0.95 N. However, the present invention is not limited to this. Absent. For example, the combination of the channel layer / lower barrier _{layer, GaN / Al X Ga 1-} X N (0 <X <0.5), In X1 Ga 1-X1 N / Al X2 Ga 1-X2 N (0 ≦ X1 ≦ 1, 0 <X2 <0.5), Al _X1 Ga _1-X1 N / Al _X2 Ga _1-X2 N (0 ≦ X1 <X2 <0.5), In _X Ga _1-X N / GaN (0 <X ≦ 1), In _X1 Ga _{1 -X1} N / In _X2 Ga _{1 -X2} N (0 <X1 ≦ 1, 0 ≦ X2 <1, X2 <X1) may be used. If the channel layer / lower barrier layer is configured by any combination of these, the band gap of the lower barrier layer becomes larger than that of the channel layer, which is the same as in the third embodiment.

Further, in the second and third embodiments described above, although the gate insulating layer was formed from Al ₂ O _3, not limited to this. The gate insulating layer may be composed of any one of SiN, SiO ₂ , AlN, ZrO ₂ , and HfO ₂ , or may be composed of an insulating material other than this.

  DESCRIPTION OF SYMBOLS 101 ... Channel layer, 102 ... Barrier layer, 103 ... Gate electrode, 104 ... Gate insulating layer, 105 ... Source electrode, 106 ... Drain electrode, 121 ... Gate formation region, 122 ... Source formation region, 123 ... Drain formation region, 131 ... two-dimensional electrons.

Claims (5)

A channel layer made of a first nitride semiconductor;
A barrier layer made of a second nitride semiconductor having a larger band gap energy than the first nitride semiconductor and formed on the channel layer;
A gate electrode formed on the barrier layer;
A source electrode and a drain electrode formed on the barrier layer in a source formation region and a drain formation region sandwiching a gate formation region in which the gate electrode is formed, and
The channel layer and the barrier layer in the gate formation region have a main surface as a −c plane,
The channel layer and the barrier layer of the source formation region and the drain formation region have a main surface as a + c plane. The field effect transistor of claim 1, wherein
A field effect transistor, wherein an impurity layer into which an impurity is introduced is formed in a partial region of the barrier layer in the stacking direction from the channel layer. The field effect transistor according to claim 1 or 2,
A lower barrier layer made of a third nitride semiconductor having a larger band gap energy than the first nitride semiconductor and formed under the channel layer;
The lower barrier layer of the gate formation region has a main surface as a -c plane,
The lower barrier layer of the source formation region and the drain formation region has a main surface as a + c plane. The field effect transistor according to any one of claims 1 to 3,
The field effect transistor, wherein the gate electrode is formed on the barrier layer through a gate insulating layer. AlN is deposited on a source formation region and a drain formation region sandwiching a gate formation region on a substrate made of sapphire, and an exposed region in which the substrate surface is exposed in the gate formation region of the substrate, and the source formation region and the drain formation A first step of forming an element formation surface comprising an AlN layer region formed in the region;
On the element formation surface of the substrate, a main surface of the gate formation region is a −c plane, a main surface of the source formation region and the drain formation region is a + c plane, and a first nitride semiconductor is epitaxially grown. A second step of forming a channel layer;
On the channel layer, the main surface of the gate formation region is a −c plane, the main surfaces of the source formation region and the drain formation region are + c planes, and has a bandgap energy larger than that of the first nitride semiconductor. A third step of epitaxially growing a 2-nitride semiconductor to form a barrier layer;
A fourth step of forming a gate electrode on the barrier layer in the gate formation region;
And a fifth step of forming a source electrode and a drain electrode on the barrier layer in the source formation region and the drain formation region.