JP6176677B2 - Nitride semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device made of a group III nitride semiconductor (hereinafter sometimes simply referred to as “nitride semiconductor”).

The group III nitride semiconductor is a semiconductor using nitrogen as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are typical examples. In _general, it can be expressed as _{Al X In Y Ga 1-X} -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ X + Y ≦ 1).
HEMT (High Electron Mobility Transistor) using such a nitride semiconductor has been proposed. Such a HEMT includes, for example, an electron transit layer made of GaN and an electron supply layer made of AlGaN epitaxially grown on the electron transit layer. A pair of source and drain electrodes are formed in contact with the electron supply layer, and a gate electrode is disposed between them. The gate electrode is disposed so as to face the electron supply layer with the insulating film interposed therebetween. Due to polarization caused by lattice mismatch between GaN and AlGaN, a two-dimensional electron gas is formed in the electron transit layer at a position several inches inside from the interface between the electron transit layer and the electron supply layer. . The source and drain are connected using this two-dimensional electron gas as a channel. By applying a control voltage to the gate electrode, when the two-dimensional electron gas is cut off, the source and drain are cut off. When the control voltage is not applied to the gate electrode, the source and drain are electrically connected, so that a normally-on type device is obtained.

A device using a nitride semiconductor has characteristics such as high breakdown voltage, high temperature operation, large current density, high speed switching, and low on-resistance, and therefore, application to a power device is being studied.
However, in order to use it as a power device, it is necessary to be a normally-off type device that cuts off a current at zero bias, and thus the HEMT as described above cannot be applied to a power device.

  A structure for realizing a normally-off type nitride semiconductor HEMT is proposed in, for example, Patent Document 1 and Patent Document 2.

JP 2011-171440 A JP 2006-339561 A

  Patent Document 1 discloses a structure in which the thickness of the electron supply layer immediately below the gate electrode is reduced. However, it is difficult to precisely control the thickness of the electron supply layer by etching, and the electron supply layer directly under the gate electrode cannot be completely eliminated. For this reason, the channel created by the polarization due to the lattice mismatch between the electron supply layer and the electron transit layer cannot be completely eliminated, so that it does not become a normally-off type device in practice. In addition, if the etching from the electron supply layer is performed beyond the interface between the electron supply layer / electron transit layer, the interface between the electron supply layer / electron transit layer is damaged, so that the electron mobility is remarkably reduced, and the device The characteristics are significantly deteriorated.

  On the other hand, in Patent Document 2, a p-type GaN layer is stacked on an n-type AlGaN electron supply layer, a gate electrode is disposed thereon, and a channel is eliminated by a depletion layer extending from the p-type GaN layer. A configuration to be achieved is disclosed. However, in this configuration, a high gate voltage cannot be applied due to a forward voltage drop (for example, about 2 V) at the pn junction. For example, when the power supply voltage is 5V, a voltage of about 3V can only be applied to the channel. Therefore, the on-characteristic is not so good.

  Accordingly, an object of the present invention is to provide a nitride semiconductor device having a normally-off HEMT structure and having excellent device characteristics.

In order to achieve the above object, the present invention provides an electron transit layer made of a nitride semiconductor and a nitride semiconductor laminated on the electron transit layer, the Al composition being different from the electron transit layer and comprising Al. An electron supply layer, a first insulating film formed on the electron traveling layer, having an interface continuous to an interface between the electron supply layer and the electron traveling layer; and the electrons sandwiching the first insulating film A gate electrode facing the traveling layer; and a second insulating film disposed so as to be interposed between the first insulating film and the gate electrode, wherein the electron supply layer faces the electron traveling layer. The first insulating film is formed over the bottom and side walls of the recess, and includes a bottom covering portion that covers the bottom portion and a side wall covering portion that covers the side wall. The second insulating film includes the second insulating film in the recess. Insulating film in contact, and the is formed to extend to the outside of the recess, the electron supply layer, the first layer is AlN layer in contact with the electron transit layer, are laminated so as to be in contact with the first layer the Provided is a nitride semiconductor device including a second layer having a different Al composition from a first layer, wherein the bottom covering portion is made of a thermal oxide of a material of the first layer.

In one embodiment of the present invention, the thickness of the first insulating film is smaller than the thickness of the second insulating film.
In one embodiment of the present invention, the thickness of the second insulating film is larger than the thickness of the electron supply layer.
The nitrogen concentration in the first insulating film may be higher than the nitrogen concentration in the second insulating film. Specifically, the nitrogen concentration in the first insulating film may be 5 × 10 ¹⁶ cm ⁻³ or more, and the nitrogen concentration in the second insulating film may be less than 5 × 10 ¹⁶ cm ⁻³ .

The film thickness of the first insulating film may be 5 nm or less (preferably 1 nm to 5 nm).
The first insulating film may contain nitrogen at a concentration of 5 × 10 ¹⁶ cm ⁻³ or more .
Before Stories second layer may consist of Al _x Ga _1-x N layer (0 <x <1).

The bottom surface covering portion may be in contact with the electron transit layer and have a film thickness substantially equal to that of the first layer.
The second insulating film may be made of aluminum oxide.

FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to an embodiment of the present invention. 2A is a cross-sectional view showing a configuration in the middle of the manufacturing process of the nitride semiconductor device of FIG. FIG. 2B is a cross-sectional view showing a configuration at a later stage of FIG. 2A. FIG. 2C is a cross-sectional view illustrating a configuration at a later stage of FIG. 2B. FIG. 2D is a cross-sectional view illustrating a configuration at a later stage of FIG. 2C. FIG. 2E is a cross-sectional view showing a configuration at a later stage of FIG. 2D. FIG. 2F is a cross-sectional view showing a configuration at a later stage of FIG. 2E.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to an embodiment of the present invention. The nitride semiconductor device includes a substrate 1 (for example, a silicon substrate), a buffer layer 2 formed on the surface of the substrate 1, an electron transit layer 3 epitaxially grown on the buffer layer 2, and an epitaxial growth on the electron transit layer 3. And the electron supply layer 4 formed. Further, the nitride semiconductor device includes a passivation film 5 that covers the surface of the electron supply layer 4, and a source electrode that is in ohmic contact with the electron supply layer 4 through the contact holes 6 a and 7 a formed in the passivation film 5. 6 and the drain electrode 7. The source electrode 6 and the drain electrode 7 are arranged at an interval, and the gate electrode 8 is arranged between them.

  The electron supply layer 4 is formed with a recess 9 dug from the surface toward the electron transit layer 3. An oxide film 11 (first insulating film) is formed so as to cover bottom 9a and side wall 9b of recess 9. An insulating layer 12 (second insulating film) is laminated on the oxide film 11, and the gate insulating film 10 is constituted by the oxide film 11 and the insulating layer 12. The gate electrode 8 faces the electron transit layer 3 at the bottom 9a of the recess 9 with the gate insulating film 10 interposed therebetween. Since the oxide film 11 extends so as to cover not only the bottom 9a of the recess 9 but also the side wall 9b, a leak path can be reduced.

The electron transit layer 3 and the electron supply layer 4 are made of group III nitride semiconductors (hereinafter simply referred to as “nitride semiconductors”) having different Al compositions. For example, the electron transit layer 3 may be composed of a GaN layer, and the thickness thereof may be about 0.5 μm. In this embodiment, the electron supply layer 4 has a first layer 41 in contact with the electron transit layer 3 and a second layer 42 in contact with the first layer 41. In this embodiment, the first layer 41 is made of an AlN layer, and has a thickness of, for example, about several atomic thickness (5 nm or less, preferably 1 to 5 nm, more preferably 1 to 3 nm). In this embodiment, the second layer 42 is composed of an Al _x Ga _1-x N layer (0 <x <1), and has a thickness of about 20 nm, for example.

  Thus, the electron transit layer 3 and the electron supply layer 4 are made of nitride semiconductors having different Al compositions, and a lattice mismatch occurs between them. Due to this polarization due to the lattice mismatch, a position close to the interface between the electron transit layer 3 and the electron supply layer 4 (for example, a position about several kilometers away from the interface) has two polarizations due to the polarization. The dimensional electron gas 15 is spreading. The first layer 41 made of AlN suppresses electron scattering and contributes to improvement of electron mobility.

  At the bottom 9 a of the recess 9, the oxide film 11 has a film thickness almost equal to that of the first layer 41 of the electron supply layer 4. Specifically, the oxide film 11 has a thickness of 5 nm or less, preferably 1 to 5 nm, more preferably 1 to 3 nm. The oxide film 11 is in contact with the electron transit layer 3, and the interface between the oxide film 11 and the electron transit layer 3 is located in the same plane as the interface between the electron supply layer 4 and the electron transit layer 3. In other words, the interface between the oxide film 11 and the electron transit layer 3 is continuous with the interface between the electron supply layer 4 and the electron transit layer 3.

In this embodiment, the oxide film 11 is a thermal oxide film, and is an oxide film formed without damaging the interface with the electron transit layer 3. The oxide film 11 contains nitrogen at a concentration higher than the nitrogen concentration in the insulating layer 12. More specifically, the nitrogen concentration in the oxide film 11 is 5 × 10 ¹⁶ cm ⁻³ or more, and the nitrogen concentration in the insulating layer 12 is less than 5 × 10 ¹⁶ cm ⁻³ . More specifically, the oxide film 11 has a higher nitrogen concentration in the bottom cover portion 11a in contact with the bottom portion 9a of the recess 9, and the nitrogen concentration in the bottom cover portion 11a is 5 × 10 ¹⁶ cm ⁻³ or more. It is higher than the nitrogen concentration in the side wall covering portion 11b that covers the side wall 9b of the recess 9.

  The insulating layer 12 is made of, for example, aluminum oxide (alumina), and is thicker than the oxide film 11 (for example, may be thicker than the electron supply layer 4). Thereby, even if the oxide film 11 is thin, the gate insulating film 10 having a required film thickness is formed together with the oxide film 11, which contributes to the improvement of the dielectric breakdown voltage. In this embodiment, the insulating layer 12 is formed so as to be in contact with the oxide film 11 in the recess 9 and further to the outside of the recess 9. Thereby, the pressure | voltage resistance is further improved.

  The gate electrode 8 is formed in contact with the insulating layer 12. The gate electrode 8 may be composed of a laminated electrode film having a lower layer in contact with the insulating layer 12 and an upper layer laminated on the lower layer. The lower layer may be made of Ni or Pt, and the upper layer may be made of Au or Al. The gate electrode 8 is biased toward the source electrode 6 and has an asymmetric structure in which the gate-drain distance is longer than the gate-source distance. This asymmetric structure alleviates a high electric field generated between the gate and the drain and contributes to an improvement in breakdown voltage.

The source electrode 6 and the drain electrode 7 may have, for example, a lower layer in contact with the electron supply layer 4 and an upper layer stacked on this lower layer. The lower layer may be Ti, and the upper layer may be an Al layer.
The buffer layer 2 may be, for example, an AlGaN layer or a layer having a superlattice structure in which an AlN layer and a GaN layer are repeatedly stacked.

  In this nitride semiconductor device, an electron supply layer 4 having a different Al composition is formed on the electron transit layer 3 to form a heterojunction. Thereby, a two-dimensional electron gas 15 is formed in the electron transit layer 3 in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4, and a HEMT using the two-dimensional electron gas 15 as a channel is formed. The gate electrode 8 faces the electron transit layer 3 with the gate insulating film 10 formed of a laminated film of the oxide film 11 and the insulating layer 12 interposed therebetween, and the electron supply layer 4 does not exist immediately below the gate electrode 8. Therefore, the two-dimensional electron gas 15 due to polarization due to lattice mismatch between the electron supply layer 4 and the electron transit layer 3 is not formed immediately below the gate electrode 8. Therefore, when no bias is applied to the gate electrode 8 (at the time of zero bias), the channel formed by the two-dimensional electron gas 15 is blocked immediately below the gate electrode 8. In this way, a normally-off HEMT is realized. When an appropriate ON voltage (for example, 5 V) is applied to the gate electrode 8, a channel is induced in the electron transit layer 3 immediately below the gate electrode 8, and the two-dimensional electron gas 15 on both sides of the gate electrode 8 is connected. Thereby, conduction between the source and the drain is established.

In use, for example, a predetermined voltage (for example, 200 V to 400 V) that is positive on the drain electrode 7 side is applied between the source electrode 6 and the drain electrode 7. In this state, an off voltage (0 V) or an on voltage (5 V) is applied to the gate electrode 8 with the source electrode 6 as a reference potential (0 V).
The interface between the oxide film 11 and the electron transit layer 3 is continuous with the interface between the electron supply layer 4 and the electron transit layer 3, and the state of the interface of the electron transit layer 3 immediately below the gate electrode 8 is the electron supply layer. 4 and the state of the interface between the electron transit layer 3. Therefore, the electron mobility in the electron transit layer 3 immediately below the gate electrode 8 is kept high. In addition, a sufficiently high on-voltage can be applied to the gate electrode 8 as compared with a configuration having a pn junction in the gate portion (see Patent Document 2). Therefore, the device characteristics when the on-voltage is applied to the gate electrode 8 are also good.

Thus, this embodiment provides a nitride semiconductor device having a normally-off HEMT structure and having excellent device characteristics.
2A to 2F are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device described above, and show cross-sectional structures at a plurality of stages in the manufacturing process.
First, as shown in FIG. 2A, the buffer layer 2 and the electron transit layer 3 are epitaxially grown on the substrate 1 in this order, and the electron supply layer 4 is further epitaxially grown on the electron transit layer 3. Further, a passivation film 5 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface of the electron supply layer 4. The passivation film 5 may be made of silicon nitride (SiN), and the film thickness is suitably about several hundred nm. The epitaxial growth of the electron supply layer 4 includes a step of epitaxially growing a first layer 41 made of AlN on the electron transit layer 3 and a step of epitaxially growing a second layer 42 made of AlGaN on the first layer 41.

  Next, as shown in FIG. 2B, a recess 9 is formed in the electron supply layer 4 in accordance with the formation position of the gate electrode 8. Specifically, a mask having an opening is formed at a position where the concave portion 9 is to be formed, the passivation film 5 is opened by dry etching through the mask, and a part of the electron supply layer 4 is etched, A recess 9 that is recessed from the surface of the electron supply layer 4 toward the electron transit layer 3 is formed. At this time, a thin part 4 t having a thickness of 5 nm or less (preferably 1 to 5 nm, more preferably 1 to 3 nm) is left on the bottom 9 a of the recess 9, which is thinner than the electron supply layer 4 outside the recess 9. This thin part 4t may consist of only the first layer 41 (AlN layer), or may include a part of the second layer 42 (AlGaN layer) in addition to the first layer 41.

Next, as shown in FIG. 2C, an oxide film 11 is formed by a thermal oxidation process performed while flowing an oxygen gas in a thermal oxidation furnace. This thermal oxidation treatment is performed so that the thin portion 4t is converted into the oxide film 11 over and over the entire thickness. In the first layer (AlN layer) included in the thin part 4t, nitrogen atoms (N) are replaced with oxygen atoms (O) by thermal oxidation treatment, and Al _a O _b (where a and b are positive real numbers) To an oxide film. As a result, at the bottom 9 a of the recess 9, the interface between the electron supply layer 4 and the electron transit layer 3 disappears and instead becomes an interface between the oxide film 11 and the electron transit layer 3.

This interface is an interface formed by thermal oxidation, and is an extremely good interface formed without being exposed to the atmosphere even during the manufacturing process. Therefore, the electron mobility in the electron transit layer 3 immediately below the interface has the same high value as the other portions. Thereby, a low on-resistance and a high switching speed can be realized.
Since the thermal oxidation process proceeds not only at the bottom 9a of the recess 9 but also at the side wall 9b exposed to the oxygen atmosphere, the oxide film 11 is formed to cover the bottom 9a and further extend to the side wall 9b. . The bottom covering portion 11a of the oxide film 11 includes a portion converted from the first layer 41 made of an AlN layer, and the side wall covering portion 11b is changed from the second layer 42 made of an AlGaN layer to an oxide film. Therefore, the oxide film 11 contains nitrogen, and the nitrogen concentration in the bottom covering portion 11a is higher than the nitrogen concentration in the side wall covering portion 11b.

Next, as shown in FIG. 2D, the insulating layer 12 is formed so as to cover the entire exposed surface. Therefore, the insulating layer 12 is formed in contact with the oxide film 11 in the recess 9 and extending to a region outside the recess 9. The insulating layer 12 is preferably an insulating film of the same type as the oxide film 11, and may be made of alumina (Al ₂ O ₃ ), for example. Such an insulating layer 12 can be formed by, for example, an ALD (Atomic Layer Deposition) method.

  Next, as shown in FIG. 2E, the source electrode 6 and the drain electrode 7 are formed. Specifically, contact holes 6a and 7a penetrating the insulating layer 12 and the passivation film 5 are formed so as to match the formation positions thereof, and then an electrode film is formed. For example, the electrode film is composed of a laminated metal film obtained by laminating a Ti layer as a lower layer and an Al layer as an upper layer, and is formed by sequentially depositing each layer. The electrode film is patterned by etching, and further subjected to a sintering process (for example, 500 ° C. to 600 ° C.), whereby the source electrode 6 and the drain electrode 7 that are in ohmic contact with the electron supply layer 4 are formed.

Next, as shown in FIG. 2F, a resist film 16 having an opening at the position where the gate electrode 8 is formed is formed, and an electrode film 17 is formed so as to cover the entire surface in that state. The electrode film 17 is made of, for example, a laminated metal film in which a lower layer made of Ni or Pt and an upper layer made of Au or Al are laminated, and each layer is deposited in order.
Next, the electrode film 17 on the resist film 16 (unnecessary portion of the electrode film 17) is lifted off together with the resist film 16, whereby the electrode film 17 is patterned and the gate electrode 8 is obtained. Further, the nitride semiconductor device having the structure shown in FIG. 1 is obtained by performing etching using the electrodes 6, 7 and 8 as a mask to remove the exposed portion of the insulating layer 12 until the passivation film 5 is exposed.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the example in which the electron transit layer 3 is made of a GaN layer and the electron supply layer 4 includes the first layer 41 made of AlN and the second layer 42 made of AlGaN has been described. The electron supply layer 4 only needs to have a different Al composition, and other combinations are possible. For example, as the combination of the electron transit layer 3 / the first layer 41 / the second layer 42, GaN / AlN / AlGaN, Al _m Ga _1-m N / AlN / Al _n Ga _1-n N (where m ≠ n ), AlGaN / AlN / AlInN, GaN / AlN / AlInN, GaN / AlN / AlN, AlGaN / AlN / AlN, and the like. Of course, when the first layer 41 and the second layer 42 are both AlN layers, it is not necessary to distinguish the first layer 41 and the second layer 42. Even when the second layer 42 is made of a material other than AlN, an oxide film can be formed on the bottom 9a of the recess 9 without necessarily providing the first layer made of AlN. However, by providing the AlN layer so as to be in contact with the electron transit layer 3, the scattering of electrons can be suppressed, the electron mobility can be increased, and the oxide film 11 in contact with the electron transit layer 3 can be reliably formed by a thermal oxidation method. There is an advantage that can be formed.

In the above-described embodiment, the gate insulating film 10 is composed of two layers of the oxide film 11 and the insulating layer 12. However, the gate insulating film 10 is formed by stacking three or more insulating films, and dielectric breakdown occurs. It is good also as a structure which raised pressure | voltage resistance more.
In the above-described embodiment, silicon is exemplified as a material example of the substrate 1, but any other substrate material such as a sapphire substrate or a GaN substrate can be applied.

In addition, various design changes can be made within the scope of matters described in the claims.
Features that can be extracted from this specification and the accompanying drawings are described below.
A1. An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, has an Al composition different from that of the electron transit layer, and is made of a nitride semiconductor containing Al;
An oxide film formed on the electron transit layer, having an interface continuous with the interface between the electron supply layer and the electron transit layer;
A gate electrode facing the electron transit layer across the oxide film;
An insulating layer disposed so as to be interposed between the oxide film and the gate electrode;
The nitride semiconductor device, wherein a thickness of the oxide film is smaller than a thickness of the insulating layer.

  According to this configuration, the electron supply layer having a different Al composition is formed on the electron transit layer to form a heterojunction. Therefore, a two-dimensional electron gas is formed in the electron transit layer in the vicinity of the interface between the electron transit layer and the electron supply layer, and a HEMT using the two-dimensional electron gas as a channel is formed. The gate electrode is opposed to the electron transit layer with the oxide film interposed therebetween. The interface between the oxide film and the electron transit layer is continuous with the interface between the electron supply layer and the electron transit layer. That is, there is no electron supply layer immediately below the oxide film, and therefore, a two-dimensional electron gas due to polarization due to lattice mismatch between the electron supply layer and the electron transit layer is not formed immediately below the gate electrode. Therefore, when no bias is applied to the gate electrode (at the time of zero bias), the channel due to the two-dimensional electron gas is blocked immediately below the gate electrode. Thereby, a normally-off type HEMT is realized. When an appropriate ON voltage is applied to the gate electrode, a channel is induced in the electron transit layer immediately below the gate electrode, and the two-dimensional electron gas on both sides of the gate electrode is connected.

  On the other hand, the interface between the oxide film and the electron transit layer is continuous with the interface between the electron supply layer and the electron transit layer, and the state of the interface of the electron transit layer immediately below the gate electrode is as follows. It is equivalent to the state of the interface. Therefore, the electron mobility in the electron transit layer directly under the gate electrode is kept high. Further, unlike the structure of Patent Document 2 in which the gate has a pn junction, a sufficiently high on-voltage can be applied to the gate electrode. Therefore, the device characteristics when the on-voltage is applied to the gate electrode are also good.

Thus, a nitride semiconductor device having a normally-off HEMT structure and having excellent device characteristics can be provided.
The combination of the electron supply layer / electron transit layer includes AlGaN layer / GaN layer, AlGaN layer / AlGaN layer (although different Al compositions), AlInN layer / AlGaN layer, AlInN layer / GaN layer, AlN layer / GaN layer, AlN Any of layer / AlGaN layer may be used. More generally, the electron supply layer contains Al and N in the composition. The electron transit layer contains Ga and N in the composition, and the Al composition is different from that of the electron supply layer. Due to the difference in Al composition between the electron supply layer and the electron transit layer, a lattice mismatch occurs between them, and thereby a two-dimensional electron gas due to polarization is generated in the electron transit layer close to the interface.

  In addition, since the insulating layer is disposed so as to be interposed between the oxide film and the gate electrode, a gate insulating film (oxide film and insulating layer) having a necessary thickness between the gate electrode and the electron supply layer. ) Can be placed. More specifically, since the insulating layer is stacked on the oxide film, even if the thickness of the oxide film is smaller than the thickness of the insulating layer, the gate insulating film having the necessary thickness for the entire oxide film and insulating layer Can be formed. Therefore, by making the oxide film thinner, the electron supply layer directly under the gate electrode can be surely lost, and damage to the interface with the electron transit layer can be minimized when forming the oxide film. . On the other hand, the dielectric breakdown voltage can be improved by forming the gate insulating film to a sufficient thickness.

A2. The nitride semiconductor device according to item A1, wherein the nitrogen concentration in the oxide film is higher than the nitrogen concentration in the insulating layer.
A3. An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, has an Al composition different from that of the electron transit layer, and is made of a nitride semiconductor containing Al;
An oxide film formed on the electron transit layer, having an interface continuous with the interface between the electron supply layer and the electron transit layer;
A gate electrode facing the electron transit layer across the oxide film;
An insulating layer disposed so as to be interposed between the oxide film and the gate electrode;
The nitride semiconductor device, wherein a nitrogen concentration in the oxide film is higher than a nitrogen concentration in the insulating layer.

For example, when an AlN layer is formed at the interface between the electron supply layer and the electron transit layer and is converted into an oxide film by a thermal oxidation method, the nitrogen concentration in the oxide film is higher than the nitrogen concentration in the insulating layer. Become.
A4. The nitrogen concentration in the oxide film is 5 × 10 ¹⁶ cm ⁻³ or more, and the nitrogen concentration in the insulating layer is less than 5 × 10 ¹⁶ cm ⁻³ , according to any one of Items A1 to A3. Nitride semiconductor device.

A5. The electron supply layer has a recess recessed toward the electron transit layer;
The nitride semiconductor device according to any one of Items A1 to A4, wherein the oxide film is formed on a bottom of the recess.
With this configuration, the channel (two-dimensional electron gas) in the electron transit layer can be cut off immediately below the recess formed in the electron supply layer, and the channel (two-dimensional electron in the electron transit layer is sandwiched between the recesses). Gas).

A6. The nitride semiconductor device according to Item A5, wherein the insulating layer includes a portion disposed in the recess.
With this configuration, since the insulating layer is in contact with the oxide film disposed at the bottom of the recess, a good gate insulating film can be formed between the gate electrode.
The insulating layer may be formed so as to extend not only inside the recess but also outside the recess. If the insulating layer is formed so as to extend out of the recess, the breakdown voltage can be increased.

A7. The nitride semiconductor device according to Item A5 or A6, wherein the oxide film is formed across the bottom and side walls of the recess.
According to this configuration, since the oxide film is formed not only on the bottom but also on the side wall, the leakage current can be reduced. For example, when an oxide film is formed by thermal oxidation after forming a recess in the electron supply layer, an oxide film continuous over the bottom and side walls of the recess is formed.

A8. The nitride semiconductor device according to any one of Items A1 to A7, wherein the thickness of the oxide film is 5 nm or less (preferably 1 nm to 5 nm).
An oxide film of 5 nm or less can be formed by a thermal oxidation method. Therefore, after the electron supply layer is partially thinned to 5 nm or less (for example, the concave portion is formed), thermal oxidation is performed, so that the electron travel is not damaged to the interface between the electron supply layer and the electron travel layer. A thermal oxide film in contact with the layer can be formed, and the electron supply layer can be lost in that portion.

A9. The nitride semiconductor device according to any one of Items A1 to A8, wherein the oxide film contains nitrogen at a concentration of 5 × 10 ¹⁶ cm ⁻³ or more.
A10. The nitride semiconductor device according to any one of Items A1 to A9, wherein the electron supply layer has an AlN layer at an interface with the electron transit layer.
When thermal oxidation is performed on the AlN layer, nitrogen atoms (N) are removed by heating, whereby nitrogen atoms (N) are replaced with oxygen atoms (O), and an oxide film made of Al _x O _y is formed. Therefore, if an AlN layer is disposed at the interface between the electron supply layer and the electron transit layer, it can be converted into a thermal oxide film to form an oxide film. In addition, since the AlN layer is formed at the interface with the electron transit layer, electron scattering is suppressed, so that the electron mobility can be increased.

A11. Any of paragraphs A1 to A10, wherein the electron supply layer includes a first layer that is in contact with the electron transit layer, and a second layer that is stacked so as to be in contact with the first layer and has a different Al composition from the first layer. The nitride semiconductor device according to claim 1. The first layer may be the AlN layer. In this case, the second layer may be an AlGaN layer or an AlInN layer.
A12. Forming an electron transit layer made of a nitride semiconductor;
A step of forming an electron supply layer made of a nitride semiconductor containing Al on the electron transit layer, the Al composition being different from the electron transit layer;
Forming a recess by etching a part of the electron supply layer, and forming a recess at the bottom of the recess that is thinner than a portion outside the recess and in contact with the electron transit layer;
A thermal oxidation step of converting the entire thin portion into an oxide film by thermally oxidizing the thin portion;
And a gate forming step of forming a gate electrode facing the electron transit layer with the oxide film interposed therebetween.

  According to this method, a part of the electron supply layer is etched to form a recess, and a thin part of the electron supply layer is formed at the bottom of the recess. By thermally oxidizing the thin part, the entire thin part is converted into an oxide film. Thus, the electron supply layer can be lost at the bottom of the recess without damaging the interface between the electron supply layer and the electron transit layer. Thereby, a nitride semiconductor device having a normally-off HEMT structure and having excellent device characteristics can be manufactured.

A13. The nitride semiconductor device according to Item A12, wherein the recess forming step includes a step of etching part of the electron supply layer so that the thickness of the thin portion is 5 nm or less (preferably 1 to 5 nm). Production method.
According to this method, etching is performed until the thickness of the thin portion becomes 5 nm or less, so that the entire thin portion can be reliably converted into an oxide film by subsequent thermal oxidation.

A14. The method of manufacturing a nitride semiconductor device according to Item A13, wherein the thermal oxidation step includes a step of oxidizing the side wall of the concave portion continuous from the thin portion and forming the oxide film so as to extend to the side wall. .
According to this method, since the oxide film is formed not only on the bottom of the recess but also on the side wall thereof, the leak path can be reduced and the device characteristics can be improved.

A15. The nitride according to any one of Items A12 to A14, further including a step of forming an insulating layer on the oxide film after the thermal oxidation step, wherein the gate forming step is performed after the formation of the insulating layer. A method for manufacturing a semiconductor device.
According to this method, the insulating layer is formed on the oxide film, and the gate electrode on the insulating layer can be formed. Thereby, a gate insulating film having a required thickness can be disposed between the gate electrode and the electron transit layer. The insulating layer may be formed by, for example, an ALD (Atomic Layer Deposition) method.

A16. The method for manufacturing a nitride semiconductor device according to any one of Items A12 to A15, wherein the step of forming the electron supply layer includes a step of forming an AlN layer at an interface with the electron transit layer.
By this method, since the AlN layer is formed in contact with the electron transit layer, during thermal oxidation, nitrogen atoms (N) in the AlN layer are converted into oxygen atoms (O), and at the interface with the electron transit layer. The electron supply layer (AlN layer) can be reliably lost.

  A17. The step of forming the electron supply layer includes a step of forming a first layer in contact with the electron transit layer and a step of forming a second layer having a different Al composition from the first layer so as to be in contact with the first layer. The method for manufacturing a nitride semiconductor device according to any one of Items A12 to A16. The first layer may be an AlN layer. In this case, the second layer may be an AlGaN layer or an AlInN layer.

A18. The method for manufacturing a nitride semiconductor device according to Item A15, wherein the oxide film and the insulating layer are formed such that a film thickness of the oxide film is smaller than a layer thickness of the insulating layer.
In this method, even if the thickness of the oxide film is thin, the gate insulating film formed of the stacked film of the oxide film and the insulating layer can have a necessary thickness. Since the oxide film can be made thin, the electron supply layer directly under the gate electrode can be surely lost, and the damage to the interface with the electron transit layer due to the formation of the oxide film can be minimized. On the other hand, the dielectric breakdown voltage can be improved by forming the gate insulating film to a sufficient thickness.

1 Substrate 2 Buffer layer 3 Electron travel layer (GaN layer)
4 Electron supply layer (AlGaN layer)
41 First layer (AlN layer)
42 Second layer (AlGaN layer)
4t Thin part 5 Passivation film 6 Source electrode 7 Drain electrode 8 Gate electrode 9 Recess 9a Bottom 9b Side wall 10 Gate insulating film 11 Oxide film 11a Bottom covering part 11b Side wall covering part 12 Insulating layer 15 Two-dimensional electron gas 16 Resist film 17 Electrode film

Claims (10)

An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, has an Al composition different from that of the electron transit layer, and is made of a nitride semiconductor containing Al;
A first insulating film having an interface continuous with the interface between the electron supply layer and the electron transit layer and formed on the electron transit layer;
A gate electrode facing the electron transit layer across the first insulating film;
A second insulating film disposed so as to be interposed between the first insulating film and the gate electrode;
The electron supply layer has a recess recessed toward the electron transit layer;
The first insulating film is formed over the bottom and side walls of the recess, and includes a bottom covering portion that covers the bottom portion, and a side wall covering portion that covers the side wall,
The second insulating film is formed in contact with the first insulating film in the recess and extending to the outside of the recess;
The electron supply layer includes a first layer that is an AlN layer that is in contact with the electron transit layer, and a second layer that is stacked so as to be in contact with the first layer and has a different Al composition from the first layer,
The nitride semiconductor device, wherein the bottom covering portion is made of a thermal oxide of the first layer material.   The nitride semiconductor device according to claim 1, wherein a film thickness of the first insulating film is smaller than a film thickness of the second insulating film.   The nitride semiconductor device according to claim 1, wherein a film thickness of the second insulating film is larger than a layer thickness of the electron supply layer.   The nitride semiconductor device according to claim 1, wherein a nitrogen concentration in the first insulating film is higher than a nitrogen concentration in the second insulating film. The nitrogen concentration in the first insulating film is 5 × 10 ¹⁶ cm ⁻³ or more, and the nitrogen concentration in the second insulating film is less than 5 × 10 ¹⁶ cm ⁻³ . The nitride semiconductor device according to one item.   The nitride semiconductor device according to claim 1, wherein a film thickness of the first insulating film is 5 nm or less. The nitride semiconductor device according to claim 1, wherein the first insulating film contains nitrogen at a concentration of 5 × 10 ¹⁶ cm ⁻³ or more. Before Stories second layer consists Al _x Ga _1-x N layer (0 <x <1), the nitride semiconductor device according to any one of claims 1-7. The nitride semiconductor device according to any one of claims 1 to 8 , wherein the bottom surface covering portion is in contact with the electron transit layer and has a film thickness substantially equal to that of the first layer. Said second insulating film, made of aluminum oxide, a nitride semiconductor device according to any one of claims 1-9.

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