JP6016440B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device made of a group III nitride semiconductor (hereinafter sometimes simply referred to as “nitride semiconductor”) and a method for manufacturing the same.

The group III nitride semiconductor is a semiconductor using nitrogen as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are typical examples. In _general, it can be expressed as _{Al X In Y Ga 1-X} -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ X + Y ≦ 1).
HEMT (High Electron Mobility Transistor) using such a nitride semiconductor has been proposed. Such a HEMT includes, for example, an electron transit layer made of GaN and an electron supply layer made of AlGaN epitaxially grown on the electron transit layer. A pair of source and drain electrodes are formed in contact with the electron supply layer, and a gate electrode is disposed between them. The gate electrode is disposed so as to face the electron transit layer, and a Schottky junction in the electron supply layer. In the electron transit layer, a two-dimensional electron gas is formed at a position a few inches inward from the heterojunction interface between the electron transit layer and the electron supply layer. In a HEMT using a nitride semiconductor, carriers due to polarization due to lattice mismatch between GaN and AlGaN also contribute to the formation of a two-dimensional electron gas. The source and drain are connected using this two-dimensional electron gas as a channel. When a control voltage is applied to the gate electrode to expand the depletion layer due to the Schottky junction and block the two-dimensional electron gas, the source and drain are blocked. When the control voltage is not applied to the gate electrode, the source and drain are electrically connected, so that a normally-on type device is obtained.

  Patent Document 1 avoids alloy scattering caused by AlGaN having a ternary structure by forming an AlN layer having a binary structure having excellent crystallinity between the electron transit layer and the electron supply layer. Discloses a structure with improved mobility.

JP 2011-82216 A

The AlN layer disposed between the electron transit layer and the electron supply layer functions as a barrier layer when the channel is viewed from the source electrode and the drain electrode. Therefore, it is not easy to form the source electrode and the drain electrode on the surface of the electron supply layer that can obtain ohmic contact with the two-dimensional electron gas.
Therefore, in the structure of Patent Document 1, the source electrode and the drain electrode are embedded in a recess that penetrates the electron supply layer and the AlN layer and reaches the electron transit layer, thereby making ohmic contact with the two-dimensional electron gas. ing.

However, since the process of forming the recess is necessary, the manufacturing process is complicated, and the cost increases accordingly. Moreover, it is difficult to accurately control the depth of the recess formed by etching. Therefore, it is difficult to stabilize the depth of the recess, and the depth varies, and the contact resistance may vary accordingly.
Accordingly, an object of the present invention is to form a nitride semiconductor device having a HEMT structure, which can form an electrode that is in ohmic contact with a two-dimensional electron gas by a simple manufacturing process, has stable characteristics, and has high channel mobility. It is to provide a manufacturing method.

AlN This invention, and the electron transit layer made of a nitride semiconductor, which are laminated in the electron transit layer, the Al composition is different from the nitride semiconductor and the electron transit layer with containing Al, in contact with the electron transit layer An electron supply layer having a layer; a source electrode and a drain electrode formed on the electron supply layer at intervals from each other and made of an ohmic electrode containing Ti, Al, Mo, and Si; and the source electrode and the drain electrode disposed between said and a gate electrode opposed to the electron transit layer, that provides a nitride semiconductor device. In the ohmic electrode, a Ti composition peak, an Al composition peak, and a Mo composition peak appear in order from the electron supply layer side, and the first Si composition is between the Ti composition peak and the Al composition peak. And the second Si composition peak appears between the Al composition peak and the Mo composition peak.

  According to this configuration, the heterojunction is formed by contacting the electron transit layer and the electron supply layer made of nitride semiconductors having different Al compositions. Therefore, a two-dimensional electron gas is formed in the electron transit layer near the interface between the electron transit layer and the electron supply layer, and a HEMT (High Electron Mobility Transistor) using the two-dimensional electron gas as a channel is formed. . Furthermore, since the electron supply layer has an AlN layer at the interface with the electron transit layer, alloy scattering near the channel is suppressed. Thereby, a HEMT structure with high channel mobility can be formed.

  On the other hand, the source electrode and the drain electrode formed on the electron supply layer contain Ti, Al, Mo, and Si. Such a source electrode and a drain electrode constitute an ohmic electrode that is in ohmic contact with the two-dimensional electron gas even when formed on an electron supply layer including an AlN layer. That is, ohmic contact between the source and drain electrodes and the two-dimensional electron gas can be obtained without forming a recess that penetrates the electron supply layer and reaches the two-dimensional electron gas. Therefore, the manufacturing process is simplified because the step of forming the recess in the electron supply layer is unnecessary. Moreover, the problem of variation in contact resistance due to variation in the depth of the recess does not occur. Therefore, a nitride semiconductor device having a HEMT structure with high channel mobility and stable characteristics can be provided.

The two-dimensional electron gas that provides the source-drain channel can be controlled by applying a control voltage to the gate electrode disposed between the source and drain electrodes. Thereby, the source-drain can be turned on / off.
The gate electrode may be in Schottky junction with the electron supply layer, or may be opposed to the electron supply layer through a gate insulating film. Further, the electron supply layer directly under the gate may be removed to form a recess (recess), and the gate electrode may face the electron transit layer through the gate insulating film in the recess.

  The combination of the electron supply layer (portion other than the AlN layer at the interface) / electron transit layer is AlGaN layer / GaN layer, AlGaN layer / AlGaN layer (although different Al composition), AlInN layer / AlGaN layer, AlInN layer / GaN Any of a layer, an AlN layer / GaN layer, and an AlN layer / AlGaN layer may be used. More generally, the electron supply layer (portion other than the AlN layer at the interface) contains Al and N in the composition. The electron transit layer contains Ga and N in the composition, and the Al composition is different from that of the electron supply layer. Due to the difference in Al composition between the electron supply layer and the electron transit layer, lattice mismatch occurs between them, whereby carriers due to polarization contribute to the formation of a two-dimensional electron gas.

Meanwhile, in the invention of this, the ohmic electrode, in order from the electron supply layer side, the peak of the Ti composition, the Al composition peak, that is configured so that the peak of Mo composition appears. Ri by this configuration, the peak of the Ti composition appears near the electron supply layer. Therefore, Ti in the ohmic electrode near the surface of the electron supply layer takes away nitrogen atoms (N) in the nitride semiconductor constituting the electron supply layer, destroys its crystal structure, and forms TiN. As a result, Al in the ohmic electrode enters a space in the electron supply layer formed thereby to form a good ohmic contact with the two-dimensional electron gas. Since the peak of the Mo composition is located farther from the electron supply layer than the Al composition, Al in the ohmic electrode can be protected from oxidation, thereby reducing the contact resistance against external contact. That is, Ti and Al in the ohmic electrode contribute to a reduction in contact resistance with respect to the nitride semiconductor, and Mo contributes to a reduction in contact resistance during external connection.

In the invention Furthermore, the child, the ohmic electrode, that is configured so that the peak of the Si composition (peak of the first Si composition) appears between the peak of the peak and the Al composition of the Ti composition. Ri by this configuration, Si in the ohmic electrode, enters the surface layer portion of the electron supply layer, which functions as a dopant to impart electrical conductivity to nitride semiconductor constituting the electron supply layer. Thereby, since the contact resistance between an ohmic electrode and an electron supply layer is reduced, a better ohmic contact can be realized.

Further, in this invention, during the peak of the Mo composition with the peak of the Al composition, that have the ohmic electrode such that the peak of another Si composition (peak of the second Si composition) appear is formed. That is, the ohmic electrode has a first Si composition peak between the Ti composition peak and the Al composition peak, and a second Si composition peak between the Al composition peak and the Mo composition peak. peak of Si composition has been configured to appear.

Ti before Symbol ohmic electrodes in each peak density of Al and Mo is not less ¹⁰ 20 ^{cm -3} or more, the peak density of Si in the said ohmic electrode is preferably ¹⁰ 18 ^{cm -3} or more. Thereby, the contact resistance of the ohmic electrode with respect to the two-dimensional electron gas can be reduced.
In one embodiment of the present invention, the electron supply layer includes a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, and a source electrode and a drain electrode made of the ohmic electrode are formed on the cap layer. that has been formed. According to this configuration, since the cap layer formed on the electron supply layer is made of the nitride semiconductor having the same composition as the electron transit layer, the surface morphology of the electron supply layer can be improved. Thereby, a nitride semiconductor device having a HEMT structure with stable characteristics can be provided.

In one embodiment of the invention, the thickness is 16nm or less of the cap layer (more preferably 8nm or less) Ru der. When the thickness of the cap layer exceeds 16 nm, the effect of improving the surface morphology is reduced and the ohmic contact of the electrode may be hindered. The thickness of the cap layer is preferably 2 nm or more for improving the surface morphology.

In one embodiment of the present invention, the electron supply layer immediately below the gate electrode is removed, and the gate electrode is interposed via a gate insulating film in contact with the electron transit layer in a region where the electron supply layer is removed. It is opposed to the electron transit layer Te that.
According to this configuration, the gate electrode faces the electron transit layer with the gate insulating film interposed therebetween, and the gate insulating film is in contact with the electron transit layer. That is, there is no electron supply layer directly under the gate insulating film, and therefore, there is no two-dimensional electron gas due to polarization due to heterojunction or lattice mismatch between the electron supply layer and the electron transit layer immediately below the gate electrode. Is not formed. Therefore, when no bias is applied to the gate electrode (at the time of zero bias), the channel due to the two-dimensional electron gas is blocked immediately below the gate electrode. Thereby, a normally-off type HEMT is realized. When an appropriate ON voltage is applied to the gate electrode, a channel is induced in the electron transit layer immediately below the gate electrode, and the two-dimensional electron gas on both sides of the gate electrode is connected. Thus, a nitride semiconductor device having a normally-off HEMT structure and having stable device characteristics can be provided.

In one embodiment of the present invention, the thickness of the AlN layer is 1 nm to 5 nm, the thickness of the electron supply layer is Ru 1nm~40nm der. When the thickness of the AlN layer exceeds 5 nm, it becomes difficult to make the ohmic electrode ohmic contact with the two-dimensional electron gas. Moreover, if the total thickness of the electron supply layer exceeds 40 nm, ohmic contact between the ohmic electrode and the two-dimensional electron gas may be difficult.

In one embodiment of the present invention, the ohmic electrode, not including the Au. Au is a material in which impurities are easily mixed, and diffusion to a nitride semiconductor easily occurs, which may deteriorate device characteristics. In addition, the electrode containing Au has poor surface morphology. Therefore, a semiconductor device having a HEMT structure with excellent characteristics can be realized by using an ohmic electrode having a structure that does not contain Au. In addition, since the ohmic electrode has a good surface morphology, the distance from the source electrode and the drain electrode to the gate electrode can be shortened to reduce the size of the HEMT element or increase the degree of integration of the HEMT element. .

In one embodiment of the present invention , the semiconductor device further includes a passivation film that covers a surface of the electron supply layer, and the gate electrode is disposed in an opening formed in the passivation film, and the gate main body portion. A field plate portion extending over a predetermined field plate length toward the drain electrode on the surface of the passivation film outside the opening, and the field plate length is connected to the gate body portion. Ru der 1/6 to 1/2 of the distance between the drain electrode. According to this configuration, the gate electrode has the field plate portion extending on the passivation film from the gate main body portion, and the length (field plate length) is equal to the distance between the gate main body portion and the drain electrode. It is 1/6 or more and 1/2 or less. Thereby, the electric field concentration at the drain electrode side end of the gate body can be suppressed, and a short circuit (destruction of the passivation film) due to the electric field between the end of the field plate and the drain electrode can be avoided.

This invention also includes the steps of forming an electron transit layer formed of a nitride semiconductor, wherein a an AlN layer in contact with the electron transit layer, the nitride semiconductor Al composition different from the electron transit layer with an Al-containing A step of laminating an electron supply layer comprising the electron transit layer, and a Ti electrode, a first Si layer, an Al layer , a second Si layer, and a Mo layer, which are laminated on the electron supply layer in order. Forming a film; heat-treating the stacked electrode film to form an ohmic electrode as a source electrode and a drain electrode; and a gate facing the electron transit layer between the source electrode and the drain electrode and forming an electrode, to provide a method for manufacturing a nitride semiconductor device.

According to this method, after a Ti layer, a first Si layer, an Al layer , a second Si layer, and a Mo layer are sequentially stacked on the electron supply layer to form a stacked electrode film, heat treatment ( Preferably, a heat treatment for melting the Al layer is performed. As a result, Ti diffuses into the electron supply layer, takes nitrogen atoms from the nitride semiconductor in the electron supply layer, destroys the crystal structure, and forms TiN. Thereby, Al flows into the space formed in the electron supply layer, and a good ohmic contact with the two-dimensional gas formed near the interface between the electron transit layer and the electron supply layer is formed. Further, Si diffuses into the electron supply layer and functions as a dopant, contributing to the formation of a better ohmic contact (reduction of contact resistance). The Mo layer functions as a cap metal that prevents Al from being exposed during heat treatment and suppresses its oxidation. Thereby, it contributes to the reduction of the contact resistance at the time of external connection. Thus, the semiconductor device having the above-described configuration can be obtained.

The thickness of the AlN layer is preferably 1 nm to 5 nm, and the total thickness of the electron supply layer is preferably 1 nm to 40 nm.

The ohmic electrode preferably does not contain Au.
In the manufacturing method according to an embodiment of the present invention, in the formation of the laminated electrode film and the heat treatment, each peak density of Ti, Al, and Mo in the ohmic electrode is 10 ²⁰ cm ⁻³ or more, and the ohmic electrode peak density of Si in the Ru performed such that the ¹⁰ 18 ^{cm -3} or more.

In the manufacturing method of one embodiment of the present invention, the step of forming the electron supply layer includes the step of forming a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, and the stacked electrode film is Ru is formed on the cap layer. The thickness of the cap layer is preferably 16 nm or less (more preferably 8 nm or less).

In the manufacturing method of one embodiment of the present invention, the step of removing the electron supply layer immediately below the gate electrode and the step of forming a gate insulating film in contact with the electron transit layer in the region where the electron supply layer is removed further comprising the door, the gate electrode is Ru is formed so as to face the electron transit layer sandwiching the gate insulating film.

In the manufacturing method of an embodiment of the present invention, the method, further includes the step of forming a passivation film covering the surface of the electron supply layer, disposed on the gate electrode, the passivation film which is formed on the opening And a field plate portion extending over a predetermined field plate length toward the drain electrode on the surface of the passivation film outside the opening and continuous with the gate body portion, field plate length Ru is formed to be a 1/6 to 1/2 of the distance between the drain electrode and the gate body portion.

FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the nitride semiconductor device according to the first embodiment. FIG. 3A is a cross-sectional view showing the configuration in the middle of the manufacturing process of the nitride semiconductor device of FIG. FIG. 3B is a cross-sectional view showing a configuration at a later stage of FIG. 3A. FIG. 3C is a cross-sectional view showing a configuration at a later stage of FIG. 3B. FIG. 4 shows the structure of the laminated electrode film for forming the ohmic electrode and the composition spectrum of the ohmic electrode. FIG. 5 is a schematic cross-sectional view for illustrating the configuration of a nitride semiconductor device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to the third embodiment of the present invention. FIG. 7A is a cross-sectional view showing a configuration in the middle of the manufacturing process of the nitride semiconductor device of FIG. FIG. 7B is a cross-sectional view showing a configuration at a later stage of FIG. 7A. FIG. 7C is a cross-sectional view showing a configuration at a later stage of FIG. 7B. FIG. 7D is a cross-sectional view showing a configuration at a later stage of FIG. 7C. FIG. 7E is a cross-sectional view showing a configuration at a later stage of FIG. 7D. FIG. 7F is a cross-sectional view showing a configuration at a later stage of FIG. 7E. FIG. 8 is a schematic cross-sectional view for explaining the configuration of a nitride semiconductor device according to the fourth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the nitride semiconductor device. FIG. 1 shows a cross section taken along line II of FIG. The nitride semiconductor device includes a substrate 1 (for example, a silicon substrate), a buffer layer 2 formed on the surface of the substrate 1, an electron transit layer 3 epitaxially grown on the buffer layer 2, and an epitaxial growth on the electron transit layer 3. And the electron supply layer 4 formed. Further, the nitride semiconductor device includes a passivation film 5 that covers the surface of the electron supply layer 4 and an ohmic electrode that is in ohmic contact with the electron supply layer 4 through the contact holes 6 a and 7 a formed in the passivation film 5. Source electrode 6 and drain electrode 7. The source electrode 6 and the drain electrode 7 are arranged at an interval, and the gate electrode 8 is arranged between them. The gate electrode 8 is in Schottky contact with the electron supply layer 4.

The electron transit layer 3 and the electron supply layer 4 are made of group III nitride semiconductors (hereinafter simply referred to as “nitride semiconductors”) having different Al compositions. For example, the electron transit layer 3 may be composed of a GaN layer, and the thickness thereof may be about 0.5 μm. In this embodiment, the electron supply layer 4 has a first layer 41 in contact with the electron transit layer 3 and a second layer 42 in contact with the first layer 41. The first layer 41 is made of an AlN layer, and has a thickness of, for example, about several atomic thickness (5 nm or less, preferably 1 to 5 nm, more preferably 1 to 3 nm). In this embodiment, the second layer 42 is composed of an Al _x Ga _1-x N layer (0 <x <1), and has a thickness of, for example, 5-35 nm (more specifically, about 20 nm). is there. The total thickness of the electron supply layer 4 is preferably about 1 to 40 nm.

  Thus, the electron transit layer 3 and the electron supply layer 4 are made of nitride semiconductors having different Al compositions, form a heterojunction, and have a lattice mismatch between them. Then, due to polarization caused by the heterojunction and lattice mismatch, two-dimensional electrons are located at a position close to the interface between the electron transit layer 3 and the electron supply layer 4 (for example, a position about several kilometers away from the interface). Gas 15 is spreading. The first layer 41 made of AlN suppresses electron scattering and contributes to improvement of electron mobility. When the first layer 41 is not present and the second layer 42 made of AlGaN is in contact with the electron transit layer 3, alloy scattering is likely to occur because AlGaN is a ternary crystal. The first layer 41 made of AlN suppresses such alloy scattering.

  The gate electrode 8 is in contact with the second layer 42 made of AlGaN to form a Schottky junction. The gate electrode 8 may be composed of a laminated electrode film having a lower layer in contact with the electron supply layer 4 and an upper layer laminated on the lower layer. The lower layer may be made of Ni or Pt, and the upper layer may be made of Au or Al. The gate electrode 8 is biased toward the source electrode 6 and has an asymmetric structure in which the gate-drain distance is longer than the gate-source distance. This asymmetric structure alleviates a high electric field generated between the gate and the drain and contributes to an improvement in breakdown voltage.

  Further, in this embodiment, the gate electrode 8 is connected to the gate main body 81 that enters the opening 5 a formed in the passivation film 5 and the gate main body 81, and the drain electrode 7 is formed on the passivation film 5 outside the opening 5 a. And a field plate portion 82 extending toward the bottom. The distance Lfp (for example, about 2.25 μm) from the drain end 81a, which is the end on the drain electrode 7 side, at the interface between the gate body 81 and the electron supply layer 4 to the end on the drain electrode 7 side of the field plate portion 82 is , Called field plate length. Field plate length Lfp is preferably 1/6 or more and 1/2 or less of distance Lgd (for example, about 9 μm) from drain end 81a to drain electrode 7. Thereby, the electric field concentration at the drain end 81 a can be relaxed, and the destruction of the passivation film 5 due to the electric field between the drain side end of the field plate portion 82 and the drain electrode 7 can be avoided.

The source electrode 6 and the drain electrode 7 are ohmic electrodes containing Ti, Al, Mo, and Si, and are in ohmic contact with the two-dimensional electron gas formed in the electron transit layer 41. The detailed configuration of this ohmic electrode will be described later.
The buffer layer 2 may be, for example, an AlGaN layer or a layer having a superlattice structure in which an AlN layer and a GaN layer are repeatedly stacked.

  In this nitride semiconductor device, an electron supply layer 4 having a different Al composition is formed on the electron transit layer 3 to form a heterojunction. Thereby, a two-dimensional electron gas 15 is formed in the electron transit layer 3 in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4, and a HEMT using the two-dimensional electron gas 15 as a channel is formed. The gate electrode 8 is in Schottky junction with the electron supply layer 4. When an appropriate voltage is applied to the gate electrode 8, the electron supply layer 4 can be depleted by the depletion layer extending from the heterojunction and the depletion layer extending from the Schottky junction, and thereby the channel formed by the two-dimensional electron gas 15. Can be cut off. Therefore, by applying a control voltage to the gate electrode 8, the source-drain can be turned on / off.

In use, for example, a predetermined voltage (for example, 200 V to 600 V) that is positive on the drain electrode 7 side is applied between the source electrode 6 and the drain electrode 7. In this state, an off voltage (−5 V) or an on voltage (0 V) is applied to the gate electrode 8 with the source electrode 6 as a reference potential (0 V).
As shown in FIG. 2, in plan view, the junction region (source junction region, region in the contact hole 6 a) Sa between the source electrode 6 and the electron supply layer 4, the drain electrode 7, and the electron supply layer 4 The gate electrode 8 is routed so as to separate the junction region (drain junction region; region in the contact hole 7a) Da. In other words, the junction region (gate junction region, region in the opening 5a) Ga between the gate body 81 of the gate electrode 8 and the electron supply layer 4 has a band shape having a constant width that separates the source junction region Sa and the drain junction region Da. It is formed in a pattern. More specifically, the source junction region Sa and the drain junction region Da are rectangular regions whose longitudinal directions are parallel, and are arranged along the short direction of the rectangular regions. The gate junction region Ga is formed in a zigzag shape that passes between the source junction region Sa and the drain junction region Da. The gate junction region Ga is disposed so as to pass through a position closer to the source junction region Sa than to the drain junction region Da. The distance between the gate junction region Ga and the edge of the gate electrode 8 on the drain junction region Da side is the field plate length Lfp. The width of the gate junction region Ga is a gate length Lg (for example, about 1 μm).

3A to 3C are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device described above, and show cross-sectional structures at a plurality of stages in the manufacturing process.
First, as shown in FIG. 3A, the buffer layer 2 and the electron transit layer 3 are epitaxially grown in order on the substrate 1, and the electron supply layer 4 is further epitaxially grown on the electron transit layer 3. Further, a passivation film 5 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface of the electron supply layer 4. The passivation film 5 may be made of silicon nitride (SiN), and the film thickness is suitably about several hundred nm. The epitaxial growth of the electron supply layer 4 includes a step of epitaxially growing a first layer 41 made of AlN on the electron transit layer 3 and a step of epitaxially growing a second layer 42 made of AlGaN on the first layer 41.

  Next, as shown in FIG. 3B, the source electrode 6 and the drain electrode 7 are formed. Specifically, contact holes 6a and 7a penetrating the passivation film 5 are formed so as to match the formation positions thereof, and then a laminated electrode film 30 as shown in FIG. 4 is formed. For example, the stacked electrode film 30 includes a Ti layer 31 (for example, a thickness of 200 mm), a first Si layer 32 (for example, a thickness of 200 mm), an Al layer 33 (for example, a thickness of 2000 mm), a second Si layer 34 ( For example, it is formed of a laminated metal film in which a thickness of 200 mm and a Mo layer (for example, thickness of 2000 mm) 35 are sequentially laminated, and each layer is formed by vapor deposition or sputtering in order. The laminated electrode film 30 is patterned. The patterning of the laminated electrode film 30 may be performed by lift-off or may be performed by etching. After this patterning, a sinter process is further performed to form the source electrode 6 and the drain electrode 7 that are in ohmic contact with the two-dimensional electron gas 15. The sintering process is preferably performed so that the Al layer 33 is melted, and is performed at a temperature (for example, 850 ° C.) higher than the melting point of Al (565 ° C.). Specifically, the sintering process may be performed at 850 ° C. for about 35 minutes.

  Next, as shown in FIG. 3C, a resist film 16 having an opening is formed at the position where the gate electrode 8 is formed, and an electrode film 17 is formed so as to cover the entire surface in that state. The opening of the resist film 16 includes a region of the opening 5a formed in the passivation film 5 and is formed in a region wider than the region of the opening 5a. The edge of the opening of the resist film 16 on the drain electrode 7 side is set back by the field plate length Lfp from the drain side end of the opening 5 a of the passivation film 5 toward the drain electrode 7. The electrode film 17 is made of, for example, a laminated metal film in which a lower layer made of Ni or Pt and an upper layer made of Au or Al are laminated, and each layer is deposited in order.

  Next, the electrode film 17 on the resist film 16 (unnecessary portion of the electrode film 17) is lifted off together with the resist film 16, whereby the electrode film 17 is patterned and the gate electrode 8 is obtained. Thus, the nitride semiconductor device having the structure shown in FIG. 1 is obtained. Thereafter, the entire surface is covered with an interlayer insulating film, and contact holes for exposing the source electrode 6 and the drain electrode 7 are formed in the interlayer insulating film. A source wiring and a drain wiring connected to the source electrode 6 and the drain electrode 7 through contact holes, respectively, are formed on the interlayer insulating film.

The right side of FIG. 4 schematically shows a spectrum representing the composition of the ohmic electrodes (source electrode 6 and drain electrode 7) after sintering. The vertical axis represents the position of the main surface of the electron supply layer 4 in the normal direction, and the horizontal axis represents the number of atoms (density) per unit volume.
The ohmic electrodes 6 and 7 are configured such that the Ti composition peak, the Al composition peak, and the Mo composition peak appear in this order from the electron supply layer 4 side so as to follow the stacking order of the stacked electrode film 30. Furthermore, the first peak of the Si composition appears between the peak of the Ti composition and the peak of the Al composition. In addition, a second peak of the Si composition appears between the peak of the Al composition and the peak of the Mo composition. Each peak density of Ti, Al and Mo in the ohmic electrodes 6 and 7 is, for example, 10 ²⁰ cm ⁻³ or more, and the peak density of Si in the ohmic electrodes 6 and 7 is, for example, 10 ¹⁸ cm ⁻³ or more.

  The Ti composition penetrates into the electron supply layer 4. For example, the peak of the Ti composition is located in the electron supply layer 4. That is, Ti in the laminated electrode film 30 enters the electron supply layer 4 by the sintering process, takes nitrogen atoms (N) from AlGaN, breaks the crystal, and forms TiN. The molten Al flows from the laminated electrode film 30 into the space in the crystal formed thereby. Therefore, the Al composition also enters the electron supply layer 4, thereby obtaining a good ohmic contact. Furthermore, Si in the laminated electrode film 30 diffuses into the electron supply layer 4 and acts as an n-type dopant, thereby reducing the resistance of AlGaN immediately below the ohmic electrode, thereby contributing to a reduction in contact resistance. The Mo layer functions as a cap metal that prevents oxidation of the Al surface during heat treatment or the like, and contributes to a reduction in contact resistance during external connection.

  As described above, according to this embodiment, since the electron supply layer 4 has the first layer 41 made of AlN at the interface with the electron transit layer 3, alloy scattering near the channel is suppressed. . Thereby, a HEMT structure with high channel mobility can be formed. On the other hand, the source electrode 6 and the drain electrode 7 contain Ti, Al, Mo, and Si, and are in ohmic contact with the two-dimensional electron gas 15 without forming a recess penetrating the electron supply layer 4. Thereby, it can be manufactured by a simple manufacturing process that does not include a step for forming a recess in the electron supply layer 4, and there is no problem of variation in contact resistance due to variation in the depth of the recess. Thus, a nitride semiconductor device having a HEMT structure with high channel mobility, easy manufacturing process, and stable characteristics can be provided.

  Further, since the source electrode 6 and the drain electrode 7 are ohmic electrodes that do not contain Au, the surface morphology is good, which also contributes to the improvement of the characteristics of the HEMT structure. Furthermore, since the surface morphology of the source electrode 6 and the drain electrode 7 is good, the distance from them to the gate electrode 8 is shortened to reduce the size of the HEMT element, or to increase the integration degree of the HEMT element. be able to.

FIG. 5 is a schematic cross-sectional view for illustrating the configuration of a nitride semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same reference numerals are given to corresponding portions of the respective parts in FIG. 1 described above.
In this embodiment, the electron supply layer 4 includes a third layer 43 as a cap layer formed on the second layer 42 made of AlGaN. A source electrode 6 and a drain electrode 7 made of ohmic electrodes and a gate electrode 8 made of a Schottky electrode are formed so as to be in contact with the third layer 43.

The third layer 43 is made of GaN, which is a nitride semiconductor having the same composition as the electron transit layer 3, and has a thickness of 16 nm or less (more preferably 8 nm or less).
Also in this configuration, the source electrode 6 and the drain electrode 7 are formed in the two-dimensional electron gas 15 without forming a recess penetrating the electron supply layer 4 by forming an ohmic electrode in the same manner as in the first embodiment. Can make ohmic contact. The third layer 43 as the cap layer contributes to the improvement of the surface morphology of the electron supply layer 4. That is, the second layer 42 made of AlGaN having a different lattice constant is formed on the surface of the electron transit layer 3 made of GaN, and since AlGaN is a ternary crystal, the crystallinity is not necessarily good. Therefore, when the second layer 42 is the outermost surface of the electron supply layer 4, the surface morphology is not always good, and the device characteristics are not stabilized accordingly. Therefore, by laminating the third layer 43, which is a cap layer having the same composition as the electron transit layer 3, on the second layer 42, the surface morphology of the electron supply layer 4 can be improved, thereby improving the device characteristics. However, if the third layer 43 is made too thick, the effect of improving the surface morphology is reduced and the ohmic contact between the source electrode 6 and the drain electrode 7 is adversely affected, so the thickness is 16 nm or less (more preferably 8 nm or less).

FIG. 6 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to the third embodiment of the present invention. Also in the description of this embodiment, the same reference numerals are used for corresponding parts to the constituent parts shown in the first embodiment. Since the structure in plan view is the same as that of the first embodiment, FIG. 4 is also referred to.
The nitride semiconductor device according to the third embodiment includes a substrate 1 (for example, a silicon substrate), a buffer layer 2 formed on the surface of the substrate 1, an electron transit layer 3 epitaxially grown on the buffer layer 2, and an electron And an electron supply layer 4 epitaxially grown on the traveling layer 3. Further, the nitride semiconductor device includes a passivation film 5 that covers the surface of the electron supply layer 4, and a source electrode that is in ohmic contact with the electron supply layer 4 through the contact holes 6 a and 7 a formed in the passivation film 5. 6 and the drain electrode 7. The source electrode 6 and the drain electrode 7 are arranged at an interval, and the gate electrode 8 is arranged between them.

  The electron supply layer 4 is formed with a recess 9 dug from the surface toward the electron transit layer 3. An oxide film 11 is formed so as to cover bottom 9a and side wall 9b of recess 9. An insulating layer 12 is laminated on the oxide film 11, and the gate insulating film 10 is constituted by the oxide film 11 and the insulating layer 12. The gate electrode 8 faces the electron transit layer 3 at the bottom 9a of the recess 9 with the gate insulating film 10 interposed therebetween. Since the oxide film 11 extends so as to cover not only the bottom 9a of the recess 9 but also the side wall 9b, a leak path can be reduced.

The electron transit layer 3 and the electron supply layer 4 are made of group III nitride semiconductors (hereinafter simply referred to as “nitride semiconductors”) having different Al compositions. For example, the electron transit layer 3 may be composed of a GaN layer, and the thickness thereof may be about 0.5 μm. In this embodiment, the electron supply layer 4 has a first layer 41 in contact with the electron transit layer 3 and a second layer 42 in contact with the first layer 41. In this embodiment, the first layer 41 is made of an AlN layer, and has a thickness of, for example, about several atomic thickness (5 nm or less, preferably 1 to 5 nm, more preferably 1 to 3 nm). In this embodiment, the second layer 42 is composed of an Al _x Ga _1-x N layer (0 <x <1), and has a thickness of about 20 nm, for example.

  Thus, the electron transit layer 3 and the electron supply layer 4 are made of nitride semiconductors having different Al compositions, form a heterojunction, and have a lattice mismatch between them. Due to the polarization due to the heterojunction and lattice mismatch, the position close to the interface between the electron transit layer 3 and the electron supply layer 4 (for example, a position about several kilometers away from the interface) is attributed to the polarization. The two-dimensional electron gas 15 is spread. The first layer 41 made of AlN suppresses electron scattering and contributes to improvement of electron mobility. When the first layer 41 is not present and the second layer 42 made of AlGaN is in contact with the electron transit layer 3, alloy scattering is likely to occur because AlGaN is a ternary crystal. The first layer 41 made of AlN suppresses such alloy scattering.

  At the bottom 9 a of the recess 9, the oxide film 11 has a film thickness almost equal to that of the first layer 41 of the electron supply layer 4. Specifically, the oxide film 11 has a thickness of 5 nm or less, preferably 1 to 5 nm, more preferably 1 to 3 nm. The oxide film 11 is in contact with the electron transit layer 3, and the interface between the oxide film 11 and the electron transit layer 3 is located in the same plane as the interface between the electron supply layer 4 and the electron transit layer 3. In other words, the interface between the oxide film 11 and the electron transit layer 3 is continuous with the interface between the electron supply layer 4 and the electron transit layer 3.

In this embodiment, the oxide film 11 is a thermal oxide film, and is an oxide film formed without damaging the interface with the electron transit layer 3. The oxide film 11 contains nitrogen at a concentration higher than the nitrogen concentration in the insulating layer 12. More specifically, the nitrogen concentration in the oxide film 11 is 5 × 10 ¹⁶ cm ⁻³ or more, and the nitrogen concentration in the insulating layer 12 is less than 5 × 10 ¹⁶ cm ⁻³ . More specifically, the oxide film 11 has a higher nitrogen concentration in the bottom cover portion 11a in contact with the bottom portion 9a of the recess 9, and the nitrogen concentration in the bottom cover portion 11a is 5 × 10 ¹⁶ cm ⁻³ or more. It is higher than the nitrogen concentration in the side wall covering portion 11b that covers the side wall 9b of the recess 9.

  The insulating layer 12 is made of, for example, aluminum oxide (alumina), and is thicker than the oxide film 11 (for example, may be thicker than the electron supply layer 4). Thereby, even if the oxide film 11 is thin, the gate insulating film 10 having a required film thickness is formed together with the oxide film 11, which contributes to the improvement of the dielectric breakdown voltage. In this embodiment, the insulating layer 12 is formed so as to be in contact with the oxide film 11 in the recess 9 and further to the outside of the recess 9. Thereby, the pressure | voltage resistance is further improved.

  The gate electrode 8 is formed in contact with the insulating layer 12. The gate electrode 8 may be composed of a laminated electrode film having a lower layer in contact with the insulating layer 12 and an upper layer laminated on the lower layer. The lower layer may be made of Ni or Pt, and the upper layer may be made of Au or Al. The gate electrode 8 is biased toward the source electrode 6 and has an asymmetric structure in which the gate-drain distance is longer than the gate-source distance. This asymmetric structure alleviates a high electric field generated between the gate and the drain and contributes to an improvement in breakdown voltage.

  Furthermore, in this embodiment, the gate electrode 8 enters the opening 5a formed in the passivation film 5, and further continues to the gate body 81 and the gate body 81 that enters the recess 9, and the passivation film is outside the opening 5a. 5 has a field plate portion 82 extending toward the drain electrode 7. The distance Lfp (for example, about 2.25 μm) from the drain end 81a, which is the end on the drain electrode 7 side at the lower end of the gate body portion 81, to the end on the drain electrode 7 side of the field plate portion 82 is the field plate length. . Field plate length Lfp is preferably 1/6 or more and 1/2 or less of distance Lgd (for example, about 9 μm) from drain end 81a to drain electrode 7. Thereby, electric field concentration at the drain end 81a can be relaxed, and destruction of the passivation film 5 due to the electric field between the drain side end of the field plate portion 81 and the drain electrode 7 can be avoided.

The source electrode 6 and the drain electrode 7 are ohmic electrodes described in detail in the first embodiment, and are in ohmic contact with the two-dimensional electron gas 15.
The buffer layer 2 may be, for example, an AlGaN layer or a layer having a superlattice structure in which an AlN layer and a GaN layer are repeatedly stacked.
In this nitride semiconductor device, an electron supply layer 4 having a different Al composition is formed on the electron transit layer 3 to form a heterojunction. Thereby, a two-dimensional electron gas 15 is formed in the electron transit layer 3 in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4, and a HEMT using the two-dimensional electron gas 15 as a channel is formed. The gate electrode 8 faces the electron transit layer 3 with the gate insulating film 10 formed of a laminated film of the oxide film 11 and the insulating layer 12 interposed therebetween, and the electron supply layer 4 does not exist immediately below the gate electrode 8. Therefore, the two-dimensional electron gas 15 due to polarization due to lattice mismatch between the electron supply layer 4 and the electron transit layer 3 is not formed immediately below the gate electrode 8. Therefore, when no bias is applied to the gate electrode 8 (at the time of zero bias), the channel formed by the two-dimensional electron gas 15 is blocked immediately below the gate electrode 8. In this way, a normally-off HEMT is realized. When an appropriate ON voltage (for example, 5 V) is applied to the gate electrode 8, a channel is induced in the electron transit layer 3 immediately below the gate electrode 8, and the two-dimensional electron gas 15 on both sides of the gate electrode 8 is connected. Thereby, conduction between the source and the drain is established.

In use, for example, a predetermined voltage (for example, 200 V to 400 V) that is positive on the drain electrode 7 side is applied between the source electrode 6 and the drain electrode 7. In this state, an off voltage (0 V) or an on voltage (5 V) is applied to the gate electrode 8 with the source electrode 6 as a reference potential (0 V).
The interface between the oxide film 11 and the electron transit layer 3 is continuous with the interface between the electron supply layer 4 and the electron transit layer 3, and the state of the interface of the electron transit layer 3 immediately below the gate electrode 8 is the electron supply layer. 4 and the state of the interface between the electron transit layer 3. Therefore, the electron mobility in the electron transit layer 3 immediately below the gate electrode 8 is kept high. In addition, since a sufficiently high on-voltage can be applied to the gate electrode 8, the device characteristics when the on-voltage is applied to the gate electrode 8 are also good.

Thus, this embodiment provides a nitride semiconductor device having a normally-off HEMT structure and having excellent device characteristics.
In addition, also in the third embodiment, the effects described in relation to the first embodiment can be obtained, and the source electrode 6 and the drain electrode can be formed without forming a recess penetrating the electron supply layer 4. 7 can be brought into ohmic contact with the two-dimensional electron gas 15.

7A to 7F are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device according to the third embodiment, and show cross-sectional structures at a plurality of stages in the manufacturing process.
First, as shown in FIG. 7A, the buffer layer 2 and the electron transit layer 3 are epitaxially grown on the substrate 1 in this order, and the electron supply layer 4 is further epitaxially grown on the electron transit layer 3. Further, a passivation film 5 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface of the electron supply layer 4. The passivation film 5 may be made of silicon nitride (SiN), and the film thickness is suitably about several hundred nm. The epitaxial growth of the electron supply layer 4 includes a step of epitaxially growing a first layer 41 made of AlN on the electron transit layer 3 and a step of epitaxially growing a second layer 42 made of AlGaN on the first layer 41.

  Next, as shown in FIG. 7B, a recess 9 is formed in the electron supply layer 4 in accordance with the formation position of the gate electrode 8. Specifically, a mask having an opening is formed at a position where the concave portion 9 is to be formed, the passivation film 5 is opened by dry etching through the mask, and a part of the electron supply layer 4 is etched, A recess 9 that is recessed from the surface of the electron supply layer 4 toward the electron transit layer 3 is formed. At this time, a thin part 4 t having a thickness of 5 nm or less (preferably 1 to 5 nm, more preferably 1 to 3 nm) is left on the bottom 9 a of the recess 9, which is thinner than the electron supply layer 4 outside the recess 9. This thin part 4t may consist of only the first layer 41 (AlN layer), or may include a part of the second layer 42 (AlGaN layer) in addition to the first layer 41.

Next, as shown in FIG. 7C, an oxide film 11 is formed by a thermal oxidation process performed while flowing an oxygen gas in a thermal oxidation furnace. This thermal oxidation treatment is performed so that the thin portion 4t is converted into the oxide film 11 over and over the entire thickness. In the first layer (AlN layer) included in the thin part 4t, nitrogen atoms (N) are replaced with oxygen atoms (O) by thermal oxidation treatment, and Al _a O _b (where a and b are positive real numbers) To an oxide film. As a result, at the bottom 9 a of the recess 9, the interface between the electron supply layer 4 and the electron transit layer 3 disappears and instead becomes an interface between the oxide film 11 and the electron transit layer 3.

This interface is an interface formed by thermal oxidation, and is an extremely good interface formed without being exposed to the atmosphere even during the manufacturing process. Therefore, the electron mobility in the electron transit layer 3 immediately below the interface has the same high value as the other portions. Thereby, a low on-resistance and a high switching speed can be realized.
Since the thermal oxidation process proceeds not only at the bottom 9a of the recess 9 but also at the side wall 9b exposed to the oxygen atmosphere, the oxide film 11 is formed to cover the bottom 9a and further extend to the side wall 9b. . The bottom covering portion 11a of the oxide film 11 includes a portion converted from the first layer 41 made of an AlN layer, and the side wall covering portion 11b is changed from the second layer 42 made of an AlGaN layer to an oxide film. Therefore, the oxide film 11 contains nitrogen, and the nitrogen concentration in the bottom covering portion 11a is higher than the nitrogen concentration in the side wall covering portion 11b.

Next, as shown in FIG. 7D, the insulating layer 12 is formed so as to cover the entire exposed surface. Therefore, the insulating layer 12 is formed in contact with the oxide film 11 in the recess 9 and extending to a region outside the recess 9. The insulating layer 12 is preferably an insulating film of the same type as the oxide film 11, and may be made of alumina (Al ₂ O ₃ ), for example. Such an insulating layer 12 can be formed by, for example, an ALD (Atomic Layer Deposition) method.

  Next, as shown in FIG. 7E, the source electrode 6 and the drain electrode 7 are formed. Specifically, contact holes 6a and 7a penetrating the insulating layer 12 and the passivation film 5 are formed so as to match the formation positions thereof, and then the source electrode 6 is formed in the same manner as in the first embodiment. And the drain electrode 7 is formed (refer FIG. 4). The source electrode 6 and the drain electrode 7 are ohmic electrodes that are in ohmic contact with the two-dimensional electron gas 15.

  Next, as shown in FIG. 7F, a resist film 16 having an opening at the position where the gate electrode 8 is formed is formed, and an electrode film 17 is formed so as to cover the entire surface in that state. The opening of the resist film 16 includes a region of the opening 5a formed in the passivation film 5 and is formed in a region wider than the region of the opening 5a. The edge of the opening of the resist film 16 on the drain electrode 7 side is set back by the field plate length Lfp from the drain side end of the opening 5 a of the passivation film 5 toward the drain electrode 7. The electrode film 17 is made of, for example, a laminated metal film in which a lower layer made of Ni or Pt and an upper layer made of Au or Al are laminated, and each layer is deposited in order.

  Next, the electrode film 17 on the resist film 16 (unnecessary portion of the electrode film 17) is lifted off together with the resist film 16, whereby the electrode film 17 is patterned and the gate electrode 8 is obtained. Thus, the nitride semiconductor device having the structure shown in FIG. 1 is obtained. Thereafter, the entire surface is covered with an interlayer insulating film, and contact holes for exposing the source electrode 6 and the drain electrode 7 are formed in the interlayer insulating film. A source wiring and a drain wiring connected to the source electrode 6 and the drain electrode 7 through contact holes, respectively, are formed on the interlayer insulating film.

FIG. 8 is a schematic cross-sectional view for explaining the configuration of a nitride semiconductor device according to the fourth embodiment of the present invention. In FIG. 8, the same reference numerals are assigned to the corresponding portions of the respective parts in FIGS. 5 and 6 described above.
In this embodiment, as in the case of the second embodiment shown in FIG. 5, the electron supply layer 4 includes a third layer 43 as a cap layer formed on the second layer 42 made of AlGaN. A source electrode 6 and a drain electrode 7 made of ohmic electrodes are formed in contact with the third layer 43. The passivation film 5 is formed on the third layer 43.

The third layer 43 is made of GaN, which is a nitride semiconductor having the same composition as the electron transit layer 3, and has a thickness of 16 nm or less (more preferably 8 nm or less).
Also in this configuration, the source electrode 6 and the drain electrode 7 are formed in the two-dimensional electron gas 15 without forming a recess penetrating the electron supply layer 4 by forming an ohmic electrode in the same manner as in the third embodiment. Can make ohmic contact. The third layer 43 as the cap layer contributes to the improvement of the surface morphology of the electron supply layer 4.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form .

For example , in the above-described embodiment, the example in which the electron transit layer 3 is made of a GaN layer and the electron supply layer 4 includes the first layer 41 made of AlN and the second layer 42 made of AlGaN has been described. The electron supply layer 4 only needs to have a different Al composition, and other combinations are possible. For example, as the combination of the electron transit layer 3 / the first layer 41 / the second layer 42, GaN / AlN / AlGaN, Al _m Ga _1-m N / AlN / Al _n Ga _1-n N (where m ≠ n ), AlGaN / AlN / AlInN, GaN / AlN / AlInN, GaN / AlN / AlN, AlGaN / AlN / AlN, and the like. Of course, when the first layer 41 and the second layer 42 are both AlN layers, it is not necessary to distinguish the first layer 41 and the second layer 42.

  In the third and fourth embodiments described above, even when the second layer 42 is other than AlN, an oxide film is formed on the bottom 9a of the recess 9 without necessarily providing the first layer made of AlN. be able to. However, by providing the AlN layer so as to be in contact with the electron transit layer 3, the scattering of electrons can be suppressed, the electron mobility can be increased, and the oxide film 11 in contact with the electron transit layer 3 can be reliably formed by a thermal oxidation method. There is an advantage that can be formed.

In the third and fourth embodiments described above, the gate insulating film 10 is composed of two layers of the oxide film 11 and the insulating layer 12, but the gate insulating film 10 is formed by stacking three or more insulating films. It is good also as a structure which increased the dielectric breakdown voltage.
In the above-described embodiment, silicon is exemplified as a material example of the substrate 1, but any other substrate material such as a sapphire substrate or a GaN substrate can be applied.

In addition, various design changes can be made within the scope of matters described in the claims.
Examples of features derived from the description of this specification and the accompanying drawings are listed below.
1. An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, includes Al and is made of a nitride semiconductor having an Al composition different from that of the electron transit layer, and has an AlN layer in contact with the electron transit layer;
A source electrode and a drain electrode, which are formed on the electron supply layer at intervals from each other and are made of ohmic electrodes including Ti, Al, Mo and Si;
A nitride semiconductor device including a gate electrode disposed between the source electrode and the drain electrode and facing the electron transit layer.
2. The nitride semiconductor device according to Item 1, wherein the ohmic electrode is configured such that a peak of Ti composition, a peak of Al composition, and a peak of Mo composition appear in order from the electron supply layer side.
3. Item 3. The nitride semiconductor device according to Item 2, wherein the ohmic electrode is configured such that a Si composition peak appears between the Ti composition peak and the Al composition peak.
4). Any one of Items 1 to 3 , wherein each of the peak densities of Ti, Al, and Mo in the ohmic electrode is 10 ²⁰ cm ⁻³ or more, and a peak density of Si in the ohmic electrode is 10 ¹⁸ cm ⁻³ or more. The nitride semiconductor device according to one item.
5. Item 1-4, wherein the electron supply layer includes a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, and a source electrode and a drain electrode made of the ohmic electrode are formed on the cap layer. The nitride semiconductor device according to any one of the above.
6). Item 6. The nitride semiconductor device according to Item 5, wherein the cap layer has a thickness of 16 nm or less.
7). The electron supply layer directly under the gate electrode is removed, and the gate electrode is opposed to the electron transit layer through a gate insulating film in contact with the electron transit layer in a region where the electron supply layer is removed. The nitride semiconductor device according to any one of Items 1 to 6.
8). Item 8. The nitride semiconductor device according to any one of Items 1 to 7, wherein the thickness of the AlN layer is 1 nm to 5 nm, and the thickness of the electron supply layer is 1 nm to 40 nm.
9. Item 9. The nitride semiconductor device according to any one of Items 1 to 8, wherein the ohmic electrode does not contain Au.
10. Further comprising a passivation film covering the surface of the electron supply layer,
A gate body portion disposed in an opening formed in the passivation film; and a predetermined field toward the drain electrode on the surface of the passivation film outside the opening and continuous with the gate body portion. A field plate portion extending over the plate length, wherein the field plate length is 1/6 or more and 1/2 or less of a distance between the gate main body portion and the drain electrode. 10. The nitride semiconductor device according to claim 9.
11. Forming an electron transit layer made of a nitride semiconductor;
A step of forming an AlN layer in contact with the electron transit layer and laminating an electron supply layer made of a nitride semiconductor containing Al and having an Al composition different from that of the electron transit layer on the electron transit layer;
Forming a laminated electrode film by sequentially laminating a Ti layer, a Si layer, an Al layer and a Mo layer on the electron supply layer;
Heat-treating the laminated electrode film to form ohmic electrodes as source and drain electrodes;
Forming a gate electrode facing the electron transit layer between the source electrode and the drain electrode;
A method for manufacturing a nitride semiconductor device, comprising:
12 In the formation of the laminated electrode film and the heat treatment, the peak density of Ti, Al, and Mo in the ohmic electrode is 10 ²⁰ cm ⁻³ or more, and the peak density of Si in the ohmic electrode is 10 ¹⁸ cm ⁻³ or more. Item 12. The method for manufacturing a nitride semiconductor device according to Item 11, wherein the method is performed so that
13. The step of forming the electron supply layer includes a step of forming a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, and the stacked electrode film is formed on the cap layer. 13. A method for manufacturing a nitride semiconductor device according to item 12.
14 Removing the electron supply layer directly under the gate electrode;
Forming a gate insulating film in contact with the electron transit layer in the region where the electron supply layer has been removed,
Item 14. The method for manufacturing a nitride semiconductor device according to any one of Items 11 to 13, wherein the gate electrode is formed so as to face the electron transit layer with the gate insulating film interposed therebetween.
15. Further comprising forming a passivation film covering the surface of the electron supply layer,
A gate body portion disposed in an opening formed in the passivation film; and a predetermined field toward the drain electrode on the surface of the passivation film outside the opening and continuous with the gate body portion. A field plate portion extending over the plate length, and the field plate length is formed to be 1/6 or more and 1/2 or less of the distance between the gate body portion and the drain electrode. Item 15. The method for manufacturing a nitride semiconductor device according to any one of Items 11 to 14.
16. An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, includes Al and is made of a nitride semiconductor having an Al composition different from that of the electron transit layer, and has an AlN layer in contact with the electron transit layer;
A source electrode and a drain electrode formed on the electron supply layer at intervals from each other;
A gate electrode disposed between the source electrode and the drain electrode and facing the electron transit layer;
The nitride semiconductor device, wherein the gate electrode is formed in a band-shaped pattern having a constant width separating the source electrode and the drain electrode.
17. Item 17. The nitride semiconductor device according to Item 16, wherein the gate electrode is formed in a zigzag shape so as to separate the source electrode and the drain electrode.
18. Item 18. The nitride semiconductor device according to Item 16 or 17, wherein the gate electrode is formed at a position closer to the source electrode than the drain electrode.
19. Item 19. The nitride semiconductor device according to any one of Items 16 to 18, wherein the source electrode and the drain electrode are respectively formed in a pair of rectangular regions whose longitudinal directions are parallel to each other.
In the above-described embodiment, the laminated electrode film for producing the ohmic electrode has the Ti layer 31, the first Si layer 32, the Al layer 33, the second Si layer 34, and the Mo layer 35 laminated in order from the electron supply layer 4 side. Although an example is shown, the second Si layer 34 may be omitted. In this case, no peak corresponding to the second Si layer 34 appears in the composition spectrum of the ohmic electrode after the sintering process.

1 Substrate 2 Buffer layer 3 Electron travel layer (GaN layer)
4 Electron supply layer (AlGaN layer)
41 First layer (AlN layer)
42 Second layer (AlGaN layer)
43 Third layer (GaN)
DESCRIPTION OF SYMBOLS 5 Passivation film | membrane 6 Source electrode 7 Drain electrode 8 Gate electrode 81 Gate main-body part 82 Field plate part 9 Recessed part 10 Gate insulating film 11 Oxide film 12 Insulating layer 15 Two-dimensional electron gas 16 Resist film 17 Electrode film 30 Stacked electrode film 31 Ti layer 32 1st Si layer 33 Al layer 34 2nd Si layer 35 Mo layer Lg gate length Lfp field plate length Lgd gate-drain distance Sa source junction area Da drain junction area Ga gate junction area

Claims (13)

An electron transit layer made of a nitride semiconductor;
An electron supply layer that is laminated on the electron transit layer, includes Al and is made of a nitride semiconductor having an Al composition different from that of the electron transit layer, and has an AlN layer in contact with the electron transit layer;
A source electrode and a drain electrode, which are formed on the electron supply layer at intervals from each other and are made of ohmic electrodes including Ti, Al, Mo and Si;
Wherein disposed between the source electrode and the drain electrode, seen including a gate electrode opposed to the electron transit layer,
In the ohmic electrode, in order from the electron supply layer side, a Ti composition peak, an Al composition peak, and a Mo composition peak appear, and the first Si composition is between the Ti composition peak and the Al composition peak. The nitride semiconductor device is configured such that a peak of the second Si composition appears between the peak of the Al composition and the peak of the Mo composition . Wherein is the Ti in the ohmic electrodes, each peak density of Al and Mo ¹⁰ 20 ^{cm -3} or more, the peak density of Si in the said ohmic electrode is ¹⁰ 18 ^{cm -3} or more, nitride according to claim 1 Semiconductor device. The electron supply layer, wherein the includes a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, the source electrode and the drain electrode made of the ohmic electrode on the cap layer is formed, according to claim 1 or 2. The nitride semiconductor device according to 2. The nitride semiconductor device according to claim 3 , wherein the cap layer has a thickness of 16 nm or less. The electron supply layer directly under the gate electrode is removed, and the gate electrode is opposed to the electron transit layer through a gate insulating film in contact with the electron transit layer in a region where the electron supply layer is removed. The nitride semiconductor device according to any one of claims 1 to 4 . The thickness of the AlN layer is 1 nm to 5 nm, wherein the thickness of the electron supply layer is 1 nm to 40 nm, a nitride semiconductor device according to any one of claims 1-5. The ohmic electrode is free of Au, the nitride semiconductor device according to any one of claims 1-6. Further comprising a passivation film covering the surface of the electron supply layer,
A gate body portion disposed in an opening formed in the passivation film; and a predetermined field toward the drain electrode on the surface of the passivation film outside the opening and continuous with the gate body portion. 2. A field plate portion extending over a plate length, wherein the field plate length is 1/6 or more and 1/2 or less of a distance between the gate body portion and the drain electrode. The nitride semiconductor device according to any one of to 7 . Forming an electron transit layer made of a nitride semiconductor;
A step of forming an AlN layer in contact with the electron transit layer and laminating an electron supply layer made of a nitride semiconductor containing Al and having an Al composition different from that of the electron transit layer on the electron transit layer;
Forming a laminated electrode film by sequentially laminating a Ti layer, a first Si layer, an Al layer , a second Si layer and a Mo layer on the electron supply layer;
Heat-treating the laminated electrode film to form ohmic electrodes as source and drain electrodes;
Forming a gate electrode facing the electron transit layer between the source electrode and the drain electrode. In the formation of the laminated electrode film and the heat treatment, the peak density of Ti, Al, and Mo in the ohmic electrode is 10 ²⁰ cm ⁻³ or more, and the peak density of Si in the ohmic electrode is 10 ¹⁸ cm ⁻³ or more. The method for manufacturing a nitride semiconductor device according to claim 9 , wherein the method is performed so that: Wherein the step of forming the electron supply layer includes a step of forming a cap layer made of a nitride semiconductor having the same composition as the electron transit layer, the laminated electrode layer is formed over the cap layer, according to claim 9 Or a method of manufacturing a nitride semiconductor device according to 10 ; Removing the electron supply layer directly under the gate electrode;
Forming a gate insulating film in contact with the electron transit layer in the region where the electron supply layer has been removed,
The gate electrode is formed so as to face the electron transit layer sandwiching the gate insulating film, method of manufacturing the nitride semiconductor device according to any one of claims 9-11. Further comprising forming a passivation film covering the surface of the electron supply layer,
A gate body portion disposed in an opening formed in the passivation film; and a predetermined field toward the drain electrode on the surface of the passivation film outside the opening and continuous with the gate body portion. A field plate portion extending over the plate length, and the field plate length is formed to be 1/6 or more and 1/2 or less of the distance between the gate body portion and the drain electrode. method of manufacturing a nitride semiconductor device according to any one of claims 9-12.

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