JP2013168433A - Nitride semiconductor device and method of manufacturing nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device that allows maintaining a surface of a nitride semiconductor layer in an excellent condition, has a gate insulating film with excellent insulation properties, and has low on-resistance.SOLUTION: A nitride semiconductor device includes a substrate (10), a nitride semiconductor layer (11) provided on the substrate, a gate insulating film (15) provided on the nitride semiconductor layer, and a gate electrode (19) provided on the gate insulating film. The gate insulating film is in contact with the nitride semiconductor layer and has a first insulating film (16) composed of a silicon oxide film having a film thickness of 3 nm or more to 10 nm or less. On the first insulating film, a second insulating film (17) composed of a material having a high dielectric constant than the first insulating film is stacked.

Description

  Embodiments described herein relate generally to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

  A semiconductor device using a compound semiconductor as a material is expected to realize an excellent characteristic not found in a semiconductor using Si (silicon) as a material. Among these, nitride semiconductors such as GaN (gallium nitride) are promising as materials for power devices that require high output and high voltage operation because they have a wide band gap and can achieve high breakdown field strength. .

  For example, HFET (Heterostructure Field Effect Transistor) using a heterostructure in which an AlGaN (aluminum gallium nitride) layer is stacked on a GaN layer generates a high-concentration two-dimensional electron gas at the interface between the GaN layer and the AlGaN layer. Therefore, the on-resistance is small and high output characteristics can be obtained.

  In general, AlGaN / GaN-HFETs are normally on, but for power applications, for example, normally off is desirable in terms of safety and power consumption. By using a gate recess structure in which the AlGaN layer directly under the gate is locally removed, a normally-off operation can be achieved.

  In order to extract the excellent characteristics of the GaN-based power device, an insulated gate structure advantageous for high voltage operation is desired. As a gate insulating film in a MIS (Metal Insulator Semiconductor) type HFET, for example, a silicon oxide film or a silicon nitride film is used.

  However, the conventional gate insulating film has some problems. For example, when a conventional gate insulating film is formed on a nitride semiconductor layer, the surface composition of the nitride semiconductor layer is greatly deviated from the stoichiometric composition and the surface state is impaired. Alternatively, it is difficult for the conventional gate insulating film to ensure sufficient insulation between the nitride semiconductor layer and the gate electrode. A gate insulating film that can be maintained in a good state without damaging the surface of the nitride semiconductor layer, has sufficient insulation, and is suitable for a power device using a GaN-based semiconductor has not yet been obtained. is there.

JP 2009-76673 A JP 2009-10107 A

IEICE Technical Report, ED2005-129, pp.51 (2005)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device that can maintain the surface of a nitride semiconductor layer in a good state and has a gate insulating film with excellent insulating properties and low on-resistance. .

  According to the embodiment, a nitride semiconductor device includes a substrate, a nitride semiconductor layer provided on the substrate, a gate insulating film provided on the nitride semiconductor layer, and the gate insulating film. And a gate electrode. The gate insulating film includes a first insulating film made of a silicon oxide film having a thickness of 3 nm to 10 nm in contact with the nitride semiconductor layer, and the first insulating film is formed on the first insulating film. A second insulating film made of a material having a dielectric constant higher than that of the film is stacked.

The schematic diagram which shows the cross-section of the nitride semiconductor device which concerns on one Embodiment. The figure explaining the dielectric constant and band gap energy of a GaN-type semiconductor and various insulating films. The figure explaining the heat processing temperature dependence of the V / III group element ratio in the surface of the GaN-type semiconductor substrate in which the silicon oxide film was deposited. The figure explaining the silicon oxide film thickness dependence of the V / III group element ratio in the surface of the GaN-type semiconductor substrate in which the silicon oxide film was deposited. 1 is a schematic cross-sectional view illustrating a manufacturing process of a nitride semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 5. FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 6. FIG. 8 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 7. FIG. 9 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 8. FIG. 10 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 9. FIG. 11 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 10. FIG. 12 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 11. FIG. 13 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 12. FIG. 14 is a schematic cross-sectional view illustrating a manufacturing process following FIG. 13. FIG. 6 is a schematic cross-sectional view showing a nitride semiconductor device according to another embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described as appropriate.

  FIG. 1 is a schematic diagram showing a cross-sectional structure of a nitride semiconductor device according to an embodiment. The illustrated nitride semiconductor device is a MIS type AlGaN / GaN-HFET 100 having a gate recess structure, and includes a substrate 10 and a nitride semiconductor layer 11 provided thereon. A gate electrode 19 is provided on the gate insulating film 15 in a predetermined region on the nitride semiconductor layer 11. A source electrode 18S and a drain electrode 18D are provided in contact with the surface of the nitride semiconductor layer 11 with the gate insulating film 15 interposed therebetween. As the substrate 10, for example, a semi-insulating silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, or a gallium nitride substrate can be used.

More specifically, the nitride semiconductor layer 11 has a laminated structure including a buffer layer 12, an electron transit layer 13, and an electron supply layer 14 that are sequentially epitaxially grown on the substrate 10. Nitride semiconductor herein may be represented by the general formula _{In x Al y Ga 1-xy} N (0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1). The nitride semiconductor may further include a group V element other than N (nitrogen), and may further include various dopants added to control the conductivity type.

  More specifically, for example, an aluminum nitride (AlN) layer can be used as the buffer layer 12, and the thickness is usually about 10 to 100 nm. Note that the buffer layer 12 is not necessarily required when the electron transit layer 13 can be directly epitaxially grown on the substrate 10.

The electron transit layer 13 can be formed with a thickness of about 2 to 3 μm using, for example, i-type GaN. Moreover, the electron supply layer 14 can be formed with a thickness of about 20 to 30 nm using, for example, i-type Al _0.25 Ga _0.75 N. Here, i-type means that impurities are not intentionally doped. In nitride semiconductors such as GaN used for the electron transit layer 13 and AlGaN used for the electron supply layer 14, the V group nitrogen (N) vacancies function as donors, and therefore are doped with n-type impurities. Even if not, the nitride semiconductor exhibits n-type conductivity.

  The nitride semiconductor layer 11 is configured by the arbitrary buffer layer 12, the electron transit layer 13, and the electron supply layer 14. A predetermined region of the electron supply layer 14 (region where the gate electrode is formed) is provided with a recess R that exposes a part of the surface of the electron transit layer 13, and the gate insulating film 15 is formed in the recess R. Are formed on the entire surface of the electron supply layer 14. Therefore, the gate insulating film 15 also has a recess corresponding to the recess R, and the gate electrode 19 is provided in the recess of the gate insulating film 15. The gate insulating film 15 is a stacked film of a first insulating film 16 and a second insulating film 17. The first insulating film is made of a silicon oxide film having a thickness of 3 nm to 10 nm, and the second insulating film 17 is made of a material having a dielectric constant higher than that of the silicon oxide film.

  The second insulating film 17 includes, for example, an aluminum oxide film, a hafnium oxide film, a tantalum oxide film, a zirconium oxide film, a titanium oxide film, a hafnium aluminum oxide film, a hafnium silicon oxide film, a hafnium oxynitride film, and an acid. It can be selected from the group consisting of silicon nitride films. The second insulating film 17 is not limited to a single layer film, and a plurality of these insulating films may be stacked.

  If the thickness of the gate insulating film 15 as a whole can be ensured, for example, about 20 nm, the thickness of the second insulating film 17 is preferably about 10 to 17 nm.

  The source electrode 18S and the drain electrode 18D are ohmic electrodes provided in contact with the electron supply layer 14, and can be formed by, for example, sequentially laminating titanium and aluminum. The gate electrode 19 formed in the recess of the gate insulating film 15 can be formed by sequentially laminating nickel and gold, for example. In the HFET 100 shown in FIG. 1, since all of the electron supply layer 14 is removed in the recess in which the gate electrode 19 is provided, a stable normally-off operation is possible with small threshold variation.

  Nitrogen, a group V element constituting a nitride semiconductor, has a higher vapor pressure than that of a group III element and is easily desorbed. For this reason, it is generally considered difficult to obtain a stoichiometric surface state when an insulating film is formed on a nitride semiconductor layer. For example, when a silicon oxide film is deposited on a nitride semiconductor layer by a plasma CVD (Chemical Vapor Deposition) method or the like to form a MIS type GaN-based HFET having a gate insulating film made of a silicon oxide film, When the silicon film is deposited, the nitride semiconductor layer is oxidized and nitrogen is released. As a result, a large number of interface states are generated at the interface between the nitride semiconductor layer and the gate insulating film.

  In the case of forming a MIS type GaN-based HFET having a gate insulating film made of a silicon nitride film by depositing a silicon nitride film on the nitride semiconductor layer, the nitride semiconductor layer is compared with the case of forming a silicon oxide film. The oxidation of is suppressed. However, it is difficult to obtain a silicon nitride film having a stoichiometric composition by a general plasma CVD method or sputtering method, and there are more defects in the film than a silicon oxide film whose composition control is easy.

  Further, when manufacturing an HFET having a gate recess structure, a recess is formed in the nitride semiconductor layer by a dry etching method such as RIE (Reactive Ion Etching). The dry etching may cause defects mainly due to nitrogen vacancies on the surface of the nitride semiconductor layer, resulting in an increase in interface state density.

  Such interface states, defects in the film, and the like cause factors such as fluctuations in threshold voltage, a decrease in carrier mobility, an increase in gate leakage current, and the like, which greatly deteriorates the electrical characteristics of the FET. In order to extract the excellent characteristics of the MIS type nitride semiconductor device, it is required to form a good interface between the nitride semiconductor layer and the gate insulating film, and the gate insulating film has defects in the film. Less is also required.

Here, FIG. 2 shows the band gap energy and relative dielectric constant of the GaN-based semiconductor and various insulating materials. Silicon oxide has a band gap energy of about 9 eV, which is the largest among the insulating materials shown in FIG. For example, it is about 5 eV for silicon nitride and only 5.6 eV for hafnium oxide. The band gap energy of GaN is about 3.4 eV, and the band gap energy of Al _0.25 Ga _0.75 N is about 4.1 eV. Therefore, the silicon oxide film provided on the GaN-based semiconductor layer can form a sufficiently high energy barrier with the GaN-based semiconductor layer, and has an effect of improving insulation.

  In order to obtain an MIS type nitride semiconductor device having a low on-resistance, it is desirable to use a material having a high dielectric constant as a gate insulating film in addition to a large band gap energy. This is because the insulation between the nitride semiconductor layer and the gate electrode can be improved and the mutual conductance can be increased.

  Although silicon oxide has a large band gap energy, its relative dielectric constant is as low as about 3.9. When such a silicon oxide film is used as the gate insulating film of the MIS type nitride semiconductor device, the on-resistance is not sufficiently reduced. The inventors have made it possible to increase the dielectric constant of the entire gate insulating film by stacking a film having a higher dielectric constant than that of the silicon oxide film on the silicon oxide film and using it as the gate insulating film. For example, aluminum oxide has a relative dielectric constant of about 10 which is larger than that of silicon oxide and a band gap energy of about 7.3 eV, which is a relatively large value among general high dielectric constant materials.

  In the gate insulating film in which such a high dielectric constant film is laminated on the silicon oxide film, the equivalent oxide film thickness of the gate insulating film can be reduced compared to the case where the silicon oxide film is formed as a single layer. it can. Thereby, it is possible to increase the mutual conductance as compared with the case where the gate insulating film is formed of a single silicon oxide film. Further, by increasing the physical film thickness of the insulating film in accordance with the dielectric constant, the insulating property of the gate insulating film can be improved. When a material having a dielectric constant higher than that of aluminum oxide, for example, hafnium oxide (relative dielectric constant: about 20) is used, the effect due to the second insulating film is further enhanced.

  As described above, in order to obtain a MIS type nitride semiconductor device having a low on-resistance, the gate insulating film is required to have a large band gap energy and a high dielectric constant. A first insulating film made of a silicon oxide film is formed on the nitride semiconductor layer, and a second insulating film having a higher dielectric constant than that of the silicon oxide film is formed on the first insulating film to form a laminated structure. By using a gate insulating film, the conditions of band gap energy and dielectric constant are satisfied.

  Note that since the second insulating film is provided to ensure a high dielectric constant, it is desirable that the thickness of the first insulating film is not too large. For example, when the total thickness of the gate insulating film is about 20 nm, the thickness of the first insulating film is 10 nm or less.

  As described above, the silicon oxide film can be easily controlled in composition and can reduce defects in the film. However, when formed on the nitride semiconductor layer, the nitride is caused by nitrogen desorption. Many interface states are generated at the interface between the semiconductor layer and the silicon oxide film. Such an interface state can be reduced by heat-treating the nitride semiconductor layer and the first insulating film in a nitrogen atmosphere before forming the second insulating film. In order to obtain a sufficient heat treatment effect, it is desirable that the thickness of the first insulating film be small.

  The present inventor has further intensively studied the chemical composition at the interface between the nitride semiconductor layer and the silicon oxide film as the first insulating film.

  A silicon oxide film was deposited on the GaN-based semiconductor substrate and heat-treated, and the V / III group element ratio on the surface of the GaN-based semiconductor substrate after the heat treatment was examined. Specifically, a GaN substrate or an AlGaN substrate is prepared as a GaN-based semiconductor substrate, a dry etching process using a chlorine-based gas is performed on the surface, and then a silicon oxide film having a predetermined thickness is deposited by a plasma CVD method. A sample was obtained. The sample was placed in an electric furnace and heat-treated in a nitrogen atmosphere at a predetermined temperature and for a predetermined time, and the chemical composition at the interface between the GaN-based semiconductor substrate and the silicon oxide film was examined by X-ray photoelectron spectroscopy.

  FIG. 3 shows the relationship between the heat treatment temperature and the V / III group element ratio on the surface of the GaN-based semiconductor (GaN) substrate. Here, the thickness of the silicon oxide film formed on the GaN substrate was 5 nm, and the heat treatment time was 10 minutes. As shown in the graph of FIG. 3, when the heat treatment in a nitrogen atmosphere is performed in a temperature range of 380 to 450 ° C., a V / III element ratio of 0.84 or more is obtained. When the heat treatment is performed in a temperature range of 395 to 415 ° C., a higher V / III group element ratio is obtained, and the value is 0.92 or more. The V / III element ratio in the stoichiometric composition is 1, but it is acceptable if it is 0.84 or more.

  FIG. 4 shows the relationship between the thickness of the silicon oxide film and the V / III group element ratio on the surface of the GaN-based semiconductor (GaN) substrate. Here, the heat treatment temperature in a nitrogen atmosphere was 400 ° C., and the heat treatment time was 10 minutes. FIG. 4 shows that when the thickness of the silicon oxide film exceeds a certain value, the V / III element ratio rapidly decreases. When the thickness of the silicon oxide film is 10 nm or less, the V / III group element ratio is 0.88 or more. However, when the thickness of the silicon oxide film is about 13 nm, the V / III group element ratio is about 0.5. To drop. It can be seen that the thickness of the silicon oxide film with which the allowable V / III group element ratio can be reliably obtained is 10 nm or less.

  If the thickness of the silicon oxide film is less than 3 nm, sufficient insulation cannot be obtained. When the second insulating film is deposited on such a silicon oxide film, the nitride semiconductor layer may be damaged. Considering this, it is desirable that the thickness of the silicon oxide film be 3 nm or more.

  From the above results, when the thickness of the silicon oxide film is 3 nm to 10 nm and the heat treatment temperature in the nitrogen atmosphere is 380 ° C. to 450 ° C., the improvement rate of the V / III group element ratio on the GaN substrate surface It can be seen that a good chemical bonding state close to the stoichiometric composition is obtained. For example, by covering the surface of a GaN-based semiconductor layer with a very thin silicon oxide film of about 5 nm and heat-treating at about 400 ° C. in a nitrogen atmosphere, the interface state caused by nitrogen vacancy defects that cause electrical property deterioration Is greatly reduced.

  In addition, since the heat treatment at a low temperature of about 400 ° C. can be performed between the formation of the first insulating film and the second insulating film, the stacked gate insulating film is not exposed to the outside air. It becomes possible to form. Accordingly, a highly reliable gate insulating film can be manufactured by a low cost and simple method.

  In the nitride semiconductor device of this embodiment, a good interface can be obtained between the nitride semiconductor layer and the gate insulating film. The insulation between the nitride semiconductor layer and the gate electrode is enhanced, and the mutual conductance can be increased. As a result, it is possible to realize a nitride semiconductor device having a low on-resistance, which can maintain the surface of the nitride semiconductor layer in a good state and has a gate insulating film excellent in insulation.

  A manufacturing process of a nitride semiconductor device according to an embodiment will be described with reference to FIGS.

First, as shown in FIG. 5, an AlN layer (thickness 10 nm) as a buffer layer 12, an i-type GaN layer (thickness 2 μm) as an electron transit layer 13, and an electron supply layer 14 on a SiC substrate 10. I-type Al _0.25 Ga _0.75 N layers (thickness 25 nm) are sequentially deposited to obtain the nitride semiconductor layer 11. The buffer layer 12, the electron transit layer 13, and the electron supply layer 14 can be formed using, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method.

  After an element isolation structure (not shown) is formed in the nitride semiconductor layer 11, a recess R is formed in a predetermined region of the electron supply layer 14 as shown in FIG. In forming the element isolation structure, for example, a resist mask is formed on the surface of the electron supply layer 14, and an element isolation groove is formed in a predetermined region by a dry etching method using a chlorine-based gas as an etching gas. Alternatively, an insulating element isolation region may be formed by ion implantation.

  The recess R in the electron supply layer 14 can be formed by a dry etching method using a chlorine gas by providing a resist mask in a predetermined region. In the recess R shown in FIG. 6, the electron supply layer 14 is completely removed, and the electron transit layer 13 is exposed on the bottom surface of the recess.

  Next, as shown in FIG. 7, a silicon oxide film is formed on the entire surface as the first insulating film 16. The silicon oxide film preferably has a thickness of 3 nm to 10 nm, and can be deposited by using, for example, an ALD (Atomic Layer Deposition) method. By using the ALD method, the film thickness and film quality of the silicon oxide film can be controlled with high accuracy.

  The substrate 10 on which the first insulating film 16 is formed on the nitride semiconductor layer 11 is subjected to heat treatment in a temperature range of 380 ° C. to 450 ° C. in a nitrogen gas atmosphere. The heat treatment time can be appropriately selected according to the thickness of the first insulating film 16 and can be, for example, about 10 to 15 minutes.

  On the first insulating film 16 after the heat treatment, a second insulating film 17 is formed as shown in FIG. For example, the second insulating film 17 having a thickness of about 10 to 15 nm can be obtained by depositing an aluminum oxide film using the ALD method. As described above, the ALD method is advantageous in that the film thickness and film quality of the obtained film can be controlled with high accuracy. The gate insulating film 15 is configured by a laminated film in which the second insulating film 17 is provided on the first insulating film 16.

  On the gate insulating film 15, a lower resist mask 20a and an upper resist mask 20b having openings 21 at predetermined positions are sequentially formed as shown in FIG. As shown in the figure, in the opening 21, the end portion of the upper resist mask 20b has an overhang shape that protrudes above the lower resist mask 20a. A predetermined region of the gate insulating film 15 is removed by, for example, a dry etching method using the laminated resist mask 20 including the lower layer resist mask 20a and the upper layer resist mask 20b as an etching mask. After the dry etching, as shown in FIG. 9, the gate insulating film 15 in the region where the source electrode 18S and the drain electrode 18D are formed is removed, and the electron transit layer 14 is exposed.

  On the electron transit layer 14 exposed by removing the gate insulating film 15, a metal layer 23 is formed as shown in FIG. The metal layer 23 can be formed, for example, by sequentially depositing a Ti (titanium) film and an Al (aluminum) film. As illustrated, the metal layer 23 is separated into a portion deposited on the bottom of the opening 21 and a portion deposited on the upper resist mask 20b by the laminated resist mask 20 formed in an overhang shape. It is formed.

  The laminated resist mask 20 including the lower resist mask 20a and the upper resist mask 20b is removed by wet treatment. As a result, as shown in FIG. 11, only the portion of the metal layer 23 deposited on the bottom of the opening 21 is left. The remaining metal layer 23 forms a source electrode 18S and a drain electrode 18D.

  Next, in order to obtain ohmic characteristics, for example, rapid thermal annealing (RTA) is performed in a temperature range of 500 ° C. to 600 ° C., and the electron supply layer 14, the source electrode 18S, and the drain electrode An ohmic contact is formed with 18D.

  Thereafter, as shown in FIG. 12, a lower resist mask 20c and an upper resist mask 20d having an opening 22 between the source electrode 18S and the drain electrode 18D are formed. In the opening 22, the end portion of the upper resist mask 20d has an overhang shape protruding above the lower resist mask 20c. By using such a laminated resist mask 20, a gate electrode is formed by a lift-off method.

  Subsequently, as shown in FIG. 13, a metal layer 24 to be the gate electrode 19 in which Ni (nickel) and Au (gold) are sequentially laminated is formed by using, for example, a vapor deposition method. Although not shown in the drawing, the metal layer 24 has a laminated structure including a Ni layer and an Au layer. A wet peeling process is performed to remove the metal layer 24 deposited on the upper resist mask 20d together with the laminated resist mask 20 including the lower resist mask 20c and the upper resist mask 20d. As shown in FIG. 14, the remaining metal layer 24 constitutes the gate electrode 19. Through the above steps, the HFET 100 according to the present embodiment is obtained.

  In the HFET 100 shown in FIG. 14, the first insulating film 16 is provided in contact with the electron transit layer 13 at the bottom surface of the recess, but is not limited thereto. For example, as shown in FIG. 15, the first insulating film 16 can be provided so as to contact only the electron supply layer 14. Such a structure is obtained by controlling the formation of the recess. That is, for example, when a recess is formed in a predetermined region by a dry etching method using a chlorine-based gas, the etching amount is controlled so that the electron supply layer 14 having a predetermined thickness (for example, 5 nm) is left at the bottom. To do. A first insulating film 16 is formed on the recessed electron supply layer 14 by the same method as described above, and the nitride semiconductor layer 11 and the first insulating film 16 are heat-treated under predetermined conditions. Then, the second insulating film 17 is formed to obtain the gate insulating film 15. Further, the source electrode 18S, the drain electrode 18D, and the gate electrode 19 are formed by the same method as described above, and the HFET 110 illustrated is obtained.

  Note that the nitride semiconductor device of the present embodiment is not limited to the HFET, and is widely applied to any nitride semiconductor device in which a gate insulating film is formed on a semiconductor layer of a MISFET, MOSFET, semiconductor laser, or other nitride semiconductor. can do.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... Substrate; 11 ... Nitride semiconductor layer; 12 ... Buffer layer; 13 ... Electron transit layer 14 ... Electron supply layer; 15 ... Gate insulating film; 16 ... First insulating film 17 ... Second insulating film; 18D ... Drain electrode 19 ... Gate electrode; 20 ... Multilayer resist mask; 20a ... Lower resist mask 20b ... Upper resist mask; 20c ... Lower resist mask 20d ... Upper resist mask; 21 ... Opening; Metal layer 24 ... Metal layer; 100 ... HFET; 110 ... HFET.

Claims (4)

A substrate,
A nitride semiconductor layer provided on the substrate;
A gate insulating film provided on the nitride semiconductor layer;
A gate electrode provided on the gate insulating film,
The gate insulating film is in contact with the nitride semiconductor layer and is stacked on the first insulating film and a first insulating film made of a silicon oxide film having a thickness of 3 nm to 10 nm. And a second insulating film made of a material having a high dielectric constant. Forming a nitride semiconductor layer on the substrate;
Forming a first insulating film made of a silicon oxide film in contact with the nitride semiconductor layer;
Heat treating the nitride semiconductor layer and the first insulating film;
A second insulating film made of a material having a higher dielectric constant than that of the first insulating film is formed on the first insulating film after the heat treatment, and the first insulating film and the second insulating film are formed. Obtaining a gate insulating film having a laminated structure with
And a step of forming a gate electrode on the gate insulating film.   The method for manufacturing a nitride semiconductor device according to claim 2, wherein the first insulating film is formed with a thickness of 3 nm to 10 nm.   4. The nitride semiconductor device according to claim 2, wherein the heat treatment of the nitride semiconductor layer and the first insulating film is performed at a temperature of 380 ° C. to 450 ° C. in a nitrogen gas atmosphere. 5. Production method.

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