JP5487550B2 - Field effect semiconductor device and manufacturing method thereof - Google Patents

Field effect semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5487550B2
JP5487550B2 JP2008073603A JP2008073603A JP5487550B2 JP 5487550 B2 JP5487550 B2 JP 5487550B2 JP 2008073603 A JP2008073603 A JP 2008073603A JP 2008073603 A JP2008073603 A JP 2008073603A JP 5487550 B2 JP5487550 B2 JP 5487550B2
Authority
JP
Japan
Prior art keywords
semiconductor
main
layer
electrode
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008073603A
Other languages
Japanese (ja)
Other versions
JP2009076845A5 (en
JP2009076845A (en
Inventor
信男 金子
Original Assignee
サンケン電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2007222273 priority Critical
Priority to JP2007222273 priority
Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to JP2008073603A priority patent/JP5487550B2/en
Priority claimed from US12/199,323 external-priority patent/US7859021B2/en
Publication of JP2009076845A publication Critical patent/JP2009076845A/en
Publication of JP2009076845A5 publication Critical patent/JP2009076845A5/ja
Application granted granted Critical
Publication of JP5487550B2 publication Critical patent/JP5487550B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a field effect such as a high electron mobility transistor (HEMT), a diode having a two-dimensional electron carrier gas layer as a current path, a metal semiconductor field effect transistor (MESFET), or the like. The present invention relates to a semiconductor device and a manufacturing method thereof.

  A conventional HEMT, which is a kind of field effect transistor, has an electron transit layer made of a nitride semiconductor such as undoped GaN formed on a substrate such as silicon or sapphire via a buffer layer, and is doped with an n-type impurity. Or it has the electron supply layer or barrier layer which consists of nitride semiconductors, such as undoped AlGaN, and the source electrode, drain electrode, and gate electrode (Schottky electrode) which were formed on the electron supply layer. The band gap of the electron supply layer made of AlGaN or the like is larger than the band gap of the electron transit layer made of GaN or the like, and the lattice constant of the electron supply layer made of AlGaN or the like is smaller than the lattice constant of the electron transit layer made of GaN or the like. . When an electron supply layer having a smaller lattice constant than this is disposed on the electron transit layer, an extensible strain, that is, a tensile stress, is generated in the electron supply layer, resulting in piezoelectric polarization. Since the electron supply layer also spontaneously polarizes, a well-known two-dimensional electron gas layer, that is, a 2DEG layer is formed in the vicinity of the heterojunction surface between the electron transit layer and the electron supply layer by the action of an electric field based on piezo polarization and spontaneous polarization. As is well known, the 2DEG layer functions as a current path (channel) between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

By the way, a HEMT having a general configuration has a characteristic that a current flows between a source electrode and a drain electrode in a state where a gate control voltage is not applied to the gate electrode (normally state), that is, a normally-on characteristic. In order to keep the normally-on HEMT in an off state, a negative power source for setting the gate electrode to a negative potential is required, and the electric circuit is necessarily expensive. Therefore, the ease of use of a conventional normally-on HEMT is not good.

Therefore, development of a heterojunction field effect semiconductor device having normally-off characteristics is underway. As a typical method for obtaining normally-off characteristics,
(1) A method of forming a recess (concave portion) in the electron supply layer and forming a gate electrode on the electron supply layer thinned by the recess,
(2) A method of disposing a p-type semiconductor layer made of a p-type nitride semiconductor between a gate electrode and an electron supply layer as disclosed in Japanese Patent Application Laid-Open No. 2004-273486 (Patent Document 1),
(3) As disclosed in JP 2006-222414 A (Patent Document 2), a recess is formed in the electron supply layer (barrier layer), and an insulating film such as strontium titanate is formed on the recess. A method of providing a gate electrode;
(4) As disclosed in WO2003 / 071607 (Patent Document 3), a part of the electron supply layer is removed to expose a part of the electron transit layer, and an insulating film is formed on the electron transit layer. Providing a gate electrode via,
It has been known.

When the electron supply layer is partially thinned by the recess according to the method of (1) above, the electric field based on piezoelectric polarization and spontaneous polarization in the thinned portion of the electron supply layer is weakened. Therefore, the electric field based on the piezo polarization and spontaneous polarization of the electron supply layer weakened due to the recess is a built-in potential between the gate electrode and the electron supply layer, that is, the bias voltage of the gate electrode. Is canceled by the potential difference between the gate electrode and the electron supply layer in a state where the zero is zero, and the 2DEG layer disappears from the portion of the electron transit layer facing the gate electrode. As a result, the drain-source is turned off in a state where no gate control voltage is applied to the gate electrode, and a normally-off characteristic is obtained. However, the HEMT threshold value according to the above method (1) is relatively small, for example, +1 V or less, and it is easy to malfunction due to noise, and a positive gate control voltage is applied to the gate electrode composed of a Schottky electrode. The problem that a relatively large leakage current flows, the problem that the threshold voltage changes greatly due to variations in the depth of the recess, and the thin part of the electron supply layer (barrier layer) under the gate electrode Even when a control voltage for turning on (conducting) is applied to the gate electrode, the electron concentration in the electron transit layer facing the gate electrode is sufficient because the ability to supply electrons to the electron transit layer is low. In other words, it is difficult to form a high 2DEG layer, and the on-resistance between the drain electrode and the source electrode becomes relatively high.

When the p-type semiconductor layer is disposed under the gate electrode according to the method of (2) above, the p-type semiconductor layer raises the potential of the electron transit layer immediately below the gate electrode to deplete the electrons in the 2DEG layer, The 2DEG layer disappears and normally-off characteristics are obtained. However, the method (2) has a problem that it is difficult to easily obtain a p-type semiconductor layer made of a p-type nitride semiconductor having a high hole concentration, and a p-type semiconductor layer having a high hole concentration is obtained. When this is not possible, it is required to make the electron supply layer thin or to reduce the Al ratio of the electron supply layer made of AlGaN or AlInGaN. As a result, the electron concentration of the 2DEG layer decreases, and the source electrode There is a problem that the on-resistance between the drain electrode and the drain electrode is increased.

When a recess is formed under the gate electrode in accordance with the method (3) and an insulating film is disposed here, a normally-off characteristic is obtained because the portion of the electron supply layer (barrier layer) under the gate electrode is thin. In addition, since an insulating film is provided, an increase in leakage current is suppressed even though the portion under the gate electrode of the electron supply layer (barrier layer) is thin, and the transconductance g m of the HEMT is reduced. Can be high. However, the method (3) also has the same problem as the method (1) because the recess is formed in the same manner as the method (1). Further, in the method (3), in order to increase the transconductance g m of the HEMT, when a relatively thin insulating film, defects are likely to occur in the insulating film. If there is a defect in the insulating film, an increase in leakage current, a decrease in breakdown voltage, element breakdown, and an increase in current collapse are likely to occur. Of course, these problems can be solved by forming a thick insulating film. However, when the insulating film is formed thick, the transconductance g m is lowered.

In accordance with the method (4) above, when an insulating film is arranged directly on the electron transit layer and a gate electrode is provided on this insulating film, a 2DGE layer is formed in a normally state directly under the gate electrode of the electron transit layer. As a result, normally-off characteristics are obtained. However, since a 2DGE layer based on a heterojunction is not formed immediately below the gate electrode of the electron transit layer when a voltage for turning on the gate electrode is applied, it is turned on compared to a conventional HEMT having normally-on characteristics. There is a problem that the resistance is high.

The same problem as the above-described HEMT also exists in a diode using a 2DEG layer, a field effect semiconductor device (for example, MESFET) other than the HEMT, and the like.
JP 2004-273486 A JP 2006-222414 A WO2003 / 071607 Publication

  Therefore, the problem to be solved by the present invention is that a normally-off type field effect semiconductor device with small on-resistance and gate leakage current is required, and the object of the present invention is a field effect capable of meeting the above requirements. A semiconductor device and a manufacturing method thereof are provided.

The present invention for solving the above problems is as follows.
One and the other main surfaces opposed to each other, a first semiconductor layer disposed between the one and the other main surfaces, and disposed between the first semiconductor layer and the one main surface; and A second semiconductor layer formed of a material heterojunctioned to the first semiconductor layer and capable of generating a two-dimensional carrier gas layer functioning as a current path in the first semiconductor layer based on the heterojunction; A main semiconductor region comprising:
A first main electrode disposed on the one main surface of the main semiconductor region and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer;
A second main electrode disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer When,
The first main electrode and the second main electrode on the one main surface of the main semiconductor region to control a current path between the first main electrode and the second main electrode; A gate electrode disposed between,
The first main electrode formed between the main semiconductor region and the gate electrode by sputtering in an atmosphere containing oxygen and having a conductivity type for reducing carriers in the two-dimensional carrier gas layer; And a metal oxide semiconductor film disposed apart from the second main electrode. The present invention relates to a field effect semiconductor device.

According to another aspect of the present invention, the main semiconductor region has a recess having a depth that does not reach the first semiconductor layer from the one main surface, and the gate electrode is formed on the metal on the recess. It is desirable that the oxide semiconductor film be disposed through the oxide semiconductor film.
In addition, as shown in claim 3, the thickness of the remaining portion of the second semiconductor layer disposed between the concave portion and the first semiconductor layer is set before the metal oxide semiconductor film is provided. The two-dimensional carrier gas layer can be formed in a portion of the first semiconductor layer facing the recess, and after the metal oxide semiconductor film is provided, the recess in the first semiconductor layer is formed in the recess. It is desirable that the two-dimensional carrier gas layer be set so that the two-dimensional carrier gas layer cannot be formed in the facing portion.
According to a fourth aspect of the present invention, the two-dimensional carrier gas layer is preferably a two-dimensional electron gas layer, and the metal oxide semiconductor film is preferably a p-type metal oxide semiconductor film.
The p-type metal oxide semiconductor film is preferably made of at least one selected from nickel oxide, iron oxide, cobalt oxide, manganese oxide, and copper oxide.
According to a sixth aspect of the present invention, the p-type metal oxide semiconductor film is made of nickel oxide, and the gate electrode is formed on the nickel layer formed on the p-type metal oxide semiconductor film and on the nickel layer. And a gold layer formed on the substrate.
According to a seventh aspect of the present invention, the p-type metal oxide semiconductor film can be a stacked body of a plurality of p-type metal oxide semiconductor films made of different materials.
Moreover, as shown in claim 8, the p-type metal oxide semiconductor film can be formed so as to have different hole concentrations gradually or stepwise in the thickness direction.
In addition, according to a ninth aspect of the present invention, the main semiconductor region is further disposed on the second semiconductor layer and has a higher carrier concentration than the second semiconductor layer. It is preferable that the concave portion is formed so as to delete at least a part of the third semiconductor layer.
The first semiconductor layer is made of a nitride semiconductor, the second semiconductor layer is made of a nitride semiconductor containing Al, and the third semiconductor layer is made of the second semiconductor layer. It is desirable to be made of a nitride semiconductor containing Al at a larger ratio than the semiconductor layer.
The main semiconductor region may be further arranged on the third semiconductor layer and nitrided containing Al at a lower rate (including zero) than the third semiconductor layer. Preferably, the semiconductor device has a fourth semiconductor layer formed of a physical semiconductor, and the recess is formed so as to remove at least a part of the fourth semiconductor layer and the third semiconductor layer.
In addition, according to a twelfth aspect of the present invention, the main semiconductor region is further formed of a nitride semiconductor that is disposed on the third semiconductor layer and contains Al at a lower rate than the third semiconductor layer. A fourth semiconductor layer formed on the fourth semiconductor layer and a nitride semiconductor containing Al at a lower rate (including zero) than the fourth semiconductor layer and the metal oxide layer. A fifth semiconductor layer containing an impurity that determines a conductivity type opposite to the physical semiconductor film, and the recess includes at least the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor. It is desirable to be formed so as to remove a part of the layer.
The main semiconductor region may be further disposed between the first semiconductor layer and the second semiconductor layer and formed thinner than the second semiconductor layer. It is desirable to have a spacer layer made of a nitride semiconductor containing Al at a higher rate than the second semiconductor layer.
Moreover, as shown in claim 14, at least a part between the gate electrode and the first main electrode on one main surface of the main semiconductor region, and the gate electrode and the second main electrode It is desirable to have an insulating film disposed on at least a part between the two.
Moreover, as shown in claim 15, at least a part between the gate electrode and the first main electrode on one main surface of the main semiconductor region, and the gate electrode and the second main electrode And a gate field plate disposed on the insulating film, and the gate field plate has at least one of the main semiconductor regions through the insulating film. It is desirable to be opposed to the main surface and connected to the gate electrode.
According to a sixteenth aspect of the present invention, it is preferable that an end of the insulating film on the gate electrode side is an inclined side surface, and the gate field plate covers at least the inclined side surface of the insulating film.
According to a seventeenth aspect of the present invention, a conductor that electrically connects the gate electrode to the first main electrode can be provided for diode operation.
According to another aspect of the present invention, the first and second main surfaces facing each other, the first semiconductor layer disposed between the one and the other main surfaces, and the first semiconductor layer to form a current path. A main semiconductor region comprising a second semiconductor layer disposed between the semiconductor layer and the one main surface and having the first conductivity type, and the one main surface of the main semiconductor region A first main electrode disposed on and electrically coupled to the second semiconductor layer, disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode; A second main electrode electrically coupled to the second semiconductor layer; and the first main surface on the one main surface of the main semiconductor region to control a current path of the second semiconductor layer. A gate electrode disposed between the main electrode and the second main electrode; the gate electrode; It is disposed between the semiconductor region and the first conductivity type and having a second conductivity type opposite formed by sputtering in an atmosphere containing oxygen and the first main electrode and the second main A field effect semiconductor device including a metal oxide semiconductor film disposed away from an electrode can also be configured.
Moreover, as shown in claim 19, in the field effect semiconductor device according to claim 18, further, a recess is provided in the second semiconductor layer, and the metal oxide semiconductor film is provided on the recess. It is desirable to arrange via.
According to a twentieth aspect, in the field effect semiconductor device according to the seventeenth aspect, a conductor that electrically connects the gate electrode to the first main electrode can be further provided.
A main semiconductor region having at least one semiconductor layer for forming a current path and a current path disposed on one main surface of the main semiconductor region as defined in claim 21 A first main electrode electrically coupled to the semiconductor layer for forming the semiconductor layer, a first main electrode on one main surface of the main semiconductor region, the first main electrode being spaced apart from the first main electrode, and the current path A second main electrode electrically coupled to the semiconductor layer for forming, and the first main electrode on one main surface of the main semiconductor region to control the current path of the semiconductor layer And a gate electrode disposed between the second main electrode and a function of reducing carriers in the semiconductor layer disposed between the main semiconductor region and the gate electrode and forming the current path And the shape of the gate electrode When manufacturing a field effect semiconductor device comprising a metal oxide semiconductor film formed prior to a process and disposed away from the first main electrode and the second main electrode, the metal oxide The physical semiconductor film is preferably formed by sputtering in an atmosphere containing oxygen.

The invention of each claim of the present application has the following effects.
(1) The metal oxide semiconductor film can be formed relatively easily and is chemically stable. Therefore, the metal oxide semiconductor film of a predetermined conductivity type (for example, p-type) stably reduces the carriers in the current path of the main semiconductor region when the field effect semiconductor device is normal.
(2) The carrier (for example, hole) concentration of the metal oxide semiconductor film can be increased relatively easily. When the carrier (for example, hole) concentration of the metal oxide semiconductor film is high, the effect of reducing the carriers in the current path of the main semiconductor region (the function of forming a depletion layer) becomes large when the field effect semiconductor device is normal. In addition, since the metal oxide semiconductor film is formed by sputtering in an atmosphere containing oxygen, the carrier concentration (density) of the metal oxide semiconductor film is high .
The inventions of claims 2 and 19 have the following effects in addition to the effects (1) and (2).
(3) When the field effect semiconductor device is normal, the formation of a two-dimensional carrier gas layer (for example, a 2DEG layer) on the portion of the first semiconductor layer facing the gate electrode is well suppressed by the metal oxide semiconductor film. And good normally-off characteristics can be obtained.
According to the sixth aspect of the present invention, the gate leakage current can be greatly reduced by the combination of the nickel oxide to the p-type metal oxide semiconductor film and the gate electrode made of the nickel layer and the gold layer.
The invention of claim 9 has the following effects in addition to the effects of (1), (2) and (3) above. (4) The first semiconductor layer on which the two-dimensional electron gas layer (for example, 2DEG layer) is formed. A third semiconductor layer (for example, the second semiconductor layer) having a higher carrier concentration (for example, electron concentration) than the second semiconductor layer through the second semiconductor layer (for example, the first electron supply layer). Since the electron supply layer is provided, a second semiconductor layer (for example, the first electron supply layer) having a relatively low electron concentration is interposed between the recess and the first semiconductor layer (for example, the electron transit layer). . Therefore, the variation in threshold voltage due to the variation in the depth of the recess is reduced. If a semiconductor layer (for example, an electron supply layer) having a relatively high electron concentration is interposed between the recess and the first semiconductor layer (for example, an electron transit layer), the depth of the recess may vary. The variation in threshold voltage increases.
(5) Since the third semiconductor layer (for example, the second electron supply layer) having a relatively high electron concentration is provided, the second semiconductor layer (for example, the first electron supply) having a relatively low electron concentration is provided. Although the layer) is provided, the carrier concentration (for example, electron concentration) of the two-dimensional carrier gas layer (for example, 2DEG layer) in the portion other than the concave portion of the main semiconductor region can be increased, and the heterojunction field effect The on-resistance of the semiconductor device can be reduced.
The invention of claim 10 has the following effects in addition to the effects (1) to (5).
(6) The second semiconductor layer (for example, the first electron supply layer) adjacent to the first semiconductor layer (for example, the electron transit layer) has a low Al ratio, so that a positive threshold voltage can be reliably obtained. Can do.
(7) Since the second semiconductor layer (for example, the first electron supply layer) adjacent to the first semiconductor layer (for example, the electron transit layer) has a low Al ratio, the threshold voltage due to the variation in the depth of the recesses The variation of the is reduced. If a semiconductor layer (for example, an electron supply layer) having a relatively high proportion of Al is interposed between the recess and the first semiconductor layer (for example, an electron transit layer), the depth of the recess varies. The variation in threshold voltage due to increases.
The invention of claim 11 has the following effects in addition to the effects (1) to (7).
(8) The fourth semiconductor layer (for example, the third electron supply layer) adjacent to the third semiconductor layer (for example, the second electron supply layer) is the third semiconductor layer (for example, the second electron supply layer). Since the ratio of Al is lower than that, one main surface of the main semiconductor region can be stabilized, and a leakage current can be reduced and current collapse can be suppressed.
The invention of claim 12 has the following effects in addition to the effects (1) to (8).
(9) Since the fifth semiconductor layer containing an impurity that determines the conductivity type (for example, n-type) opposite to the metal oxide semiconductor film is provided, the ohmic contact property of the first and second main electrodes Can be improved.
The invention of claim 13 has the following effects in addition to the effects (1) to (3).
(10) The spacer layer suppresses diffusion of impurities or elements from the second semiconductor layer side to the first semiconductor layer side. This suppresses a decrease in carrier mobility in the two-dimensional carrier gas layer in the first semiconductor layer.
The invention of claim 14 has the following effects in addition to the effects (1) to (3).
(11) Since the field effect semiconductor device has an insulating film on one main surface of the main semiconductor region, surface stabilization of the main semiconductor region is achieved. Note that the insulating film is preferably formed using silicon oxide. The insulating film made of silicon oxide generates compressive stress (for example, 4.00 × 10 9 dyn / cm 2 ). When the compressive stress of the insulating film made of silicon oxide acts on one main surface of the main semiconductor region, that is, the main surface of the second semiconductor layer, a two-dimensional carrier gas layer (for example, 2DEG based on the piezoelectric polarization of the second semiconductor layer). The number of carriers (for example, electrons) in the layer increases. As a result, the on-resistance of the heterojunction field effect semiconductor device is lowered as compared with the case where a silicon nitride film is formed on one main surface of the main semiconductor region.
The invention of claim 15 has the following effects in addition to the effects (1) to (3).
(12) Electric field concentration can be relaxed satisfactorily by the gate field plate. Also, carriers trapped at the surface level of the main semiconductor region when a high voltage is applied to the heterojunction field effect semiconductor device can be effectively extracted through the gate field plate. As a result, a known current collapse can be suppressed, and an increase in on-resistance of the heterojunction field effect semiconductor device can be suppressed.
The invention of claim 16 has the following effects in addition to the effects (1) to (3) and (12).
(13) Since the gate field plate 11 is provided on the inclined side surface of the insulating film, the electric field concentration at the end of the gate electrode can be satisfactorily eased, and a high breakdown voltage can be achieved.
According to the invention of claim 17, it is possible to easily obtain a diode having a high operating speed using a two-dimensional carrier gas layer (for example, a 2DEG layer).
According to the invention of claims 18 to 20, a MESFET having normally-off characteristics or a similar field effect semiconductor device can be reliably obtained with the help of a p-type metal oxide semiconductor film.
According to the invention of claim 21, since the metal oxide semiconductor film is formed by sputtering in an atmosphere containing oxygen, a metal oxide semiconductor film having a high carrier concentration (density) can be easily obtained.

  Next, a heterojunction field effect semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

A heterojunction field effect semiconductor device according to Embodiment 1 of the present invention shown in FIG. 1A includes a substrate 1 made of a single crystal silicon semiconductor and a buffer layer 2 on one main surface 1a of the substrate 1. A main semiconductor region 3 including an electron transit layer 4 as a first semiconductor layer and an electron supply layer 5 as a second semiconductor layer, which are sequentially disposed, and a first semiconductor layer 3 disposed on the main semiconductor region 3. A source electrode 6 as a main electrode, a drain electrode 7 and a gate electrode 8 as a second main electrode, an insulating film 9 made of silicon oxide disposed on the main semiconductor region 3, and a p-type according to the present invention A metal oxide semiconductor film 10 and a gate field plate 11 are provided. Although this heterojunction field effect semiconductor device has an insulated gate structure different from that of a typical HEMT, it operates on the same principle as that of a typical HEMT, and can also be called a HEMT or a HEMT type semiconductor device. Hereinafter, each part of FIG. 1 will be described in detail.

  The substrate 1 has one main surface 1a and the other main surface 1b opposite thereto, and functions as a growth substrate for epitaxially growing semiconductor materials for the buffer layer 2 and the main semiconductor region 3, and It functions as a support substrate for supporting these mechanically. In this embodiment, the substrate 1 is made of silicon in order to reduce costs. However, the substrate 1 may be formed of a semiconductor such as silicon carbide (SiC) other than silicon, or an insulator such as sapphire or ceramic.

The buffer layer 2 on one main surface 1a of the substrate 1 is formed by an epitaxial growth method such as a well-known MOCVD method. In FIG. 1, the buffer layer 2 is shown as a single layer for the sake of simplicity, but actually, it is formed of a plurality of layers. In other words, the buffer layer 2 has alternating first sublayers (first sublayer) made of AlN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride). Is a multi-layered buffer laminated on the substrate. Since the buffer layer 2 is not directly related to the operation of the HEMT, it can be omitted. Further, the semiconductor material of the buffer layer 2 can be replaced with a nitride semiconductor other than AlN or GaN or a Group 3-5 compound semiconductor, or a buffer layer having a single layer structure can be formed.

The main semiconductor region 3 has one main surface 13 and the other main surface 14 facing each other, and the electron transit layer 4 as the first semiconductor layer is disposed on the other main surface 14 side, and the second semiconductor The electron supply layer 5 as a layer is disposed between the electron transit layer 4 and one main surface 13 . The electron transit layer 4 is made of a first nitride semiconductor and has a thickness of 0.3 to 10 μm. The electron transit layer 4 has a two-dimensional electron gas layer (2DEG layer) 12 (indicated by a dotted line) as a two-dimensional carrier gas layer that functions as a current path (channel) in the vicinity of the heterojunction surface with the electron supply layer 5 above. It is made of undoped GaN (gallium nitride) epitaxially grown by a known MOCVD method. The electron supply layer 5 is made of, for example, Al a In b Ga 1-ab N, other than GaN.
Here, a is a numerical value satisfying 0 ≦ a <1, b is 0 ≦ b <1,
It can also be formed of a nitride semiconductor such as, or another compound semiconductor.

The electron supply layer 5 formed on the electron transit layer 4 is preferably 10 by a second nitride semiconductor having a band gap larger than that of the electron transit layer 4 and having a lattice constant smaller than that of the electron transit layer 4. It is formed to a thickness of ˜50 nm (for example, 25 nm). The electron supply layer 5 of this embodiment is made of undoped Al 0.3 Ga 0.7 N epitaxially grown by a known MOCVD method. Note that the electron supply layer 5 can be formed of a nitride semiconductor other than Al 0.3 Ga 0.7 N, for example, represented by the following formula.
Al x In y Ga 1-xy N,
Here, x is a numerical value satisfying 0 <x <1, y is 0 ≦ y <1, a preferable value of x is 0.1 to 0.4, and a more preferable value is 0.3.
Instead of forming the electron supply layer 5 with undoped Al x In y Ga 1 -xy N, a nitride made of Al x In y Ga 1 -xy N to which an n-type (first conductivity type) impurity is added It can also be formed of a semiconductor, a nitride semiconductor of another composition, or another compound semiconductor.

A source electrode 6 and a drain electrode 7 are disposed on one main surface 13 of the main semiconductor region 3, and a recess 15 is provided. The recess 15 is formed by dry etching between the source electrode 6 and the drain electrode 7 on one main surface 13 of the main semiconductor region 3, and has a bottom surface 16 and a pair of side surfaces 17, and the electron supply layer 5. It is formed shallower than the thickness. Therefore, there is a thin remaining portion 18 of the electron supply layer 5 between the bottom surface 16 of the recess 15 and the electron transit layer 4. The remaining portion 18 of the electron supply layer 5 has a thickness of 0 to 20 nm, more preferably 2 to 15 nm, most preferably 3 to 8 nm, and 5 nm in FIG.
If normally-off characteristics can be obtained without providing the recess 15, the recess 15 can be omitted and the p-type metal oxide semiconductor film 10 can be disposed on the flat main surface of the electron supply layer 5. Further, the side surface 17 of the recess 15 can be an inclined surface.

The insulating film 9 made of silicon oxide is disposed in a portion other than the portion where the source electrode 6, the drain electrode 7, and the recess 15 are formed on one main surface 13 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Has been. More specifically, the insulating film 9 made of silicon oxide is made of SiO x (where x is a value from 1 to 2 and preferably 2), preferably plasma CVD (chemical vapor deposition). The two-dimensional carrier gas is preferably formed to a thickness of 300 to 700 nm (for example, 500 nm) by a method, and has a property of generating compressive stress, that is, compressive strain (for example, 4.00 × 10 9 dyn / cm 2 ). This contributes to increasing the carrier concentration of the layer 12. That is, since the electron supply layer 5 made of AlGaN is disposed under the insulating film 9 made of silicon oxide, this reaction occurs when the compressive stress of the insulating film 9 made of silicon oxide acts on the electron supply layer 5. As a result, extensible strain, that is, tensile stress is generated in the electron supply layer 5, the piezo polarization of the electron supply layer 5 is strengthened, and the electron concentration in the two-dimensional electron gas layer (2DEG layer) 12 increases. This increase in the electron concentration contributes to a reduction in resistance between the source electrode 6 and the drain electrode 7 when the heterojunction field effect semiconductor device is on. The insulating film 9 made of silicon oxide is not disposed in the recess 15 and has an opening corresponding to the recess 15. The wall surface of the opening of the insulating film 9 made of silicon oxide, that is, the side surface 19 adjacent to the entrance of the recess 15 has an inclination of 5 to 60 degrees.
The insulating film 9 made of silicon oxide can be formed by another method such as sputtering. However, plasma CVD is most excellent for reducing crystal damage on one main surface 13 of the main semiconductor region 3, reducing surface states (traps), and suppressing current collapse. The insulating film 9 can also be formed of another insulating material (for example, silicon nitride) other than silicon oxide.

The p-type metal oxide semiconductor film 10 according to the present invention is disposed so as to cover the bottom surface 16 and the side surface 17 of the recess 15 and part of the insulating film 9 made of silicon oxide, and has a higher resistivity than the electron supply layer 5. The metal oxide semiconductor material has a thickness of preferably 3 to 1000 nm, more preferably 10 to 500 nm. When the p-type metal oxide semiconductor film 10 is thinner than 3 nm, the normally-off characteristic cannot be obtained satisfactorily, and when it is thicker than 1000 nm, the turn-on characteristic by the control of the gate electrode 8 is deteriorated.
Note that the p-type metal oxide semiconductor film 10 may be limited to the recess 15 so as not to extend on the insulating film 9.
The p-type metal oxide semiconductor film 10 of this embodiment is made of nickel oxide (NiO x , where x is an arbitrary numerical value, for example, 1) formed by magnetron sputtering and having a thickness of 200 nm. When the p-type metal oxide semiconductor film 10 is formed, the main semiconductor region 3 is provided on one main surface 1a of the substrate 1 via the buffer layer 2, and the insulating film 9 made of silicon oxide is further provided. A p-type metal oxide semiconductor film is placed in a magnetron sputtering apparatus, the inside of the magnetron sputtering apparatus is an atmosphere containing oxygen (preferably a mixed gas of argon and oxygen), and nickel oxide (NiO) is sputtered. Get 10. When nickel oxide is sputtered in an atmosphere containing oxygen, the p-type metal oxide semiconductor film 10 having a high hole concentration can be easily obtained.
In this embodiment, the p-type metal oxide semiconductor film 10 is patterned simultaneously with the patterning of the gate field plate 11 and the gate electrode 8, but the p-type metal oxide semiconductor film 10 is patterned in an independent process. You can also.
A p-type metal oxide semiconductor film 10 formed by sputtering nickel oxide in an oxygen-containing atmosphere has a higher hole concentration than GaN doped with a conventional p-type impurity and is relatively large. Has resistivity. Therefore, the p-type metal oxide semiconductor film 10 raises the potential under the gate electrode 8 relatively high to prevent the two-dimensional electron gas layer from being formed in the portion of the electron transit layer 4 below the gate electrode 8. To do. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained. The p-type metal oxide semiconductor film 10 contributes to a reduction in gate leakage current (leakage current) during HEMT operation.

Instead of forming the p-type metal oxide semiconductor film 10 with the above nickel oxide, iron oxide (FeO x , where x is an arbitrary numerical value, for example, 2), cobalt oxide (CoO x, where x Is an arbitrary numerical value, for example, 2), manganese oxide (MnO x , where x is an arbitrary numerical value, for example, 1), and copper oxide (CuO x , where x is an arbitrary value) It is also a numerical value, for example, 1). The p-type metal oxide semiconductor film made of a metal oxide other than nickel oxide is also preferably formed by sputtering a metal material in an atmosphere containing oxygen.
The p-type metal oxide semiconductor film 10 may be formed by forming a metal film by sputtering or the like and then oxidizing the metal film instead of forming the metal material by sputtering in an atmosphere containing oxygen. it can.
Further, in order to enhance the p-type characteristics of the p-type metal oxide semiconductor film 10, the p-type metal oxide semiconductor film 10 is subjected to heat treatment, ozone ashing treatment, or O 2 (oxygen). ) Ashing processing can be performed.

  For the source electrode 6 and the drain electrode 7, for example, titanium (Ti) is vapor-deposited to a desired thickness (for example, 25 nm) on one main surface 13 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Each of them is formed by vapor-depositing (Al) to a desired thickness (for example, 300 nm) and then forming a desired pattern by a photolithographic technique. The source electrode 6 and the drain electrode 7 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but are formed of a metal capable of low resistance contact (ohmic contact) other than this. You can also Since the electron supply layer 5 in the main semiconductor region 3 is extremely thin, the resistance in the thickness direction is negligibly small. Accordingly, the source electrode 6 and the drain electrode 7 are electrically coupled to the 2DEG layer 12 as a current path.

The gate electrode 8 is made of a metal layer deposited on the p-type metal oxide semiconductor film 10 and faces the bottom surface 16 of the recess 15 with the p-type metal oxide semiconductor film 10 interposed therebetween. As shown in FIG. 1B, the gate electrode 8 of this embodiment is formed by vapor deposition on a p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx), and a nickel (Ni) layer 81 having a thickness of 30 nm. A 300 nm thick gold (Au) layer 82 is formed on the nickel layer 81 by vapor deposition. Depending on the combination of the p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx), the nickel (Ni) layer 81, and the gold (Au) layer 82, the gate leakage current can be satisfactorily reduced. However, the gate electrode 8 can be formed of a multilayer film of a nickel (Ni) layer, a gold (Au) layer, and a titanium layer, an aluminum layer, a conductive polysilicon layer, or the like.
The gate field plate 11 is electrically connected to the gate electrode 8 and is formed continuously with the gate electrode 8. An insulating film 9 made of silicon oxide and a p-type metal oxide semiconductor film 10 are formed on the surface of the electron supply layer 5. Are facing each other. Since the insulating film 9 made of silicon oxide has inclined side surfaces 19 of 5 to 60 degrees, the distance between the gate field plate 11 and the electron supply layer 5 gradually increases as the distance from the gate electrode 8 on the bottom surface 16 of the recess 15 increases. doing. Thereby, the relaxation of the electric field concentration at the end of the gate electrode 8 can be achieved satisfactorily.

In the heterojunction field effect semiconductor device of FIG. 1, when the gate control voltage is not applied to the gate electrode 8 (when the gate voltage is zero), even if the potential of the drain electrode 7 is higher than the potential of the source electrode 6. Even if it is higher, the recess 15 is provided corresponding to the gate electrode 8, the electron supply layer 5 is thinned under the gate electrode 8, and the p-type metal oxide semiconductor film 10 is formed between the gate electrode 8 and the electron supply layer 5. 2DEG layer is not formed in the electron transit layer 4 below the gate electrode 8, the 2DEG layer 12 is divided, and the source electrode 6 and the drain electrode 7 are turned off. .

2A is an energy level diagram of a recess of the heterojunction field-effect semiconductor device of FIG. 1, and FIG. 2B is an energy level of a conventional Schottky gate structure HEMT (hereinafter referred to as Comparative Example 1). FIG. 2C is a HEMT having a conventional Schottky gate structure in which an electron supply layer immediately below the gate electrode is thinly processed, that is, a HEMT having a structure in which the p-type metal oxide semiconductor film 10 is removed from FIG. 2) is shown. In these figures, E F represents the Fermi level, and E C represents the boundary level between the conduction band and the forbidden band. Ni represents the gate electrode 8, NiO represents the p-type metal oxide semiconductor film 10, AlGaN represents the electron supply layer 5, and GaN represents the electron transit layer 4.
In the heterojunction field effect semiconductor device of FIG. 1, since the electron supply layer 5 under the gate electrode 8 is as thin as 5 nm or less, the lattice is formed in the electron supply layer 5 under the gate electrode 8 as in FIG. Relaxation occurs, the charge due to piezo polarization is reduced, and the bulk characteristics are diminished and the charge due to spontaneous polarization is also reduced. The reduction of these charges in the electron supply layer 5 causes a decrease in Fermi level, and the potential under the gate electrode 8 is relatively increased. Further, since the p-type metal oxide semiconductor film 10 is provided, the potential under the gate electrode 8 is raised as shown in FIG. As a result, a two-dimensional carrier gas layer is not formed in the portion of the electron transit layer 4 facing the gate electrode 8, and a heterojunction field effect semiconductor device having normally-off characteristics is obtained. In other words, at the normal time, the polarization of the remaining portion 18 under the recess 15 of the electron supply layer 5 is canceled by the p-type metal oxide semiconductor film 10 and faces the gate electrode 8 of the electron transit layer 4. A two-dimensional carrier gas layer is not formed on the part to be formed.

When a positive gate control voltage higher than a predetermined threshold voltage is applied between the gate electrode 8 and the source electrode 6 in a state where the potential of the drain electrode 7 is higher than the potential of the source electrode 6, a known MOS gate structure is used. A channel (current path) is formed in a portion of the electron transit layer 4 facing the gate electrode 8 based on the same principle as the formation of the channel (current path). That is, when a positive gate control voltage is applied to the gate electrode 8, polarization occurs in the p-type metal oxide semiconductor film 10, holes collect on the electron supply layer 5 side of the p-type metal oxide semiconductor film 10, Electrons are induced on the side of the electron transit layer 4 in contact with the electron supply layer 5 to form a channel. As a result, the source electrode 6 and the drain electrode 7 are turned on, and electrons are supplied to the source electrode 6, the electron supply layer 5, the 2DEG layer 12, the channel, the 2DEG layer 12, the electron supply layer 5, and the drain electrode 7. It flows along the route. As is well known, since the electron supply layer 5 is extremely thin, electrons pass through this thickness direction by the tunnel effect.

The characteristic line A in FIG. 3 shows the relationship between the drain-source voltage Vds and the gate leakage current (leakage current) Ig of the heterojunction field effect semiconductor device of Example 1 in FIG. 1, and the characteristic line B is a comparative example. 1 shows the relationship between the drain-source voltage Vds and the gate leakage current Ig, and the characteristic line C shows the relationship between the drain-source voltage Vds and the gate leakage current Ig of Comparative Example 2. The gate leakage current Ig on the characteristic lines A, B, and C indicates the gate-drain current when the gate-source voltage Vgs is kept at zero.
As is clear from the comparison of the characteristic lines A, B, and C in FIG. 3, the gate leakage current Ig of the heterojunction field effect semiconductor device of Example 1 is significantly smaller than the gate leakage current Ig of Comparative Examples 1 and 2. .

The heterojunction field effect semiconductor device of Example 1 of FIG. 1 has the following effects.
(1) The p-type metal oxide semiconductor film 10 formed by sputtering (magnetron sputtering) in an oxygen-containing atmosphere has a higher hole concentration than GaN doped with a conventional p-type impurity. The p-type metal oxide semiconductor film 10 having a high hole concentration pulls up the potential under the gate electrode 8 well, and a two-dimensional electron gas layer is formed in the electron transit layer 4 under the gate electrode 8 during normal operation. Is well suppressed. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained.
(2) The p-type metal oxide semiconductor film 10 has a relatively high resistivity (insulating property) and is formed relatively thick (for example, 10 to 500 nm). Therefore, the gate leakage current during the operation of the heterojunction field effect semiconductor device is reduced, the breakdown voltage of the heterojunction field effect semiconductor device is improved, and the reliability is improved. Note that the threshold voltage does not shift to the negative side even if the p-type metal oxide semiconductor film 10 is formed relatively thick. In particular, when the p-type metal oxide semiconductor film 10 is made of nickel oxide (NiOx) and the gate electrode 8 is made of a nickel (Ni) layer 81 and a gold (Au) layer 82 as shown in FIG. A good effect of reducing the gate leakage current can be obtained.
(3) Since the p-type metal oxide semiconductor film 10 is made of a chemically stable substance and can be formed in an atmosphere containing oxygen, it is easy to manufacture.
(4) The normally-off characteristic is not only obtained by reducing the thickness of the remaining portion 18 below the recess (recess) 15 of the electron supply layer 5 but also between the recess (recess) 15 and the p-type metal oxide semiconductor film 10. Get in combination. Therefore, the thickness of the remaining portion 18 under the recess 15 of the electron supply layer 5 can be made relatively thick as 3 to 8 nm. As a result, when a control voltage for turning on the heterojunction field effect semiconductor device is applied to the gate electrode 8, the electron concentration in the portion of the electron transit layer 4 facing the gate electrode 8 can be made relatively high. The on-resistance can be made relatively low, and the maximum allowable current Imax of the heterojunction field effect semiconductor device can be increased.
(5) The portions of the electron supply layer 5 between the source electrode 6 and the gate electrode 8 and between the drain electrode 7 and the gate electrode 8 are formed relatively thick so as to be 10 nm or more, and Al in the electron supply layer 5 is formed. The ratio of (aluminum) is relatively large, for example 0.1 or more. For this reason, although the heterojunction field effect semiconductor device has normally-off characteristics, the electron concentration of the 2DEG layer 12 is relatively large and the on-resistance is relatively low. As a result, the maximum allowable current Imax of the heterojunction field effect semiconductor device can be increased.
(6) The insulating film 9 made of silicon oxide formed on one main surface 13 of the main semiconductor region 3 has a property of generating compressive stress (for example, 4.00 × 10 9 dyn / cm 2 ). When the compressive stress of the insulating film 9 made of silicon oxide acts on one main surface 13 of the main semiconductor region 3, that is, the main surface of the electron supply layer 5, electrons in the 2DEG layer 12 based on the piezoelectric polarization of the electron supply layer 5 are transferred. Become more. Thereby, the on-resistance of the heterojunction field effect semiconductor device is lower than that of a conventional heterojunction field effect semiconductor device in which a silicon nitride film is formed on one main surface 13 of the main semiconductor region 3. Further, the gate leakage current is reduced by the insulating film 9 made of silicon oxide.
(7) Since the gate field plate 11 is provided, and the inclined side surface 19 of 5 to 60 degrees is provided in the insulating film 9 made of silicon oxide, the electric field concentration at the end of the gate electrode 8 is satisfactorily reduced. And a high breakdown voltage can be achieved.
(8) Since the gate field plate 11 is provided, the electrons trapped in the surface level of the main semiconductor region 3 when the reverse voltage is applied between the drain and the source via the gate field plate 11. 8 can be pulled out, and current collapse can be reduced.
(9) By forming the p-type metal oxide semiconductor film 10 by magnetron sputtering in an atmosphere containing oxygen, the p-type metal oxide semiconductor film 10 having a relatively large thickness and a relatively high hole concentration can be easily obtained. be able to.
(10) The p-type metal oxide semiconductor film 10 is subjected to a heat treatment, an ozone ashing process, or an O 2 (oxygen) ashing process. The p-type characteristics (hole concentration) can be easily enhanced.

Next, a heterojunction field effect semiconductor device according to the second embodiment shown in FIG. 4 will be described. 4 that are substantially the same as those in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device of Example 2 of FIG. 4 is formed substantially the same as FIG. 1 except that it has a modified main semiconductor region 3a. The deformed main semiconductor region 3a includes the electron transit layer 4 as the first semiconductor layer and the first, second, and second semiconductor layers as the first, second, third, and fourth semiconductor layers formed in the same manner as FIG. 3 electron supply layers 21, 22, and 23. That is, the main semiconductor region 3a in FIG. 4 includes first, second, and third electron supply layers 21, 22, and 23 that are sequentially stacked instead of the one electron supply layer 5 in FIG. Also, the main semiconductor region 3a in FIG. 4 has a recess 15c corresponding to the recess 15 in FIG. The recess 15a in FIG. 4 is formed in the same manner as the recess 15 in FIG. 1 except that the recess 15a has an inclined side wall 17a.

The first electron supply layer 21 heterojunction with the electron transit layer 4 has a band gap larger than that of the electron transit layer 4 and a lattice constant smaller than that of the electron transit layer 4 and is made of Al (aluminum). Preferably it consists of a nitride semiconductor contained in a proportion of 0.1 to 0.3, and preferably has a thickness of 5 nm to 10 nm. The first electron supply layer 21 of Example 2 is made of undoped Al 0.26 Ga 0.74 N epitaxially grown by a known MOCVD method and has a thickness of 7 nm. Therefore, the proportion of Al in the first electron supply layer 21 is smaller than the proportion of Al in the electron supply layer 5 of FIG. 1, and the thickness is thinner than that of the electron supply layer 5 in FIG. The first electron supply layer 21 having a smaller Al ratio than the electron supply layer 5 in FIG. 1 functions to make the threshold voltage of the heterojunction field effect semiconductor device more positive, and the depth of the recess 15a. It has a function of reducing the variation in threshold voltage due to the variation in thickness.
Note that the first electron supply layer 21 may be formed of a nitride semiconductor other than Al 0.26 Ga 0.74 N, for example, represented by the following formula.
Al x In y Ga 1-xy N,
Here, x is a numerical value satisfying 0.1 <x <0.3 and y is 0 ≦ y <1.

The second electron supply layer 22 disposed on the first electron supply layer 21 has a band gap larger than that of the electron transit layer 4 and a lattice constant smaller than that of the electron transit layer 4, and the first electron supply layer 22. It is made of an n-type nitride semiconductor containing Al (aluminum) at a ratio larger than that of the electron supply layer 21 and has a thickness of 5 nm. The thickness of the second electron supply layer 22 is desirably in the range of 3 nm to 25 nm. The second electron supply layer 22 of this embodiment is made of Al 0.34 Ga 0.66 N epitaxially grown by a known MOCVD method and contains Si as an n-type impurity. Therefore, the proportion of Al in the second electron supply layer 22 is larger than the proportion of Al in the first electron supply layer 21, and the electron concentration in the second electron supply layer 22 is the electron concentration in the first electron supply layer 21. Higher than. The second electron supply layer 22 contributes to increasing the electron concentration in the 2DEG layer 12 of the electron transit layer 4. However, since the recess 15 under the gate electrode 8 is formed so as to penetrate the second electron supply layer 22, the second electron supply layer 22 does not deteriorate normally-off characteristics.
Note that the second electron supply layer 22 may be formed of a nitride semiconductor other than Al 0.34 Ga 0.66 N, for example, represented by the following formula.
Al x In y Ga 1-xy N,
Here, x is a numerical value satisfying 0.2 <x <0.5, and y is 0 ≦ y <1.

The third electron supply layer 23 disposed on the second electron supply layer 22 has a band gap larger than that of the electron transit layer 4 and has a lattice constant smaller than that of the electron transit layer 4 and the second. It is made of an undoped nitride semiconductor containing Al (aluminum) at a proportion smaller than that of the electron supply layer 22 and has a thickness of 13 nm. The thickness of the third electron supply layer 23 is desirably in the range of 10 nm to 150 nm. The third electron supply layer 23 of this embodiment is made of undoped Al 0.30 Ga 0.70 N epitaxially grown by a known MOCVD method. Therefore, the proportion of Al in the third electron supply layer 23 is smaller than the proportion of Al in the second electron supply layer 22. The third electron supply layer 23 made of a nitride semiconductor that is undoped and has a lower Al ratio than the second electron supply layer 22 contributes to control of the surface charge of the main semiconductor region 3a.
Note that the third electron supply layer 23 may be formed of a nitride semiconductor other than Al 0.30 Ga 0.70 N, for example, represented by the following formula.
Al x In y Ga 1-xy N,
Here, x is a numerical value satisfying 0 ≦ x <0.4, and y is 0 ≦ y <1.

The recess 15a extends from one main surface 1a of the main semiconductor region 3a to the first electron supply layer 21 through the third electron supply layer 23 and the second electron supply layer 22, and further reaches the first electron supply layer 21. It is formed so as to bite into the electron supply layer 21. Therefore, only the remaining portion 18 of the first electron supply layer 21 is disposed between the recess 15 a and the electron transit layer 4. In the embodiment of FIG. 4, the recess 15 a bites into the first electron supply layer 21, but the recess 15 a can be modified so as not to bite into the first electron supply layer 21. In any case, if the p-type metal oxide semiconductor film 10 is not provided, a 2DEG layer is formed in a portion facing the gate electrode 8 of the electron transit layer 4 in a normally state, and the p-type metal oxide semiconductor is formed. In the case where the film 10 is provided, the depth of the recess 15a is set so that the 2DEG layer does not occur in the portion facing the gate electrode 8 of the electron transit layer 4 in the normally state.

The side surface 17a of the recess (recess) 15a has an inclination of 15 to 80 degrees so that the recess (recess) 15a is tapered. The inclination angle of the side surface 17 a of the recess (recess) 15 a is slightly larger than the inclination angle (5 to 60 degrees) of the side surface 19 of the opening of the insulating film 9. Of course, also in FIG. 4, the side surface 17a of the recess 15a can be formed substantially perpendicular to the side surface 17 of the recess 15 in FIG. Since the p-type metal oxide semiconductor film 10 has a relatively high resistance, the field plate 11 is insulated by the field plate 11 facing the main semiconductor region 3a through the p-type metal oxide semiconductor film 10. The same effect as the electric field concentration mitigation effect obtained by facing the main semiconductor region 3a through the film 9 can be obtained. In addition, since the second electron supply layer 22 having a relatively high electron concentration is exposed at the side surface 17a of the recess 15a, the effect of reducing the electric field concentration by the field plate 11 can be obtained satisfactorily.

5 shows the gate-source voltage Vgs and drain-source of the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the heterojunction field effect semiconductor devices of the first, second and third comparative examples. The relationship with the inter-current Ids is shown.
That is, in the characteristic line A1, the recess (recess) 15a and the p-type metal oxide semiconductor film 10 are omitted from FIG. 4, and a gate electrode made of a Ni / Au laminate is provided on one main surface 13 of the main semiconductor region 3a. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 1st comparative example of a structure is shown.
The characteristic line A2 is the p-type metal oxide semiconductor film 10 omitted from FIG. 4, the recess (recess) 15a and the field plate 11 are provided, and the gate electrode made of a Ni / Au laminate is provided on the recess (recess) 15a. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 2nd comparative example of a structure is shown.
The characteristic line B1 is obtained by omitting the recess (recess) 15a from FIG. 4 and providing a p-type metal oxide semiconductor film 10 made of nickel oxide (NiO x ) having a thickness of 200 nm, on the p-type metal oxide semiconductor film 10. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 3rd comparative example of the structure provided with the gate electrode which consists of a Ni / Au laminated body is shown.
The characteristic line B2 indicates the structure shown in FIG. 4, that is, the structure obtained by adding the recess 15a and the field plate 11 to the third comparative example, that is, the Vgs-Ids of the telojunction field effect semiconductor device having the structure according to the second embodiment. Show properties.

The threshold voltages of the characteristic lines A1, A2, and B1 of the first, second, and third comparative examples in FIG. 5 are all negative. On the other hand, the threshold voltage of the characteristic line B2 of Example 2 is positive. Accordingly, a normally-off type heterojunction field effect semiconductor device having a positive threshold voltage, that is, a field effect semiconductor device having a HEMT or a HEMT-like structure can be obtained according to the second embodiment.

FIG. 6 shows the drain-source voltage Vds and gate leakage of the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the heterojunction field effect semiconductor devices of the first, second and third comparative examples. The relationship with the current Ig is shown.
That is, the characteristic line C1 shows the Vds-Ig characteristic of the first comparative example.
A characteristic line C2 shows the Vds-Ig characteristic of the second comparative example.
A characteristic line D1 indicates the Vds-Ig characteristic of the heterojunction field effect semiconductor device having a structure in which the field plate 11 is omitted from the third comparative example.
A characteristic line D2 shows the Vds-Ig characteristic of Example 2.
Note that the gate leakage current Ig in each characteristic of FIG. 6 indicates the gate-drain current when the gate-source voltage Vgs is kept at zero.

The gate leakage current Ig of Example 2 indicated by the characteristic line D2 is smaller than the gate leakage currents Ig of the first, second, and third comparative examples of the characteristic lines C1, C2, and D1. That is, when the field plate 11 is provided and the p-type metal oxide semiconductor film 10 having a high resistivity is provided, the gate leakage current is suppressed and the breakdown voltage is improved. As already explained,

In addition to the same effects as the first embodiment of FIG. 1, the second embodiment of FIG. 4 has the following effects.
(1) Since the first electron supply layer 21 having a low Al ratio is disposed adjacent to the electron transit layer 4, a positive threshold voltage can be obtained with certainty.
(2) The second electron supply layer 22 disposed adjacent to the first electron supply layer 21 has a higher Al ratio than the first electron supply layer 21 and is higher than the first electron supply layer 21. Since it has a high electron concentration, the electron concentration of the 2DEG layer 12 in a portion other than the recess 15a of the main semiconductor region 3a can be increased, and the on-resistance of the heterojunction field effect semiconductor device can be reduced. That is, if the second and third electron supply layers 22 and 23 are omitted in FIG. 4, the electron supply layer is configured by only the first electron supply layer 21 whose Al ratio is lower than that of the electron supply layer 5 of FIG. 1. Then, the electron concentration of the 2DEG layer 12 becomes lower than the electron concentration of the 2DEG layer 12 of FIG. However, as shown in FIG. 4, the first electron supply layer 21 has a higher Al ratio than the first electron supply layer 21 and a higher electron concentration than the first electron supply layer 21. When the second electron supply layer 22 is disposed, the second electron supply layer 22 can compensate for a decrease in the electron concentration of the 2DEG layer 12 due to the provision of the first electron supply layer 21. As a result, the on-resistance of the heterojunction field-effect semiconductor device of FIG. 4 is the same as or lower than the on-resistance of the heterojunction field-effect semiconductor device of FIG. Since the recess 15a penetrates the second electron supply layer 22, the second electron supply layer 22 does not interfere with the normally-off characteristic.
(3) Since the recess 15a is provided so as to reach the first electron supply layer 21 in which the proportion of Al is low, the variation in threshold voltage due to the variation in the depth of the recess 15a is reduced. That is, if the ratio of Al and the electron concentration in the remaining portion 18 of the first electron supply layer 21 under the recess 15a is large, the variation in threshold voltage due to the variation in the thickness of the remaining portion 18 increases. In FIG. 4, since the ratio of Al in the remaining portion 18 is smaller than the ratio of Al in the remaining portion 18 in FIG. 1, the variation in threshold voltage due to the variation in the thickness of the remaining portion 18 is also reduced.
(4) Since the concave portion 15a has an inclined side surface 17a and the second electron supply layer 22 having a high electron concentration is exposed on the inclined side surface 17a, the electric field concentration in the vicinity of the gate electrode 8 is reduced. be able to. Since the field plate 11 is provided on the inclined side surface 17a of the recess 15a via the p-type metal oxide semiconductor film 10 having a resistivity that can be regarded as an insulator, the vicinity of the inclined side surface 17a of the recess 15a is provided. In this case, the field plate effect can be obtained. Thereby, the electric field concentration in the vicinity of the gate electrode 8 is further relaxed, and high resistance is achieved.
(5) Since the third electron supply layer 23 having a lower Al ratio than the second electron supply layer 22 is provided and this surface is one main surface of the main semiconductor region 3a, the main semiconductor region 3a It is possible to stabilize one of the main surfaces, and it becomes possible to reduce leakage current and suppress current collapse.

Next, a heterojunction field effect semiconductor device according to Example 3 shown in FIG. 7 will be described. 7 that are substantially the same as those in FIGS. 1 and 4 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device of Example 3 of FIG. 7 is formed substantially the same as FIG. 4 except that it has a modified main semiconductor region 3b. The main semiconductor region 3b in FIG. 7 is configured by only the first and second electron supply layers 21 and 22 ′ by omitting the third electron supply layer 23 from the main semiconductor region 3a in FIG. The first electron supply layer 21 in FIG. 7 is configured in the same way as in FIG. 4, and the second electron supply layer 22 ′ is formed thicker than the second electron supply layer 22 in FIG. 4 is the same. The thickness of the second electron supply layer 22 ′ in FIG. 7 is 18 nm selected from the preferred range of 10 to 150 nm.

The composition of the first and second electron supply layers 21 and 22 'in the main semiconductor region 3b of Example 3 in FIG. 7 is the same as that of the first and second electron supply layers in the main semiconductor region 3a of Example 2 in FIG. Since the compositions are the same as those in FIGS. 21 and 22, Example 3 in FIG. 7 has the same effect as Example 2 in FIG. 4 except for the effect of the third electron supply layer 23 in Example 2 in FIG. .
Note that the second electron supply layer 22 ′ in the main semiconductor region 3 b of Example 3 in FIG. 7 can be transformed into a nitride semiconductor layer not doped with an n-type impurity (for example, Si). This undoped nitride semiconductor layer has the same function as a known cap layer for the purpose of controlling surface charge.

Next, a heterojunction field effect semiconductor device according to the fourth embodiment shown in FIG. 8 will be described. 8 that are substantially the same as those in FIGS. 1 and 4 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device of Example 4 of FIG. 8 is formed substantially the same as FIG. 4 except that it has a modified main semiconductor region 3c. The main semiconductor region 3c in FIG. 8 has a fourth electron supply layer 24 that can be called an ohmic contact layer added to the main semiconductor region 3a in FIG. 4 and is thinner than the third electron supply layer 23 in FIG. 3 except that the third electron supply layer 23 'is provided. The third electron supply layer 23 ′ in FIG. 8 has a thickness of 13 nm selected from a preferable range of 5 to 140 nm, and the fourth electron supply layer 24 has an Al ratio higher than that of the third electron supply layer 23 ′. The n-type nitride semiconductor is preferably low or zero. In this embodiment, the n-type nitride semiconductor is made of GaN doped with Si as an n-type impurity, and has a thickness of 13 nm selected from a preferable range of 3 to 100 nm.
Note that the fourth electron supply layer 24 can also be formed of a nitride semiconductor other than GaN, for example, represented by the following formula, ignoring n-type impurities.
Al x In y Ga 1-xy N,
Here, x is a numerical value satisfying 0 ≦ x <0.4, and y is 0 ≦ y <1.

The heterojunction field effect semiconductor device according to the fourth embodiment shown in FIG. 8 has the same effect as that of the second embodiment of FIG. 4, and the fourth electron supply layer 24 is made of Si-doped GaN. There is an effect that the ohmic contact with respect to the main semiconductor region 3c of the electrode 6 and the drain electrode 7 is improved. In FIG. 8, since the recess 15a penetrates the fourth electron supply layer 24, the fourth electron supply layer 24 does not affect normally-off characteristics.

Next, a heterojunction field effect semiconductor device according to the fifth embodiment shown in FIG. 9 will be described. 9 that are substantially the same as those in FIGS. 1 and 4 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device according to the fifth embodiment shown in FIG. 9 has a second insulating film 30 added to the heterojunction field effect semiconductor device according to the second embodiment shown in FIG. They are formed identically. The second insulating film 30 is made of metal oxide, silicon oxide, or the like, and is disposed between the p-type metal oxide semiconductor film 10, the gate electrode 8, and the field plate 11, and contributes to reduction of gate leakage current. . The thickness of the second insulating film 30 is determined so that the field effect action based on the gate electrode 8 can reach the electron transit layer 4. Since the heterojunction field effect semiconductor device of Example 5 of FIG. 9 is configured in the same manner as Example 2 of FIG. 4 except for the second insulating film 30, the same effect as that of Example 2 of FIG. Also have.
Note that a material similar to the second insulating film 30 in FIG. 9 can be added to the heterojunction field-effect semiconductor device in FIGS.

Next, a heterojunction field effect semiconductor device according to Example 6 shown in FIG. 10 will be described. 10 that are substantially the same as those in FIGS. 1 and 4 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device of Example 6 in FIG. 10 is formed substantially the same as FIG. 4 except that it has a modified main semiconductor region 3d, source electrode 6a, and drain electrode 7a. The main semiconductor region 3d in FIG. 10 has a well-known spacer layer 31 added to the main semiconductor region 3a in FIG. 4 and is provided with a source electrode recess (recess) 32 and a drain electrode recess (recess) 33 in FIG. The main semiconductor region 3a has the same configuration. The spacer layer 31 has a thickness smaller than that of the first electron supply layer 21 and is disposed between the electron transit layer 4 and the first electron supply layer 21, and the first to third electron supply layers. The impurities or elements of 21, 22, and 23 are prevented from diffusing into the electron transit layer 4, and the decrease in electron mobility in the 2DEG layer 12 is suppressed. The spacer layer 31 and the first electron supply layer 21 may be collectively referred to as the second semiconductor layer of the present invention. The source electrode recess (recess) 32 and the drain electrode recess (recess) 33 penetrate the third and second electron supply layers 23 and 22 in the same manner as the recess 15a below the gate electrode 8. It is formed on one main surface 13 of the main semiconductor region 3 d so as to reach one electron supply layer 21. The source electrode 6 a and the drain electrode 7 a are disposed in the source electrode recess (recess) 32 and the drain electrode recess (recess) 33, respectively, and are electrically coupled to the 2DEG layer 12. Therefore, the electrical resistance between the source electrode 6a and the drain electrode 7a and the 2DEG layer 12 of the electron transit layer 4 is smaller than the electrical resistance of the similar part in the structure of FIG.
Since the heterojunction field effect semiconductor device of Example 6 in FIG. 10 is configured in the same way as in FIG. 4 except for the modified points, it also has the same effect as in Example 2 of FIG.

The source electrode recess (recess) 32 and the drain electrode recess (recess) 33 may be formed to a depth reaching the electron transit layer 4.
Further, as indicated by chain lines in FIG. 10, a source contact region 41 and a drain contact region 42 each including an n-type impurity implantation region are provided below the source electrode 6a and the drain electrode 7a, and the source electrode 6a and the drain electrode 7a are provided here Ohmic contact can be made.
Further, one selected from the spacer layer 31, the source electrode recess (recess) 32, the drain electrode recess (recess) 33, the source electrode 6a, the drain electrode 7a, the source contact region 41, and the drain contact region 42 of FIG. Alternatively, a plurality or all of them can be provided in the heterojunction field effect semiconductor device shown in FIGS. 1, 4, 7, 8, and 9.

Next, a heterojunction field effect semiconductor device according to Example 7 shown in FIG. 11 will be described. However, in FIG. 11, the same reference numerals are given to substantially the same parts as those in FIGS. 1 and 4, and the description thereof is omitted.

The heterojunction field effect semiconductor device of Example 7 of FIG. 11 is formed substantially the same as FIG. 4 except that it has a modified p-type metal oxide semiconductor film 10 ′. The modified p-type metal oxide semiconductor film 10 ′ in FIG. 11 is formed so as not to extend on the insulating film 9. Therefore, the field plate 11 is in direct contact with the insulating film 9. Thereby, the effect of the field plate 11 is improved. Since the heterojunction field effect semiconductor device according to the seventh embodiment shown in FIG. 11 has the same configuration as that shown in FIG. 4 except for the modified points, the same effect as that of the second embodiment shown in FIG. 4 is obtained.
Note that a layer corresponding to the p-type metal oxide semiconductor film 10 ′ in FIG. 11 can be provided in the heterojunction field effect semiconductor device illustrated in FIGS. 1, 7, 8, 9, and 10.

Next, a heterojunction field effect semiconductor device according to Example 8 shown in FIG. 12 will be described. However, in FIG. 12, the same reference numerals are assigned to substantially the same parts as those in FIGS. 1 and 4, and the description thereof is omitted.

The heterojunction field effect semiconductor device of Example 8 of FIG. 12 is formed substantially the same as FIG. 4 except that it has a conductor 50 for obtaining a diode function. The conductor 50 electrically connects the gate electrode 8 and the source electrode 6 as the first electrode. The conductor 50 is disposed on the insulating film 9 and connects the one end connected to the source electrode 6 and the field plate 11. And the other end connected to the gate electrode 8, and is formed of the same metal as the gate electrode 8 and the field plate 11. Of course, the conductor 50 may be formed of a metal different from that of the gate electrode 8 and the field plate 11.

The heterojunction field effect semiconductor device of FIG. 12 in which the gate electrode 8 and the source electrode 6 are short-circuited by the conductor 50 operates as a diode having a high operating speed. That is, if the gate electrode 8 and the source electrode 6 are not short-circuited by the conductor 50 in FIG. 12, it operates as a normally-off heterojunction field effect semiconductor device as in FIG. In the state where the gate electrode 8 and the source electrode 6 are short-circuited by the conductor 50 as shown in FIG. 12, the potential of the drain electrode 7 as the second electrode is higher than the potential of the source electrode 6 as the first electrode. When it is high, the potential of the gate electrode 8 is the same as the potential of the source electrode 6 and is lower than the potential of the electron transit layer 4. As a result, an action of discharging electrons from the portion of the electron transit layer 4 facing the gate electrode 8 occurs, and the gap between the source electrode 6 and the drain electrode 7 is maintained in an off state. On the contrary, when the potential of the source electrode 6 as the first electrode is higher than the potential of the drain electrode 7 as the second electrode, the potential of the gate electrode 8 is the same as the potential of the source electrode 6. Therefore, the potential of the gate electrode 8 becomes higher than the potential of the drain electrode 7 and the potential of the electron transit layer 4, and when the voltage between the gate electrode 8 and the electron transit layer 4 becomes equal to or higher than the threshold voltage, the electron transit layer 4. A channel is formed at a portion facing the gate electrode 8, and the source electrode 6 and the drain electrode 7 are turned on. The above operation of the heterojunction field effect semiconductor device of FIG. 12 is a diode operation.

In FIG. 12, the source electrode 6 and the gate electrode 8 are short-circuited by the conductor 50 on the insulating film 9, but instead, the source electrode 6 and the gate electrode 8 can be short-circuited by an external conductor or an external switch circuit. .
Since the heterojunction field effect semiconductor device of FIG. 12 is configured in the same way as in FIG. 4 except for the conductor 50, it also has the same effect as the embodiment 2 of FIG.
12 may be provided in the heterojunction field effect semiconductor device shown in FIGS. 1, 7, 8, 9, 10, and 11. FIG.

Next, a field effect semiconductor device similar to the MESFET according to the ninth embodiment shown in FIG. 13 will be described. However, in FIG. 13, substantially the same parts as those in FIGS. 1 and 4 are denoted by the same reference numerals, and the description thereof is omitted.

The field effect semiconductor device of Example 9 in FIG. 13 has the same configuration as that in FIG. 4 except for the deformed main semiconductor region 3e. The main semiconductor region 3e of FIG. 13 includes a first semiconductor layer 4 ′ formed of the same material as the electron transit layer 4 of FIG. 4 and a second semiconductor layer 5 ′ doped with an n-type impurity (for example, Si). Consists of. For example, the second semiconductor layer 5 ′ is formed of the same material as the second electron supply layer 22 of FIG. 4 and is used as a current path between the source electrode 6 and the drain electrode 7. In order to obtain normally-off characteristics, a recess 15a is provided in the main semiconductor region 3e as in FIG. That is, the recess 15a is formed by removing a part of the second semiconductor layer 5 ', and the remaining portion 18' of the second semiconductor layer 5 'is between the recess 15a and the first semiconductor layer 4'. Has occurred. The depth of the recess 15a and the thickness of the remaining portion 18 'are determined so that electrons are discharged from the remaining portion 18' with the help of the p-type metal oxide semiconductor film 10 and the remaining portion 18 'is filled with the depletion layer. Yes.

The field effect semiconductor device of Example 9 of FIG. 13 operates in the same manner as a junction field effect transistor (FET), and the source electrode 6 and the gate electrode 8 with the potential of the drain electrode 7 higher than the potential of the source electrode 6. When a voltage equal to or higher than the threshold voltage is applied between the drain electrode 7 and the drain electrode 7, a drain current flows through the path of the drain electrode 7, the second semiconductor layer 5 ′, and the source electrode 6.

Example 9 of FIG. 13 has the following effects.
(1) With the help of the p-type metal oxide semiconductor film 10, normally-off characteristics can be obtained with certainty.
(2) Since the remaining portion 18 'under the gate electrode 8 of the second semiconductor layer 5' is relatively thick, the power loss here is small.
(3) The effect of the field plate 11 can be obtained in the same manner as the first and second embodiments shown in FIGS.

The field effect semiconductor device of Example 9 in FIG. 13 corresponds to the insulating film 30 in FIG. 9, or corresponds to the recesses 32 and 33 in FIG. 10, or the modified p-type metal oxide semiconductor in FIG. It is also possible to provide a diode forming conductor 50 ′ corresponding to the film 10 ′ or connecting the gate electrode 8 and the source electrode 6 as shown in FIG. 13.

FIG. 14 shows a part of a modified p-type metal oxide semiconductor film 10a of the heterojunction field effect semiconductor device according to the tenth embodiment. A p-type metal oxide semiconductor film 10a in FIG. 14 is a modification of the p-type metal oxide semiconductor film 10 in the first embodiment in FIG. 1, and includes a first layer 51 made of nickel oxide and a second layer made of iron oxide. And a third layer 53 made of cobalt oxide. One main surface (lower surface) 54 of the p-type metal oxide semiconductor film 10 a in FIG. 14 is a surface in contact with the electron supply layer 5, and the other main surface (upper surface) 55 is a surface in contact with the gate electrode 8. It is desirable that the hole concentration of the first layer 51 is the highest and the hole concentration of the third layer 53 is the lowest.
Thus, the p-type metal oxide semiconductor film 10a composed of a stack of a plurality of different p-type metal oxide semiconductor materials has the same effect as the p-type metal oxide semiconductor film 10 of Example 1 in FIG. Have
Note that the p-type metal oxide semiconductor film 10a can be used in place of the p-type metal oxide semiconductor film 10 or 10 ′ of the second to ninth embodiments other than the first embodiment.
Further, the material of the first to third layers 51 to 53 of the p-type metal oxide semiconductor film 10a is changed to another material selected from, for example, nickel oxide, iron oxide, cobalt oxide, manganese oxide, and copper oxide. Can do. In addition, for example, the third layer 53 can be omitted from the first to third layers 51 to 53 of the p-type metal oxide semiconductor film 10a, or another layer can be added.

FIG. 15 shows a part of a modified p-type metal oxide semiconductor film 10b of the heterojunction field effect semiconductor device according to the eleventh embodiment. A p-type metal oxide semiconductor film 10b of FIG. 15 is a modification of the p-type metal oxide semiconductor film 10 of Example 1 of FIG. 1, and the hole concentration changes from one main surface 54 to the other main surface 55. It consists of a laminate of first, second and third layers 51a, 52a, 53a which are successively lowered. One main surface (lower surface) 54 of the p-type metal oxide semiconductor film 10 b in FIG. 15 is a surface in contact with the electron supply layer 5, and the other main surface (upper surface) 55 is a surface in contact with the gate electrode 8. Accordingly, the first layer 51 a having the highest hole concentration is in contact with the electron supply layer 5.
The first, second, and third layers 51a, 52a, and 53a having different hole concentrations are formed, for example, by gradually reducing the amount of oxygen added when sputtering nickel oxide (NiO) with a magnetron sputtering apparatus. The
As described above, the p-type metal oxide semiconductor film 10b composed of the stacked body of the first, second, and third layers 51a, 52a, and 53a having different hole concentrations is the p-type metal of Example 1 in FIG. The effect is similar to that of the oxide semiconductor film 10. In addition, since the first layer 51a having the highest hole concentration is in contact with the electron supply layer 5, normally-off characteristics can be favorably obtained.
Note that the p-type metal oxide semiconductor film 10b can be used not only in the first embodiment, but also in place of the p-type metal oxide semiconductor film 10 or 10 ′ in the second to ninth embodiments.
Further, for example, the third layer 53a can be omitted from the first to third layers 51a to 53a of the p-type metal oxide semiconductor film 10b, or another layer can be added.
Further, instead of stepwise changing the hole concentration of the p-type metal oxide semiconductor film 10b, the hole concentration gradually decreases from one main surface (lower surface) 54 to the other main surface (upper surface) 55, that is, It can be reduced with a slope. In this way, in order to gradually reduce the hole concentration of the p-type metal oxide semiconductor film 10b, the amount of oxygen added is gradually decreased with the progress of film formation of, for example, nickel oxide (NiO) by magnetron sputtering.
In addition, in order to change the hole concentration in the thickness direction of the p-type metal oxide semiconductor film, conditions for heat treatment of the p-type metal oxide semiconductor film, ozone ashing conditions, or O 2 (oxygen) as the film formation proceeds The ashing process conditions can be changed.
Further, in order to change the hole concentration in the thickness direction of the p-type metal oxide semiconductor film, the doping amount of lithium (Li) can be changed with the progress of film formation.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The main semiconductor regions 3 to 3e are separated from InGaN other than GaN and AlGaN, AllnGaN, AlN, InAlN, AlP, GaP, AllnP, GalnP, AlGaP, AlGaAs, GaAs, AlAs, InAs, InP, InN, and GaAsP. 3-5 compound semiconductor, 2-6 compound semiconductor such as ZnO, or still another compound semiconductor.
(2) A well-known source field plate and drain field plate can be provided.
(3) Although one source electrode 6, one drain electrode 7, and one gate electrode 8 are shown in the drawings showing the respective embodiments, a plurality of them can be provided. That is, a plurality of minute FETs (unit FETs) can be provided on one chip, and these can be connected in parallel.
(4) Heterojunction field effect semiconductor in which the electron supply layers of Examples 1 to 8 and 12 are replaced with hole supply layers and a two-dimensional hole gas layer is formed as a two-dimensional carrier gas layer in a region corresponding to the 2DEG layer 12 A device can be configured. In this case, an n-type metal oxide semiconductor film is provided instead of the p-type metal oxide semiconductor films 10, 10 ′, 10a, 10b, and 10c. In FIG. 13, a p-type second semiconductor layer can be provided instead of the n-type second semiconductor layer 5 ', and an n-type metal oxide semiconductor film can be provided thereon.
(5) Lithium (Li) can be added instead of adding oxygen when obtaining the p-type metal oxide semiconductor films 10, 10 ′, 10a, 10b, and 10c.

(A) is sectional drawing which shows the heterojunction field effect semiconductor device of Example 1 of this invention, (B) is sectional drawing which expands and shows a part of gate electrode. FIG. 2 is an energy level diagram of the heterojunction field effect semiconductor device of Example 1 of FIG. 1 and two comparative examples. FIG. 2 is a diagram illustrating a relationship between a drain-source voltage Vds and a gate current (gate leakage current) Ig of the heterojunction field effect semiconductor device of Example 1 of FIG. 1 and two comparative examples. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 2 of this invention. FIG. 5 is a diagram showing the relationship between the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the gate-source voltage Vgs and the drain-source current Ids of three comparative examples. FIG. 5 is a diagram showing the relationship between the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the drain-source voltage Vds and the gate leakage current Ig of three comparative examples. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 3 of this invention. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 4 of this invention. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 5 of this invention. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 6 of this invention. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 7 of this invention. It is sectional drawing which shows the diode type heterojunction field effect semiconductor device of Example 8 of this invention. It is sectional drawing which shows the MESFET type field effect semiconductor device of Example 9 of this invention. It is sectional drawing which shows a part of p-type metal oxide semiconductor film according to Example 10 of this invention. It is sectional drawing which shows a part of p-type metal oxide semiconductor film according to Example 11 of this invention.

Explanation of symbols

1 substrate 2 buffer layer 3 main semiconductor region 4 electron transit layer (first semiconductor layer)
5 Electron supply layer (second semiconductor layer)
6 Source electrode 7 Drain electrode 8 Gate electrode 9 Insulating film 10 made of silicon oxide p-type metal oxide semiconductor film

Claims (21)

  1. One and the other main surfaces opposed to each other, a first semiconductor layer disposed between the one and the other main surfaces, and disposed between the first semiconductor layer and the one main surface; and A second semiconductor layer formed of a material heterojunctioned to the first semiconductor layer and capable of generating a two-dimensional carrier gas layer functioning as a current path in the first semiconductor layer based on the heterojunction; A main semiconductor region comprising:
    A first main electrode disposed on the one main surface of the main semiconductor region and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer;
    A second main electrode disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer When,
    The first main electrode and the second main electrode on the one main surface of the main semiconductor region to control a current path between the first main electrode and the second main electrode; A gate electrode disposed between,
    The first main electrode formed between the main semiconductor region and the gate electrode by sputtering in an atmosphere containing oxygen and having a conductivity type for reducing carriers in the two-dimensional carrier gas layer; A field effect semiconductor device comprising: a metal oxide semiconductor film disposed apart from the second main electrode.
  2. The main semiconductor region has a recess having a depth that does not reach the first semiconductor layer from the one main surface;
    The field effect semiconductor device according to claim 1, wherein the gate electrode is disposed on the concave portion via the metal oxide semiconductor film.
  3. The thickness of the remaining portion of the second semiconductor layer disposed between the recess and the first semiconductor layer is determined by the thickness of the recess in the first semiconductor layer before the metal oxide semiconductor film is provided. The two-dimensional carrier gas layer can be formed in a portion facing the recess in the first semiconductor layer after the two-dimensional carrier gas layer can be generated in the facing portion and the metal oxide semiconductor film is provided. The field effect semiconductor device according to claim 2, wherein the field effect semiconductor device is set so as to prevent the occurrence of the phenomenon.
  4. 4. The field effect semiconductor device according to claim 1, wherein the two-dimensional carrier gas layer is a two-dimensional electron gas layer, and the metal oxide semiconductor film is a p-type metal oxide semiconductor film.
  5. 5. The field effect semiconductor device according to claim 4, wherein the p-type metal oxide semiconductor film is made of at least one selected from nickel oxide, iron oxide, cobalt oxide, manganese oxide, and copper oxide.
  6. The p-type metal oxide semiconductor film is made of nickel oxide, and the gate electrode is made of a nickel layer formed on the p-type metal oxide semiconductor film and a gold layer formed on the nickel layer. The field effect semiconductor device according to claim 4.
  7. 5. The field effect semiconductor device according to claim 4, wherein the p-type metal oxide semiconductor film is formed of a stack of a plurality of p-type metal oxide semiconductor films made of different materials.
  8. 5. The field effect semiconductor device according to claim 4, wherein the p-type metal oxide semiconductor film has different hole concentrations gradually or stepwise in the thickness direction.
  9. The main semiconductor region further includes a third semiconductor layer disposed on the second semiconductor layer and having a higher carrier concentration than the second semiconductor layer,
    3. The field effect semiconductor device according to claim 2, wherein the recess is formed so as to delete at least a part of the third semiconductor layer.
  10. The first semiconductor layer is made of a nitride semiconductor, the second semiconductor layer is made of a nitride semiconductor containing Al, and the third semiconductor layer contains Al in a larger proportion than the second semiconductor layer. The field effect semiconductor device according to claim 9, comprising a nitride semiconductor.
  11. The main semiconductor region is further formed of a nitride semiconductor that is disposed on the third semiconductor layer and that includes Al at a lower rate (including zero) than the third semiconductor layer. Having a semiconductor layer,
    11. The field effect semiconductor device according to claim 10, wherein the concave portion is formed so as to remove at least a part of the fourth semiconductor layer and the third semiconductor layer.
  12. The main semiconductor region is further disposed on the third semiconductor layer, and a fourth semiconductor layer formed of a nitride semiconductor containing Al at a lower rate than the third semiconductor layer; A conductivity type opposite to that of the metal oxide semiconductor film formed on the fourth semiconductor layer and formed of a nitride semiconductor containing Al at a lower rate (including zero) than the fourth semiconductor layer is determined. A fifth semiconductor layer containing impurities
    10. The field effect semiconductor according to claim 9, wherein the recess is formed so as to remove at least a part of the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer. apparatus.
  13. The main semiconductor region is further disposed between the first semiconductor layer and the second semiconductor layer, is formed thinner than the second semiconductor layer, and is higher in proportion than the second semiconductor layer. 13. The field effect semiconductor device according to claim 1, further comprising a spacer layer made of a nitride semiconductor containing Al.
  14. Furthermore, it is disposed on at least a part between the gate electrode and the first main electrode and at least a part between the gate electrode and the second main electrode on one main surface of the main semiconductor region. 14. The field effect semiconductor device according to claim 1, further comprising an insulating film formed.
  15. Furthermore, it is disposed on at least a part between the gate electrode and the first main electrode and at least a part between the gate electrode and the second main electrode on one main surface of the main semiconductor region. And a gate field plate disposed on the insulating film, the gate field plate being disposed to face at least one main surface of the main semiconductor region via the insulating film and the gate The field effect semiconductor device according to claim 1, wherein the field effect semiconductor device is connected to an electrode.
  16. 16. The field effect semiconductor device according to claim 15, wherein an end of the insulating film on the gate electrode side is an inclined side surface, and the gate field plate covers at least the inclined side surface of the insulating film.
  17.   17. The field effect semiconductor according to claim 1, further comprising a conductor electrically connecting the gate electrode to the first main electrode for diode operation. apparatus.
  18. One and the other main surfaces facing each other, a first semiconductor layer disposed between the one and the other main surfaces, and the first semiconductor layer and the one main surface to form a current path A main semiconductor region comprising a second semiconductor layer disposed between and having a first conductivity type;
    A first main electrode disposed on the one main surface of the main semiconductor region and electrically coupled to the second semiconductor layer;
    A second main electrode disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode and electrically coupled to the second semiconductor layer;
    A gate electrode disposed between the first main electrode and the second main electrode on the one main surface of the main semiconductor region to control a current path of the second semiconductor layer;
    The first main electrode is disposed between the gate electrode and the main semiconductor region, has a second conductivity type opposite to the first conductivity type, and is formed by sputtering in an atmosphere containing oxygen. And a metal oxide semiconductor film disposed away from the second main electrode.
  19.   19. The field effect semiconductor device according to claim 18, wherein the second semiconductor layer has a recess, and the gate electrode is disposed on the recess via the metal oxide semiconductor film. .
  20.   20. The field effect semiconductor device according to claim 18, further comprising a conductor that electrically connects the gate electrode to the first main electrode.
  21. A main semiconductor region having at least one semiconductor layer for forming a current path, and an electric current connected to the semiconductor layer disposed on one main surface of the main semiconductor region and forming the current path Electrically coupled to the first main electrode and the semiconductor layer disposed on one main surface of the main semiconductor region spaced apart from the first main electrode and forming the current path Between the first main electrode and the second main electrode on one main surface of the main semiconductor region to control the current path of the semiconductor layer And a step of forming the gate electrode having a function of reducing carriers in the semiconductor layer, which is disposed between the main semiconductor region and the gate electrode, and which forms the current path. Formed before and before First a main electrode and the second method of fabricating a field effect semiconductor device and a metal oxide semiconductor film that is located away from the main electrode,
    A method of manufacturing a field effect semiconductor device, wherein the metal oxide semiconductor film is formed by sputtering in an atmosphere containing oxygen.
JP2008073603A 2007-08-29 2008-03-21 Field effect semiconductor device and manufacturing method thereof Active JP5487550B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007222273 2007-08-29
JP2007222273 2007-08-29
JP2008073603A JP5487550B2 (en) 2007-08-29 2008-03-21 Field effect semiconductor device and manufacturing method thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008073603A JP5487550B2 (en) 2007-08-29 2008-03-21 Field effect semiconductor device and manufacturing method thereof
US12/199,323 US7859021B2 (en) 2007-08-29 2008-08-27 Field-effect semiconductor device
US12/947,088 US7985987B2 (en) 2007-08-29 2010-11-16 Field-effect semiconductor device

Publications (3)

Publication Number Publication Date
JP2009076845A JP2009076845A (en) 2009-04-09
JP2009076845A5 JP2009076845A5 (en) 2009-10-01
JP5487550B2 true JP5487550B2 (en) 2014-05-07

Family

ID=40611498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008073603A Active JP5487550B2 (en) 2007-08-29 2008-03-21 Field effect semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5487550B2 (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5582378B2 (en) * 2009-02-27 2014-09-03 サンケン電気株式会社 Field effect semiconductor device and manufacturing method thereof
JP2010267865A (en) * 2009-05-15 2010-11-25 Toyota Central R&D Labs Inc Solar cell, and method of manufacturing the same
JP4786730B2 (en) * 2009-05-28 2011-10-05 シャープ株式会社 Field effect transistor and manufacturing method thereof
US8390000B2 (en) * 2009-08-28 2013-03-05 Transphorm Inc. Semiconductor devices with field plates
JP5625336B2 (en) * 2009-11-30 2014-11-19 サンケン電気株式会社 Semiconductor device
JP5716737B2 (en) 2010-03-01 2015-05-13 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP5056883B2 (en) 2010-03-26 2012-10-24 サンケン電気株式会社 Semiconductor device
US8896122B2 (en) 2010-05-12 2014-11-25 Cree, Inc. Semiconductor devices having gates including oxidized nickel
GB2482308A (en) 2010-07-28 2012-02-01 Univ Sheffield Super junction silicon devices
JP5672868B2 (en) 2010-08-31 2015-02-18 富士通株式会社 Compound semiconductor device and manufacturing method thereof
KR102065115B1 (en) * 2010-11-05 2020-01-13 삼성전자주식회사 High Electron Mobility Transistor having E-mode and method of manufacturing the same
JP5810518B2 (en) 2010-12-03 2015-11-11 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP5724347B2 (en) 2010-12-10 2015-05-27 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP5775321B2 (en) 2011-02-17 2015-09-09 トランスフォーム・ジャパン株式会社 Semiconductor device, manufacturing method thereof, and power supply device
JP5913816B2 (en) 2011-02-21 2016-04-27 富士通株式会社 Manufacturing method of semiconductor device
JP2012178376A (en) * 2011-02-25 2012-09-13 Sanken Electric Co Ltd Semiconductor device and manufacturing method thereof
JP5782947B2 (en) 2011-09-15 2015-09-24 富士通株式会社 Semiconductor device and manufacturing method thereof, power supply device, and high-frequency amplifier
JP5896667B2 (en) 2011-09-26 2016-03-30 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
JP6231730B2 (en) 2011-09-28 2017-11-15 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP2013089673A (en) 2011-10-14 2013-05-13 Toshiba Corp Semiconductor device and semiconductor device manufacturing method
KR101934851B1 (en) * 2011-12-07 2019-01-04 삼성전자주식회사 High electron mobility transistor
JP5932368B2 (en) * 2012-01-27 2016-06-08 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
KR101920715B1 (en) * 2012-03-06 2018-11-21 삼성전자주식회사 High Electron Mobility Transistor and method of manufacturing the same
JP5950643B2 (en) 2012-03-19 2016-07-13 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
JP5902010B2 (en) 2012-03-19 2016-04-13 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
WO2014020809A1 (en) * 2012-08-03 2014-02-06 パナソニック株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
JP6087552B2 (en) 2012-09-21 2017-03-01 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
JP6017248B2 (en) 2012-09-28 2016-10-26 トランスフォーム・ジャパン株式会社 Semiconductor device manufacturing method and semiconductor device
JP2014072426A (en) 2012-09-28 2014-04-21 Fujitsu Ltd Semiconductor device and semiconductor device manufacturing method
KR20140066015A (en) 2012-11-22 2014-05-30 삼성전자주식회사 Hetero junction field effect transistor and method for manufacturing the same
JP5949527B2 (en) 2012-12-21 2016-07-06 富士通株式会社 Semiconductor device and manufacturing method thereof, power supply device, and high-frequency amplifier
JP6565376B2 (en) 2014-10-29 2019-08-28 サンケン電気株式会社 Semiconductor device
JP6631950B2 (en) 2014-12-11 2020-01-15 パナソニックIpマネジメント株式会社 Nitride semiconductor device and method of manufacturing nitride semiconductor device
JP6631160B2 (en) * 2015-10-29 2020-01-15 富士通株式会社 Semiconductor device, power supply device, high frequency amplifier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170990A (en) * 2000-12-04 2002-06-14 Nippon Telegr & Teleph Corp <Ntt> Method for forming p type ohmic junction to nitride semiconductor
US8174048B2 (en) * 2004-01-23 2012-05-08 International Rectifier Corporation III-nitride current control device and method of manufacture
JP4705482B2 (en) * 2006-01-27 2011-06-22 パナソニック株式会社 Transistor

Also Published As

Publication number Publication date
JP2009076845A (en) 2009-04-09

Similar Documents

Publication Publication Date Title
US9941399B2 (en) Enhancement mode III-N HEMTs
US8900939B2 (en) Transistor with enhanced channel charge inducing material layer and threshold voltage control
US20200006497A1 (en) Nitride-based semiconductor device and method of manufacturing the same
JP6357037B2 (en) Always-off semiconductor device and manufacturing method thereof
TWI663698B (en) Semiconductor device
US9490324B2 (en) N-polar III-nitride transistors
US10014403B2 (en) Semiconductor device
US10686064B2 (en) Nitride semiconductor device and fabrication method therefor
US8963209B2 (en) Enhancement-mode HFET circuit arrangement having high power and a high threshold voltage
US8907349B2 (en) Semiconductor device and method of manufacturing the same
TWI487102B (en) Compound semiconductor device
JP5548909B2 (en) Nitride semiconductor device
JP5202312B2 (en) Group III nitride enhancement type devices
JP4968068B2 (en) Field effect transistor
US8164115B2 (en) Nitride semiconductor device
JP5292716B2 (en) Compound semiconductor device
US8441035B2 (en) Field effect transistor and method of manufacturing the same
US9837524B2 (en) Semiconductor device and method of manufacturing semiconductor device
US7973335B2 (en) Field-effect transistor having group III nitride electrode structure
US7777253B2 (en) Field-effect semiconductor device
JP5065616B2 (en) Nitride semiconductor device
CN102365763B (en) Dopant diffusion modulation in GaN buffer layers
US8519441B2 (en) High speed high power nitride semiconductor device
US7800116B2 (en) Group III-nitride semiconductor device with a cap layer
US9768257B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090817

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130426

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130514

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130711

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130919

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131112

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140210

R150 Certificate of patent or registration of utility model

Ref document number: 5487550

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250