JP2010153748A - Method of manufacturing field effect semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off field effect semiconductor device having small on resistance and gate leakage current, and to provide a method of manufacturing the normally-off field-effect semiconductor device. <P>SOLUTION: By the method, the field effect semiconductor device is manufactured. The field effect semiconductor device includes: a main semiconductor region, including at least one semiconductor layer for forming a current passage; a first main electrode 6 disposed on one main surface of the main semiconductor region; a second main electrode 7 disposed on one main surface of the main semiconductor region, separately from the first main electrode 6; a gate electrode 8 disposed between the first and second main electrodes on one main surface of the main semiconductor region; and a metal oxide semiconductor film 10, disposed between the main semiconductor region and the gate electrode 8. In this case, a thin film containing a metal material for composing the metal oxide semiconductor film 10 is evaporated onto the main semiconductor region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a field effect such as a high electron mobility transistor (HEMT), a diode having a two-dimensional electron carrier gas layer as a current path, a metal semiconductor field effect transistor (MESFET), or the like. The present invention relates to a semiconductor device and a manufacturing method thereof.

A conventional HEMT, which is a kind of field effect transistor, has an electron transit layer made of a nitride semiconductor such as undoped GaN formed on a substrate such as silicon or sapphire via a buffer layer, and is doped with an n-type impurity. Or it has the electron supply layer or barrier layer which consists of nitride semiconductors, such as undoped AlGaN, and the source electrode, drain electrode, and gate electrode (Schottky electrode) which were formed on the electron supply layer. The band gap of the electron supply layer made of AlGaN or the like is larger than the band gap of the electron transit layer made of GaN or the like, and the lattice constant of the electron supply layer made of AlGaN or the like is smaller than the lattice constant of the electron transit layer made of GaN or the like. . When an electron supply layer having a smaller lattice constant than this is disposed on the electron transit layer, an extensible strain, that is, a tensile stress, is generated in the electron supply layer, resulting in piezoelectric polarization. Since the electron supply layer also spontaneously polarizes, a well-known two-dimensional electron gas layer, that is, a 2DEG layer is formed in the vicinity of the heterojunction surface between the electron transit layer and the electron supply layer by the action of an electric field based on piezo polarization and spontaneous polarization. As is well known, the 2DEG layer functions as a current path (channel) between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

By the way, a HEMT having a general configuration has a characteristic that a current flows between a source electrode and a drain electrode in a state where a gate control voltage is not applied to the gate electrode (normally state), that is, a normally-on characteristic. In order to keep the normally-on HEMT in an off state, a negative power source for setting the gate electrode to a negative potential is required, and the electric circuit is necessarily expensive. Therefore, the ease of use of a conventional normally-on HEMT is not good.

Therefore, development of a heterojunction field effect semiconductor device having normally-off characteristics is underway. As a typical method for obtaining normally-off characteristics,
(1) A method of forming a recess (concave portion) in the electron supply layer and forming a gate electrode on the electron supply layer thinned by the recess,
(2) As disclosed in Japanese Patent Application Laid-Open No. 2004-273486 (Patent Document 1), there is a method of disposing a p-type semiconductor layer made of a p-type nitride semiconductor between a gate electrode and an electron supply layer. Are known.

When the electron supply layer is partially thinned by the recess according to the method of (1) above, the electric field based on piezoelectric polarization and spontaneous polarization in the thinned portion of the electron supply layer is weakened. Therefore, the electric field based on the piezo polarization and spontaneous polarization of the electron supply layer weakened due to the recess is a built-in potential between the gate electrode and the electron supply layer, that is, the bias voltage of the gate electrode. Is canceled by the potential difference between the gate electrode and the electron supply layer in a state where the zero is zero, and the 2DEG layer disappears from the portion of the electron transit layer facing the gate electrode. As a result, the drain-source is turned off in a state where no gate control voltage is applied to the gate electrode, and a normally-off characteristic is obtained.

When the p-type semiconductor layer is disposed under the gate electrode according to the method of (2) above, the p-type semiconductor layer raises the potential of the electron transit layer immediately below the gate electrode to deplete the electrons in the 2DEG layer, The 2DEG layer disappears and normally-off characteristics are obtained.

JP 2004-273486 A

However, when the above method is used, there are the following problems.
The threshold value of the HEMT according to the method (1) is relatively small, for example, +1 V or less, and it is easy to malfunction due to noise, and when a positive gate control voltage is applied to the gate electrode composed of a Schottky electrode, The problem that a relatively large leak current flows, the problem that the threshold voltage changes greatly due to variations in the depth of the recess, and the thin part of the electron supply layer (barrier layer) under the gate electrode are in the ON state. Even when a control voltage for switching to the conductive state is applied to the gate electrode, the electron concentration in the electron transit layer facing the gate electrode is sufficiently high because the ability to supply electrons to the electron transit layer is low. The 2DEG layer cannot be formed, and the on-resistance between the drain electrode and the source electrode becomes relatively high.
The method (2) has a problem that it is difficult to easily obtain a p-type semiconductor layer made of a p-type nitride semiconductor having a high hole concentration, and a p-type semiconductor layer having a high hole concentration is obtained. When this is not possible, it is required to make the electron supply layer thin or to reduce the Al ratio of the electron supply layer made of AlGaN or AlInGaN. As a result, the electron concentration of the 2DEG layer decreases, and the source electrode ON resistance between the drain electrode and the drain electrode increases.

The same problem as the above-described HEMT also exists in a diode using a 2DEG layer, a field effect semiconductor device (for example, MESFET) other than the HEMT, and the like.

Accordingly, the problem to be solved by the present invention is that a normally-off type field effect semiconductor device with small on-resistance and gate leakage current is required, and the present invention can meet the above-mentioned requirements. And a method of manufacturing the same.

In order to solve the above problems, the inventors of the present invention have developed a field effect semiconductor device in which a p-type metal oxide semiconductor film is disposed between a gate electrode and an electron supply layer and a method for manufacturing the same (Japanese Patent Application). 2008-73603). The present invention has been made based on this discovery.

According to a first aspect of the present invention, there is provided a method of manufacturing a field effect semiconductor device, comprising: a main semiconductor region having at least one semiconductor layer for forming a current path; and a main semiconductor region disposed on one main surface of the main semiconductor region. And a first main electrode electrically coupled to the semiconductor layer for forming the current path, and disposed on one main surface of the main semiconductor region, spaced apart from the first main electrode. And a second main electrode electrically coupled to the semiconductor layer for forming the current path, and the first main surface of the main semiconductor region for controlling the current path of the semiconductor layer. A gate electrode disposed between the first main electrode and the second main electrode; and a semiconductor layer disposed between the main semiconductor region and the gate electrode and forming the current path. Has the function to reduce the carrier A method of manufacturing a field effect semiconductor device comprising a metal oxide semiconductor film comprising: depositing a thin film containing a metal material constituting the metal oxide semiconductor film on the main semiconductor region. And

According to a second aspect of the present invention, there is provided a method of manufacturing a field effect semiconductor device, wherein oxygen is ion-implanted into the thin film in order to enhance a function of reducing the carriers.

According to the invention according to each claim of the present invention, a normally-off type field effect semiconductor device with small on-resistance and gate leakage current can be provided.

Next, a heterojunction field effect semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
A heterojunction field effect semiconductor device according to Embodiment 1 of the present invention shown in FIG. 1A includes a substrate 1 made of a single crystal silicon semiconductor and a buffer layer 2 on one main surface 1a of the substrate 1. A main semiconductor region 3 including an electron transit layer 4 as a first semiconductor layer and an electron supply layer 5 as a second semiconductor layer, which are sequentially disposed, and a first semiconductor layer 3 disposed on the main semiconductor region 3. A source electrode 6 as a main electrode, a drain electrode 7 and a gate electrode 8 as a second main electrode, an insulating film 9 made of silicon oxide disposed on the main semiconductor region 3, and a p-type according to the present invention A metal oxide semiconductor film 10 and a gate field plate 11 are provided. Although this heterojunction field effect semiconductor device has an insulated gate structure different from that of a typical HEMT, it operates on the same principle as that of a typical HEMT, and can also be called a HEMT or a HEMT type semiconductor device. Hereinafter, each part of FIG. 1 will be described in detail.

The substrate 1 has one main surface 1a and the other main surface 1b opposite thereto, and functions as a growth substrate for epitaxially growing semiconductor materials for the buffer layer 2 and the main semiconductor region 3, and It functions as a support substrate for supporting these mechanically. In this embodiment, the substrate 1 is made of silicon in order to reduce costs. However, the substrate 1 may be formed of a semiconductor such as silicon carbide (SiC) other than silicon, or an insulator such as sapphire or ceramic.

The buffer layer 2 on one main surface 1a of the substrate 1 is formed by an epitaxial growth method such as a well-known MOCVD method. In FIG. 1, the buffer layer 2 is shown as a single layer for the sake of simplicity, but actually, it is formed of a plurality of layers. In other words, the buffer layer 2 has alternating first sublayers (first sublayer) made of AlN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride). Is a multi-layered buffer laminated on the substrate. Since the buffer layer 2 is not directly related to the operation of the HEMT, it can be omitted. Further, the semiconductor material of the buffer layer 2 can be replaced with a nitride semiconductor other than AlN or GaN or a Group 3-5 compound semiconductor, or a buffer layer having a single layer structure can be formed.

The main semiconductor region 3 has one main surface 13 and the other main surface 14 facing each other, and the electron transit layer 4 as the first semiconductor layer is disposed on the one main surface 13 side, and the second semiconductor The electron supply layer 5 as a layer is disposed between the electron transit layer 4 and the other main surface 14. The electron transit layer 4 is made of a first nitride semiconductor and has a thickness of 0.3 to 10 μm. The electron transit layer 4 has a two-dimensional electron gas layer (2DEG layer) 12 (indicated by a dotted line) as a two-dimensional carrier gas layer that functions as a current path (channel) in the vicinity of the heterojunction surface with the electron supply layer 5 above. It is made of undoped GaN (gallium nitride) epitaxially grown by a known MOCVD method. Note that the electron supply layer 5 is made of, for example, AlaInbGa1-a-bN other than GaN,
Here, a is a numerical value satisfying 0 ≦ a <1, b is 0 ≦ b <1,
It can also be formed of a nitride semiconductor such as, or another compound semiconductor.

The electron supply layer 5 formed on the electron transit layer 4 is preferably 10 by a second nitride semiconductor having a band gap larger than that of the electron transit layer 4 and having a lattice constant smaller than that of the electron transit layer 4. It is formed to a thickness of ˜50 nm (for example, 25 nm). The electron supply layer 5 of this embodiment is made of undoped Al0.3Ga0.7N epitaxially grown by a known MOCVD method. Note that the electron supply layer 5 may be formed of a nitride semiconductor other than Al0.3Ga0.7N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0 <x <1, y is 0 ≦ y <1, a preferable value of x is 0.1 to 0.4, and a more preferable value is 0.3.

Instead of forming the electron supply layer 5 with undoped AlxInyGa1-x-yN, a nitride semiconductor made of AlxInyGa1-x-yN doped with an n-type (first conductivity type) impurity, or nitrided with another composition It can also be formed of a physical semiconductor or another compound semiconductor.

A source electrode 6 and a drain electrode 7 are disposed on one main surface 13 of the main semiconductor region 3, and a recess 15 is provided. The recess 15 is formed by dry etching between the source electrode 6 and the drain electrode 7 on one main surface 13 of the main semiconductor region 3, and has a bottom surface 16 and a pair of side surfaces 17, and the electron supply layer 5. It is formed shallower than the thickness. Therefore, there is a thin remaining portion 18 of the electron supply layer 5 between the bottom surface 16 of the recess 15 and the electron transit layer 4. The remaining portion 18 of the electron supply layer 5 has a thickness of 0 to 20 nm, more preferably 2 to 15 nm, most preferably 3 to 8 nm, and 5 nm in FIG.

If normally-off characteristics can be obtained without providing the recess 15, the recess 15 can be omitted and the p-type metal oxide semiconductor film 10 can be disposed on the flat main surface of the electron supply layer 5. Further, the side surface 17 of the recess 15 can be an inclined surface.

The insulating film 9 made of silicon oxide is disposed in a portion other than the portion where the source electrode 6, the drain electrode 7, and the recess 15 are formed on one main surface 13 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Has been. More specifically, the insulating film 9 made of silicon oxide is made of SiOx (where x is a numerical value of 1 to 2 and preferably 2), preferably plasma CVD (chemical vapor deposition method). ), Preferably having a thickness of 300 to 700 nm (for example, 500 nm) and generating compressive stress, that is, compressive strain (for example, 4.00 × 10 9 dyn / cm 2), and the carrier of the two-dimensional carrier gas layer 12 Contributes to increasing the concentration. That is, since the electron supply layer 5 made of AlGaN is disposed under the insulating film 9 made of silicon oxide, this reaction occurs when the compressive stress of the insulating film 9 made of silicon oxide acts on the electron supply layer 5. As a result, extensible strain, that is, tensile stress is generated in the electron supply layer 5, the piezo polarization of the electron supply layer 5 is strengthened, and the electron concentration in the two-dimensional electron gas layer (2DEG layer) 12 increases. This increase in the electron concentration contributes to a reduction in resistance between the source electrode 6 and the drain electrode 7 when the heterojunction field effect semiconductor device is on. The insulating film 9 made of silicon oxide is not disposed in the recess 15 and has an opening corresponding to the recess 15. The wall surface of the opening of the insulating film 9 made of silicon oxide, that is, the side surface 19 adjacent to the entrance of the recess 15 has an inclination of 5 to 60 degrees.

The insulating film 9 made of silicon oxide can be formed by another method such as sputtering. However, plasma CVD is most excellent for reducing crystal damage on one main surface 13 of the main semiconductor region 3, reducing surface states (traps), and suppressing current collapse. The insulating film 9 can also be formed of another insulating material (for example, silicon nitride) other than silicon oxide.

The p-type metal oxide semiconductor film 10 according to the present invention is disposed so as to cover the bottom surface 16 and the side surface 17 of the recess 15 and part of the insulating film 9 made of silicon oxide, and has a higher resistivity than the electron supply layer 5. The metal oxide semiconductor material has a thickness of preferably 3 to 1000 nm, more preferably 10 to 500 nm. When the p-type metal oxide semiconductor film 10 is thinner than 3 nm, the normally-off characteristic cannot be obtained satisfactorily, and when it is thicker than 1000 nm, the turn-on characteristic by the control of the gate electrode 8 is deteriorated.

Note that the p-type metal oxide semiconductor film 10 may be limited to the recess 15 so as not to extend on the insulating film 9.

The p-type metal oxide semiconductor film 10 of this embodiment is made of nickel oxide (NiOx, where x is an arbitrary numerical value, for example, 1) formed by magnetron sputtering and having a thickness of 200 nm. When the p-type metal oxide semiconductor film 10 is formed, the main semiconductor region 3 is provided on one main surface 1a of the substrate 1 via the buffer layer 2, and the insulating film 9 made of silicon oxide is further provided. A p-type metal oxide semiconductor film is placed in a magnetron sputtering apparatus, the inside of the magnetron sputtering apparatus is an atmosphere containing oxygen (preferably a mixed gas of argon and oxygen), and nickel oxide (NiO) is sputtered. Get 10. When nickel oxide is sputtered in an atmosphere containing oxygen, the p-type metal oxide semiconductor film 10 having a high hole concentration can be easily obtained.

In this embodiment, the p-type metal oxide semiconductor film 10 is patterned simultaneously with the patterning of the gate field plate 11 and the gate electrode 8, but the p-type metal oxide semiconductor film 10 is patterned in an independent process. You can also.

A p-type metal oxide semiconductor film 10 formed by sputtering nickel oxide in an oxygen-containing atmosphere has a higher hole concentration than GaN doped with a conventional p-type impurity and is relatively large. Has resistivity. Therefore, the p-type metal oxide semiconductor film 10 raises the potential under the gate electrode 8 relatively high to prevent the two-dimensional electron gas layer from being formed in the portion of the electron transit layer 4 below the gate electrode 8. To do. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained. The p-type metal oxide semiconductor film 10 contributes to a reduction in gate leakage current (leakage current) during HEMT operation.

Instead of forming the p-type metal oxide semiconductor film 10 with nickel oxide, iron oxide (FeOx, where x is an arbitrary numerical value, for example, 2), cobalt oxide (CoOx, where x is arbitrary) For example, 2), manganese oxide (MnOx, where x is an arbitrary numerical value, for example, 1), and copper oxide (CuOx, where x is an arbitrary numerical value) For example, it can be formed by at least one selected from 1. The p-type metal oxide semiconductor film made of a metal oxide other than nickel oxide is also preferably formed by sputtering a metal material in an atmosphere containing oxygen.

The p-type metal oxide semiconductor film 10 may be formed by forming a metal film by sputtering or the like and then oxidizing the metal film instead of forming the metal material by sputtering in an atmosphere containing oxygen. it can.

Further, the p-type metal oxide semiconductor film 10 can be formed by reactive sputtering in addition to the magnetron sputtering, and a physical vapor deposition method such as a well-known molecular beam epitaxy (MBE) method or a pulsed laser deposition (PLD) method, Alternatively, it can be grown by a chemical vapor deposition method such as a well-known MOCVD method.

For example, if the magnetron sputtering method is used, the p-type metal oxide semiconductor film 10 can be formed at a high deposition rate. Further, when the p-type metal oxide semiconductor film 10 is formed using a metal oxide as a target, the film composition can be made uniform by using a physical vapor deposition method such as reactive sputtering, ECR sputtering, or laser fractionation. . In addition, when the MBE method or the PLD method is used, the film formation rate becomes slow, while the film thickness can be made uniform in addition to the film composition. Further, if the MOCVD method is used, the p-type metal oxide semiconductor film 10 can be formed at a high deposition rate, and the film thickness can be made uniform even on an uneven surface such as a recess of the electron supply layer 5. be able to. As described above, the p-type metal oxide semiconductor film 10 in the present invention can be formed by using any physical or chemical vapor deposition method.

Further, in order to enhance the p-type characteristics of the p-type metal oxide semiconductor film 10, the p-type metal oxide semiconductor film 10 is subjected to heat treatment, ozone ashing treatment, or O2 (oxygen). It can be activated by performing ashing treatment or by ion-implanting O 2 into the p-type metal oxide semiconductor film 10.

For the source electrode 6 and the drain electrode 7, for example, titanium (Ti) is vapor-deposited to a desired thickness (for example, 25 nm) on one main surface 13 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Each of them is formed by vapor-depositing (Al) to a desired thickness (for example, 300 nm) and then forming a desired pattern by a photolithographic technique. The source electrode 6 and the drain electrode 7 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but are formed of a metal capable of low resistance contact (ohmic contact) other than this. You can also Since the electron supply layer 5 in the main semiconductor region 3 is extremely thin, the resistance in the thickness direction is negligibly small. Accordingly, the source electrode 6 and the drain electrode 7 are electrically coupled to the 2DEG layer 12 as a current path.

The gate electrode 8 is made of a metal layer deposited on the p-type metal oxide semiconductor film 10 and faces the bottom surface 16 of the recess 15 with the p-type metal oxide semiconductor film 10 interposed therebetween. The gate electrode 8 of this embodiment is a nickel (Ni) layer 81 having a thickness of 30 nm formed by vapor deposition on a p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx) as shown in FIG. And a gold (Au) layer 82 having a thickness of 300 nm formed on the nickel layer 81 by vapor deposition. Depending on the combination of the p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx), the nickel (Ni) layer 81, and the gold (Au) layer 82, the gate leakage current can be satisfactorily reduced. However, the gate electrode 8 can be formed of a multilayer film of a nickel (Ni) layer, a gold (Au) layer, and a titanium layer, an aluminum layer, a conductive polysilicon layer, or the like.

The gate field plate 11 is electrically connected to the gate electrode 8 and is formed continuously with the gate electrode 8. An insulating film 9 made of silicon oxide and a p-type metal oxide semiconductor film 10 are formed on the surface of the electron supply layer 5. Are facing each other. Since the insulating film 9 made of silicon oxide has inclined side surfaces 19 of 5 to 60 degrees, the distance between the gate field plate 11 and the electron supply layer 5 gradually increases as the distance from the gate electrode 8 on the bottom surface 16 of the recess 15 increases. is doing. Thereby, the relaxation of the electric field concentration at the end of the gate electrode 8 can be achieved satisfactorily.

In the heterojunction field effect semiconductor device of FIG. 1, when the gate control voltage is not applied to the gate electrode 8 (when the gate voltage is zero), even if the potential of the drain electrode 7 is higher than the potential of the source electrode 6. Even if it is higher, the recess 15 is provided corresponding to the gate electrode 8, the electron supply layer 5 is thinned under the gate electrode 8, and the p-type metal oxide semiconductor film 10 is formed between the gate electrode 8 and the electron supply layer 5. 2DEG layer is not formed in the electron transit layer 4 below the gate electrode 8, the 2DEG layer 12 is divided, and the source electrode 6 and the drain electrode 7 are turned off. .

2A is an energy level diagram of a recess of the heterojunction field-effect semiconductor device of FIG. 1, and FIG. 2B is an energy level of a conventional Schottky gate structure HEMT (hereinafter referred to as Comparative Example 1). FIG. 2C is a HEMT having a conventional Schottky gate structure in which an electron supply layer immediately below the gate electrode is thinly processed, that is, a HEMT having a structure in which the p-type metal oxide semiconductor film 10 is removed from FIG. 2) is shown. In these figures, EF represents the Fermi level, and EC represents the boundary level between the conduction band and the forbidden band. Ni represents the gate electrode 8, NiO represents the p-type metal oxide semiconductor film 10, AlGaN represents the electron supply layer 5, and GaN represents the electron transit layer 4.

In the heterojunction field effect semiconductor device of FIG. 1, since the electron supply layer 5 under the gate electrode 8 is as thin as 5 nm or less, the lattice is formed in the electron supply layer 5 under the gate electrode 8 as in FIG. Relaxation occurs, the charge due to piezo polarization is reduced, and the bulk characteristics are diminished and the charge due to spontaneous polarization is also reduced. The reduction of these charges in the electron supply layer 5 causes a decrease in Fermi level, and the potential under the gate electrode 8 is relatively increased. Further, since the p-type metal oxide semiconductor film 10 is provided, the potential under the gate electrode 8 is raised as shown in FIG. As a result, a two-dimensional carrier gas layer is not formed in the portion of the electron transit layer 4 facing the gate electrode 8, and a heterojunction field effect semiconductor device having normally-off characteristics is obtained. In other words, at the normal time, the polarization of the remaining portion 18 under the recess 15 of the electron supply layer 5 is canceled by the p-type metal oxide semiconductor film 10 and faces the gate electrode 8 of the electron transit layer 4. A two-dimensional carrier gas layer is not formed on the part to be formed.

When a positive gate control voltage higher than a predetermined threshold voltage is applied between the gate electrode 8 and the source electrode 6 in a state where the potential of the drain electrode 7 is higher than the potential of the source electrode 6, the gate of the electron transit layer 4 A channel (current passage) is formed in a portion facing the electrode 8. That is, when a positive gate control voltage is applied to the gate electrode 8, polarization occurs in the p-type metal oxide semiconductor film 10, holes collect on the electron supply layer 5 side of the p-type metal oxide semiconductor film 10, Electrons are induced on the side of the electron transit layer 4 in contact with the electron supply layer 5 to form a channel. As a result, the source electrode 6 and the drain electrode 7 are turned on, and electrons are supplied to the source electrode 6, the electron supply layer 5, the 2DEG layer 12, the channel, the 2DEG layer 12, the electron supply layer 5, and the drain electrode 7. It flows along the route. As is well known, since the electron supply layer 5 is extremely thin, electrons pass through this thickness direction by the tunnel effect.

The characteristic line A in FIG. 3 shows the relationship between the drain-source voltage Vds and the gate leakage current (leakage current) Ig of the heterojunction field effect semiconductor device of Example 1 in FIG. 1, and the characteristic line B is a comparative example. 1 shows the relationship between the drain-source voltage Vds and the gate leakage current Ig, and the characteristic line C shows the relationship between the drain-source voltage Vds and the gate leakage current Ig of Comparative Example 2. The gate leakage current Ig on the characteristic lines A, B, and C indicates the gate-drain current when the gate-source voltage Vgs is kept at zero.

As is clear from the comparison of the characteristic lines A, B, and C in FIG. 3, the gate leakage current Ig of the heterojunction field effect semiconductor device of Example 1 is significantly smaller than the gate leakage current Ig of Comparative Examples 1 and 2. .

The heterojunction field effect semiconductor device of Example 1 of FIG. 1 has the following effects.
(1) The p-type metal oxide semiconductor film 10 formed by sputtering (magnetron sputtering or reactive sputtering) in an atmosphere containing oxygen has a higher hole concentration than GaN to which a conventional p-type impurity is added. The p-type metal oxide semiconductor film 10 having a high hole concentration pulls up the potential under the gate electrode 8 well, and a two-dimensional electron gas layer is formed in the electron transit layer 4 under the gate electrode 8 during normal operation. Is well suppressed. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained.
(2) The p-type metal oxide semiconductor film 10 has a relatively high resistivity (insulating property) and is formed relatively thick (for example, 10 to 500 nm). Therefore, the gate leakage current during the operation of the heterojunction field effect semiconductor device is reduced, the breakdown voltage of the heterojunction field effect semiconductor device is improved, and the reliability is improved. Note that the threshold voltage does not shift to the negative side even if the p-type metal oxide semiconductor film 10 is formed relatively thick. In particular, when the p-type metal oxide semiconductor film 10 is made of nickel oxide (NiOx) and the gate electrode 8 is made of a nickel (Ni) layer 81 and a gold (Au) layer 82 as shown in FIG. A good effect of reducing the gate leakage current can be obtained.
(3) Since the p-type metal oxide semiconductor film 10 is made of a chemically stable substance and can be formed in an atmosphere containing oxygen, it is easy to manufacture.
(4) The normally-off characteristic is not only obtained by reducing the thickness of the remaining portion 18 below the recess (recess) 15 of the electron supply layer 5 but also between the recess (recess) 15 and the p-type metal oxide semiconductor film 10. Get in combination. Therefore, the thickness of the remaining portion 18 under the recess 15 of the electron supply layer 5 can be made relatively thick as 3 to 8 nm. As a result, when a control voltage for turning on the heterojunction field effect semiconductor device is applied to the gate electrode 8, the electron concentration in the portion of the electron transit layer 4 facing the gate electrode 8 can be made relatively high. The on-resistance can be made relatively low, and the maximum allowable current Imax of the heterojunction field effect semiconductor device can be increased.
(5) The portions of the electron supply layer 5 between the source electrode 6 and the gate electrode 8 and between the drain electrode 7 and the gate electrode 8 are formed relatively thick so as to be 10 nm or more, and Al in the electron supply layer 5 is formed. The ratio of (aluminum) is relatively large, for example 0.1 or more. For this reason, although the heterojunction field effect semiconductor device has normally-off characteristics, the electron concentration of the 2DEG layer 12 is relatively large and the on-resistance is relatively low. As a result, the maximum allowable current Imax of the heterojunction field effect semiconductor device can be increased.
(6) The insulating film 9 made of silicon oxide formed on one main surface 13 of the main semiconductor region 3 has a property of generating compressive stress (for example, 4.00 × 10 9 dyn / cm 2). When the compressive stress of the insulating film 9 made of silicon oxide acts on one main surface 13 of the main semiconductor region 3, that is, the main surface of the electron supply layer 5, electrons in the 2DEG layer 12 based on the piezoelectric polarization of the electron supply layer 5 are transferred. Become more. As a result, the on-resistance of the heterojunction field effect semiconductor device is lower than that of a conventional heterojunction field effect semiconductor device in which a silicon nitride film is formed on one main surface 13 of the main semiconductor region 3. Further, the gate leakage current is reduced by the insulating film 9 made of silicon oxide.
(7) Since the gate field plate 11 is provided, and the inclined side surface 19 of 5 to 60 degrees is provided in the insulating film 9 made of silicon oxide, the electric field concentration at the end of the gate electrode 8 is satisfactorily reduced. And a high breakdown voltage can be achieved.
(8) Since the gate field plate 11 is provided, the electrons trapped in the surface level of the main semiconductor region 3 when the reverse voltage is applied between the drain and the source via the gate field plate 11. 8 can be pulled out, and current collapse can be reduced.
(9) By forming the p-type metal oxide semiconductor film 10 by magnetron sputtering in an atmosphere containing oxygen, the p-type metal oxide semiconductor film 10 having a relatively large thickness and a relatively high hole concentration can be easily obtained. be able to.
(10) By forming the p-type metal oxide semiconductor film 10 by reactive sputtering, the p-type metal oxide semiconductor film 10 having a uniform film quality can be easily obtained.
(11) The p-type metal oxide semiconductor film 10 is subjected to a heat treatment, an ozone ashing process, an O2 (oxygen) ashing process, or the p-type metal oxide semiconductor film 10 By ion-implanting and activating O2, the p-type characteristics (hole concentration) of the p-type metal oxide semiconductor film 10 can be easily enhanced. Therefore, the effect that the p-type metal oxide semiconductor film 10 raises the potential below the gate electrode 8 becomes strong, and a field effect semiconductor device having a relatively large threshold voltage can be obtained.

(Second embodiment)
Next, a heterojunction field effect semiconductor device according to the second embodiment shown in FIG. 4 will be described. 4 that are substantially the same as those in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted.

The heterojunction field effect semiconductor device of Example 2 of FIG. 4 is formed substantially the same as FIG. 1 except that it has a modified main semiconductor region 3a. The deformed main semiconductor region 3a includes the electron transit layer 4 as the first semiconductor layer and the first, second, and second semiconductor layers as the first, second, third, and fourth semiconductor layers formed in the same manner as FIG. 3 electron supply layers 21, 22, and 23. That is, the main semiconductor region 3a in FIG. 4 includes first, second, and third electron supply layers 21, 22, and 23 that are sequentially stacked instead of the one electron supply layer 5 in FIG. Also, the main semiconductor region 3a in FIG. 4 has a recess 15c corresponding to the recess 15 in FIG. The recess 15a in FIG. 4 is formed in the same manner as the recess 15 in FIG. 1 except that the recess 15a has an inclined side wall 17a.

The first electron supply layer 21 heterojunction with the electron transit layer 4 has a band gap larger than that of the electron transit layer 4 and a lattice constant smaller than that of the electron transit layer 4 and is made of Al (aluminum). Preferably it consists of a nitride semiconductor contained in a proportion of 0.1 to 0.3, and preferably has a thickness of 5 nm to 10 nm. The first electron supply layer 21 of Example 2 is made of undoped Al0.26Ga0.74N epitaxially grown by a known MOCVD method and has a thickness of 7 nm. Therefore, the proportion of Al in the first electron supply layer 21 is smaller than the proportion of Al in the electron supply layer 5 of FIG. 1, and the thickness is thinner than that of the electron supply layer 5 in FIG. The first electron supply layer 21 having a smaller Al ratio than the electron supply layer 5 in FIG. 1 functions to make the threshold voltage of the heterojunction field effect semiconductor device more positive, and the depth of the recess 15a. It has a function of reducing the variation in threshold voltage due to the variation in thickness.

Note that the first electron supply layer 21 may be formed of a nitride semiconductor other than Al0.26Ga0.74N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0.1 <x <0.3 and y is 0 ≦ y <1.

The second electron supply layer 22 disposed on the first electron supply layer 21 has a band gap larger than that of the electron transit layer 4 and a lattice constant smaller than that of the electron transit layer 4, and the first electron supply layer 22. It is made of an n-type nitride semiconductor containing Al (aluminum) at a ratio larger than that of the electron supply layer 21 and has a thickness of 5 nm. The thickness of the second electron supply layer 22 is desirably in the range of 3 nm to 25 nm. The second electron supply layer 22 of this embodiment is made of Al0.34Ga0.66N epitaxially grown by a known MOCVD method and contains Si as an n-type impurity. Therefore, the proportion of Al in the second electron supply layer 22 is larger than the proportion of Al in the first electron supply layer 21, and the electron concentration in the second electron supply layer 22 is the electron concentration in the first electron supply layer 21. Higher than. The second electron supply layer 22 contributes to increasing the electron concentration in the 2DEG layer 12 of the electron transit layer 4. However, since the recess 15 under the gate electrode 8 is formed so as to penetrate the second electron supply layer 22, the second electron supply layer 22 does not deteriorate normally-off characteristics.

Note that the second electron supply layer 22 may be formed of a nitride semiconductor other than Al0.34Ga0.66N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0.2 <x <0.5, and y is 0 ≦ y <1.

The third electron supply layer 23 disposed on the second electron supply layer 22 has a band gap larger than that of the electron transit layer 4 and has a lattice constant smaller than that of the electron transit layer 4 and the second. It is made of an undoped nitride semiconductor containing Al (aluminum) at a proportion smaller than that of the electron supply layer 22 and has a thickness of 13 nm. The thickness of the third electron supply layer 23 is desirably in the range of 10 nm to 150 nm. The third electron supply layer 23 of this embodiment is made of undoped Al0.30Ga0.70N epitaxially grown by a known MOCVD method. Therefore, the proportion of Al in the third electron supply layer 23 is smaller than the proportion of Al in the second electron supply layer 22. The third electron supply layer 23 made of a nitride semiconductor that is undoped and has a lower Al ratio than the second electron supply layer 22 contributes to control of the surface charge of the main semiconductor region 3a. Note that the third electron supply layer 23 may be formed of a nitride semiconductor other than Al0.30Ga0.70N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0 ≦ x <0.4, and y is 0 ≦ y <1.

The recess 15a extends from one main surface 1a of the main semiconductor region 3a to the first electron supply layer 21 through the third electron supply layer 23 and the second electron supply layer 22, and further reaches the first electron supply layer 21. It is formed so as to bite into the electron supply layer 21. Therefore, only the remaining portion 18 of the first electron supply layer 21 is disposed between the recess 15 a and the electron transit layer 4. In the embodiment of FIG. 4, the recess 15 a bites into the first electron supply layer 21, but the recess 15 a can be modified so as not to bite into the first electron supply layer 21. In any case, if the p-type metal oxide semiconductor film 10 is not provided, a 2DEG layer is formed in a portion facing the gate electrode 8 of the electron transit layer 4 in a normally state, and the p-type metal oxide semiconductor is formed. In the case where the film 10 is provided, the depth of the recess 15a is set so that the 2DEG layer does not occur in the portion facing the gate electrode 8 of the electron transit layer 4 in the normally state.

The side surface 17a of the recess (recess) 15a has an inclination of 15 to 80 degrees so that the recess (recess) 15a is tapered. The inclination angle of the side surface 17 a of the recess (recess) 15 a is slightly larger than the inclination angle (5 to 60 degrees) of the side surface 19 of the opening of the insulating film 9. Of course, also in FIG. 4, the side surface 17a of the recess 15a can be formed substantially perpendicular to the side surface 17 of the recess 15 in FIG. Since the p-type metal oxide semiconductor film 10 has a relatively high resistance, the field plate 11 is insulated from the field plate 11 by facing the main semiconductor region 3a through the p-type metal oxide semiconductor film 10. The same effect as the electric field concentration mitigation effect obtained by facing the main semiconductor region 3a through the film 9 can be obtained. In addition, since the second electron supply layer 22 having a relatively high electron concentration is exposed at the side surface 17a of the recess 15a, the effect of reducing the electric field concentration by the field plate 11 can be obtained satisfactorily.

5 shows the gate-source voltage Vgs and drain-source of the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the heterojunction field effect semiconductor devices of the first, second and third comparative examples. The relationship with the inter-current Ids is shown.

That is, in the characteristic line A1, the recess (recess) 15a and the p-type metal oxide semiconductor film 10 are omitted from FIG. 4, and a gate electrode made of a Ni / Au laminate is provided on one main surface 13 of the main semiconductor region 3a. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 1st comparative example of a structure is shown. The characteristic line A2 is the p-type metal oxide semiconductor film 10 omitted from FIG. 4, the recess (recess) 15a and the field plate 11 are provided, and the gate electrode made of a Ni / Au laminate is provided on the recess (recess) 15a. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 2nd comparative example of a structure is shown.

The characteristic line B1 is obtained by removing the recess 15a from FIG. 4 and providing a p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx) having a thickness of 200 nm and forming Ni on the p-type metal oxide semiconductor film 10. The Vgs-Ids characteristic of the heterojunction field effect semiconductor device of the 3rd comparative example of the structure provided with the gate electrode which consists of / Au laminated body is shown.

The characteristic line B2 indicates the structure shown in FIG. 4, that is, the structure obtained by adding the recess 15a and the field plate 11 to the third comparative example, that is, the Vgs-Ids of the telojunction field effect semiconductor device having the structure according to the second embodiment. Show properties.

The threshold voltages of the characteristic lines A1, A2, and B1 of the first, second, and third comparative examples in FIG. 5 are all negative. On the other hand, the threshold voltage of the characteristic line B2 of Example 2 is positive. Accordingly, a normally-off type heterojunction field effect semiconductor device having a positive threshold voltage, that is, a field effect semiconductor device having a HEMT or a HEMT-like structure can be obtained according to the second embodiment.

FIG. 6 shows the drain-source voltage Vds and gate leakage of the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the heterojunction field effect semiconductor devices of the first, second and third comparative examples. The relationship with the current Ig is shown.
That is, the characteristic line C1 shows the Vds-Ig characteristic of the first comparative example.
A characteristic line C2 shows the Vds-Ig characteristic of the second comparative example.
A characteristic line D1 indicates the Vds-Ig characteristic of the heterojunction field effect semiconductor device having a structure in which the field plate 11 is omitted from the third comparative example.
A characteristic line D2 shows the Vds-Ig characteristic of Example 2.

Note that the gate leakage current Ig in each characteristic of FIG. 6 indicates the gate-drain current when the gate-source voltage Vgs is kept at zero.

The gate leakage current Ig of Example 2 indicated by the characteristic line D2 is smaller than the gate leakage currents Ig of the first, second, and third comparative examples of the characteristic lines C1, C2, and D1. That is, when the field plate 11 is provided and the p-type metal oxide semiconductor film 10 having a high resistivity is provided, the gate leakage current is suppressed and the breakdown voltage is improved.

In addition to the same effects as the first embodiment of FIG. 1, the second embodiment of FIG. 4 has the following effects.
(1) Since the first electron supply layer 21 having a low Al ratio is disposed adjacent to the electron transit layer 4, a positive threshold voltage can be obtained with certainty.
(2) The second electron supply layer 22 disposed adjacent to the first electron supply layer 21 has a higher Al ratio than the first electron supply layer 21 and is higher than the first electron supply layer 21. Since it has a high electron concentration, the electron concentration of the 2DEG layer 12 in a portion other than the recess 15a of the main semiconductor region 3a can be increased, and the on-resistance of the heterojunction field effect semiconductor device can be reduced. That is, if the second and third electron supply layers 22 and 23 are omitted in FIG. 4, the electron supply layer is configured by only the first electron supply layer 21 whose Al ratio is lower than that of the electron supply layer 5 of FIG. 1. Then, the electron concentration of the 2DEG layer 12 becomes lower than the electron concentration of the 2DEG layer 12 of FIG. However, as shown in FIG. 4, the first electron supply layer 21 has a higher Al ratio than the first electron supply layer 21 and a higher electron concentration than the first electron supply layer 21. When the second electron supply layer 22 is disposed, the second electron supply layer 22 can compensate for a decrease in the electron concentration of the 2DEG layer 12 due to the provision of the first electron supply layer 21. As a result, the on-resistance of the heterojunction field-effect semiconductor device of FIG. 4 is the same as or lower than the on-resistance of the heterojunction field-effect semiconductor device of FIG. Since the recess 15a penetrates the second electron supply layer 22, the second electron supply layer 22 does not interfere with the normally-off characteristic.
(3) Since the recess 15a is provided so as to reach the first electron supply layer 21 in which the proportion of Al is low, the variation in threshold voltage due to the variation in the depth of the recess 15a is reduced. That is, if the ratio of Al and the electron concentration in the remaining portion 18 of the first electron supply layer 21 under the recess 15a is large, the variation in threshold voltage due to the variation in the thickness of the remaining portion 18 increases. In FIG. 4, since the ratio of Al in the remaining portion 18 is smaller than the ratio of Al in the remaining portion 18 in FIG. 1, the variation in threshold voltage due to the variation in the thickness of the remaining portion 18 is also reduced.
(4) Since the concave portion 15a has an inclined side surface 17a and the second electron supply layer 22 having a high electron concentration is exposed on the inclined side surface 17a, the electric field concentration in the vicinity of the gate electrode 8 is reduced. be able to. Since the field plate 11 is provided on the inclined side surface 17a of the recess 15a via the p-type metal oxide semiconductor film 10 having a resistivity that can be regarded as an insulator, the vicinity of the inclined side surface 17a of the recess 15a is provided. In this case, the field plate effect can be obtained. Thereby, the electric field concentration in the vicinity of the gate electrode 8 is further relaxed, and high resistance is achieved.
(5) Since the third electron supply layer 23 having a lower Al ratio than the second electron supply layer 22 is provided and this surface is one main surface of the main semiconductor region 3a, the main semiconductor region 3a It is possible to stabilize one of the main surfaces, and it becomes possible to reduce leakage current and suppress current collapse.

(Third embodiment)
Next, a field effect semiconductor device similar to the MESFET according to the third embodiment shown in FIG. 7 will be described. 7 that are substantially the same as those in FIGS. 1 and 4 are given the same reference numerals, and descriptions thereof are omitted.

The field effect semiconductor device of Example 3 in FIG. 7 has the same configuration as that in FIG. 4 except for the deformed main semiconductor region 3e. The main semiconductor region 3e of FIG. 7 includes a first semiconductor layer 4 ′ formed of the same material as the electron transit layer 4 of FIG. 4 and a second semiconductor layer 5 ′ doped with an n-type impurity (for example, Si). Consists of. For example, the second semiconductor layer 5 ′ is formed of the same material as the second electron supply layer 22 of FIG. 4 and is used as a current path between the source electrode 6 and the drain electrode 7. In order to obtain normally-off characteristics, a recess 15a is provided in the main semiconductor region 3e as in FIG. That is, the recess 15a is formed by removing a part of the second semiconductor layer 5 ′, and the remaining portion 18 ′ of the second semiconductor layer 5 ′ is between the recess 15a and the first semiconductor layer 4 ′. Has occurred. The depth of the recess 15a and the thickness of the remaining portion 18 'are determined so that electrons are discharged from the remaining portion 18' with the help of the p-type metal oxide semiconductor film 10 and the remaining portion 18 'is filled with the depletion layer. Yes.

The field effect semiconductor device of Example 3 in FIG. 7 operates in the same manner as a junction field effect transistor (FET), and the source electrode 6 and the gate electrode 8 with the potential of the drain electrode 7 higher than the potential of the source electrode 6. When a voltage equal to or higher than the threshold voltage is applied between the drain electrode 7 and the drain electrode 7, a drain current flows through the path of the drain electrode 7, the second semiconductor layer 5 ′, and the source electrode 6.

Example 3 of FIG. 7 has the following effects.
(1) With the help of the p-type metal oxide semiconductor film 10, normally-off characteristics can be obtained with certainty.
(2) Since the remaining portion 18 'under the gate electrode 8 of the second semiconductor layer 5' is relatively thick, the power loss here is small.
(3) The effect of the field plate 11 can be obtained in the same manner as the first and second embodiments shown in FIGS.

In addition, a diode forming conductor 50 ′ for connecting the gate electrode 8 and the source electrode 6 can be provided in the field effect semiconductor device of Example 3 in FIG. 7.

(Fourth embodiment)
FIG. 8 shows a part of a modified p-type metal oxide semiconductor film 10a of the heterojunction field effect semiconductor device according to the fourth embodiment. A p-type metal oxide semiconductor film 10a in FIG. 8 is a modification of the p-type metal oxide semiconductor film 10 in Example 1 in FIG. 1, and includes a first layer 51 made of nickel oxide and a second layer made of iron oxide. And a third layer 53 made of cobalt oxide. One main surface (lower surface) 54 of the p-type metal oxide semiconductor film 10 a in FIG. 8 is a surface in contact with the electron supply layer 5, and the other main surface (upper surface) 55 is a surface in contact with the gate electrode 8. It is desirable that the hole concentration of the first layer 51 is the highest and the hole concentration of the third layer 53 is the lowest.

Thus, the p-type metal oxide semiconductor film 10a composed of a stack of a plurality of different p-type metal oxide semiconductor materials has the same effect as the p-type metal oxide semiconductor film 10 of Example 1 in FIG. Have

The p-type metal oxide semiconductor film 10a can be used in place of the p-type metal oxide semiconductor film 10 of Examples 2 and 3 other than Example 1.

Further, the material of the first to third layers 51 to 53 of the p-type metal oxide semiconductor film 10a is changed to another material selected from, for example, nickel oxide, iron oxide, cobalt oxide, manganese oxide, and copper oxide. Can do. In addition, for example, the third layer 53 can be omitted from the first to third layers 51 to 53 of the p-type metal oxide semiconductor film 10a, or another layer can be added.

(Fifth embodiment)
FIG. 9 shows a part of a modified p-type metal oxide semiconductor film 10b of the heterojunction field effect semiconductor device according to the fifth embodiment. The p-type metal oxide semiconductor film 10b of FIG. 9 is a modification of the p-type metal oxide semiconductor film 10 of Example 1 of FIG. 1, and the hole concentration changes from one main surface 54 to the other main surface 55. It consists of a laminate of first, second and third layers 51a, 52a, 53a which are successively lowered. One main surface (lower surface) 54 of the p-type metal oxide semiconductor film 10 b in FIG. 9 is a surface in contact with the electron supply layer 5, and the other main surface (upper surface) 55 is a surface in contact with the gate electrode 8. Accordingly, the first layer 51 a having the highest hole concentration is in contact with the electron supply layer 5.

The first, second, and third layers 51a, 52a, and 53a having different hole concentrations are formed, for example, by gradually reducing the amount of oxygen added when sputtering nickel oxide (NiO) with a magnetron sputtering apparatus. The

As described above, the p-type metal oxide semiconductor film 10b composed of the stacked body of the first, second, and third layers 51a, 52a, and 53a having different hole concentrations is the p-type metal of Example 1 in FIG. The effect is similar to that of the oxide semiconductor film 10. In addition, since the first layer 51a having the highest hole concentration is in contact with the electron supply layer 5, normally-off characteristics can be favorably obtained.

The p-type metal oxide semiconductor film 10b can be used not only for the first embodiment but also for the other p-type metal oxide semiconductor films 10 of the second and third embodiments.

Further, for example, the third layer 53a can be omitted from the first to third layers 51a to 53a of the p-type metal oxide semiconductor film 10b, or another layer can be added.

Further, instead of stepwise changing the hole concentration of the p-type metal oxide semiconductor film 10b, the hole concentration gradually decreases from one main surface (lower surface) 54 to the other main surface (upper surface) 55, that is, It can be reduced with a slope. In this way, in order to gradually reduce the hole concentration of the p-type metal oxide semiconductor film 10b, the amount of oxygen added is gradually decreased with the progress of film formation, for example, of nickel oxide (NiOx) by magnetron sputtering.

In addition, in order to change the hole concentration in the thickness direction of the p-type metal oxide semiconductor film, conditions for heat treatment of the p-type metal oxide semiconductor film, ozone ashing treatment conditions, or O2 (oxygen) ashing with the progress of film formation Processing conditions can be changed.

Further, in order to change the hole concentration in the thickness direction of the p-type metal oxide semiconductor film, O2 ions can be implanted into the metal film or the p-type metal oxide semiconductor film 10b. According to this method, a desired hole concentration and a gradient of hole concentration can be easily obtained.

Further, in order to change the hole concentration in the thickness direction of the p-type metal oxide semiconductor film, the doping amount of lithium (Li) can be changed with the progress of film formation.

As mentioned above, although an example of an embodiment of the present invention was explained, the present invention is not limited to the specific embodiment concerned, and each example is within the scope of the gist of the present invention described in the claims. Or the combination of each modification is possible, for example, the following modification is possible.
(1) The main semiconductor regions 3, 3a and 3e are made of InGaN other than GaN and AlGaN, AllnGaN, AlN, InAlN, AlP, GaP, AllnP, GalnP, AlGaP, AlGaAs, GaAs, AlAs, InAs, InP, InN, GaAsP, etc. It can be formed of another group 3-5 compound semiconductor, a group 2-6 compound semiconductor such as ZnO, or another compound semiconductor.
(2) A well-known source field plate and drain field plate can be provided.
(3) Although one source electrode 6, one drain electrode 7, and one gate electrode 8 are shown in the drawings showing the respective embodiments, a plurality of them can be provided. That is, a plurality of minute FETs (unit FETs) can be provided on one chip, and these can be connected in parallel.
(4) A heterojunction field effect semiconductor device in which the electron supply layer of Examples 1 to 3 is replaced with a hole supply layer and a two-dimensional hole gas layer is formed as a two-dimensional carrier gas layer in a region corresponding to the 2DEG layer 12 Can be configured. In this case, an n-type metal oxide semiconductor film is provided instead of the p-type metal oxide semiconductor film 10. In FIG. 7, a p-type second semiconductor layer can be provided instead of the n-type second semiconductor layer 5 ′, and an n-type metal oxide semiconductor film can be provided thereon.
(5) Lithium (Li) can be added or injected instead of adding or injecting oxygen when obtaining the p-type metal oxide semiconductor film 10.
(6) Instead of implanting O2 ions into the p-type metal oxide semiconductor film 10, O2 ions can be implanted into the metal film.

(A) is sectional drawing which shows the heterojunction field effect semiconductor device of Example 1 of this invention, (B) is sectional drawing which expands and shows a part of gate electrode. FIG. 2 is an energy level diagram of the heterojunction field effect semiconductor device of Example 1 of FIG. 1 and two comparative examples. FIG. 2 is a diagram showing the relationship between the heterojunction field effect semiconductor device of Example 1 of FIG. 1 and the drain-source voltage Vds and gate current (gate leakage current) Ig of two comparative examples. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 2 of this invention. FIG. 6 is a diagram showing the relationship between the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the gate-source voltage Vgs and the drain-source current Ids of three comparative examples. FIG. 5 is a diagram showing the relationship between the heterojunction field effect semiconductor device of Example 2 of FIG. 4 and the drain-source voltage Vds and the gate leakage current Ig of three comparative examples. It is sectional drawing which shows the MESFET type field effect semiconductor device of Example 3 of this invention. It is sectional drawing which shows a part of p-type metal oxide semiconductor film according to Example 4 of this invention. It is sectional drawing which shows a part of p-type metal oxide semiconductor film according to Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Main semiconductor region 4 Electron traveling layer (first semiconductor layer 5 electron supply layer (second semiconductor layer 6 source electrode 7 drain electrode 8 gate electrode 9 insulating film made of silicon oxide 10 p-type metal) Oxide semiconductor film

Claims (2)

A main semiconductor region having at least one semiconductor layer for forming a current path; and an electrical connection to the semiconductor layer disposed on one main surface of the main semiconductor region and forming the current path A first main electrode coupled to the semiconductor layer, and electrically disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode and electrically forming the current path A second main electrode coupled between the first main electrode and the second main electrode on one main surface of the main semiconductor region to control the current path of the semiconductor layer; And a metal oxide semiconductor film disposed between the main semiconductor region and the gate electrode and having a function of reducing carriers of the semiconductor layer for forming the current path, Field effect semiconductor device comprising A method of production,
A method of manufacturing a field effect semiconductor device, comprising: depositing a thin film containing a metal material constituting the metal oxide semiconductor film on the main semiconductor region.
  2. The method of manufacturing a field effect semiconductor device according to claim 1, wherein oxygen is ion-implanted into the thin film in order to enhance a function of reducing the carriers.

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