JP5582378B2 - Field effect semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a field effect such as a high electron mobility transistor (HEMT), a diode having a two-dimensional electron carrier gas layer as a current path, a metal semiconductor field effect transistor (MESFET), or the like. The present invention relates to a semiconductor device and a manufacturing method thereof.

A conventional HEMT, which is a kind of field effect transistor, has an electron transit layer made of a nitride semiconductor such as undoped GaN formed on a substrate such as silicon or sapphire via a buffer layer, and is doped with an n-type impurity. Or it has the electron supply layer or barrier layer which consists of nitride semiconductors, such as undoped AlGaN, and the source electrode, drain electrode, and gate electrode (Schottky electrode) which were formed on the electron supply layer. The band gap of the electron supply layer made of AlGaN or the like is larger than the band gap of the electron transit layer made of GaN or the like, and the lattice constant of the electron supply layer made of AlGaN or the like is smaller than the lattice constant of the electron transit layer made of GaN or the like. . When an electron supply layer having a smaller lattice constant than this is disposed on the electron transit layer, an extensible strain, that is, a tensile stress, is generated in the electron supply layer, resulting in piezoelectric polarization. Since the electron supply layer also spontaneously polarizes, a well-known two-dimensional electron gas layer, that is, a 2DEG layer is formed in the vicinity of the heterojunction surface between the electron transit layer and the electron supply layer by the action of an electric field based on piezo polarization and spontaneous polarization. As is well known, the 2DEG layer functions as a current path (channel) between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

By the way, a HEMT having a general configuration has a characteristic that a current flows between a source electrode and a drain electrode in a state where a gate control voltage is not applied to the gate electrode (normally state), that is, a normally-on characteristic. In order to keep the normally-on HEMT in an off state, a negative power source for setting the gate electrode to a negative potential is required, and the electric circuit is necessarily expensive. Therefore, the ease of use of a conventional normally-on HEMT is not good.

Therefore, development of a heterojunction field effect semiconductor device having normally-off characteristics is underway. As a typical method for obtaining normally-off characteristics, a method is known in which a recess (recess) is formed in an electron supply layer, and a gate electrode is formed on the electron supply layer thinned by the recess.

When the electron supply layer is partially thinned by the recess according to the above method, the electric field based on piezoelectric polarization and spontaneous polarization in the thinned portion of the electron supply layer is weakened. Therefore, the electric field based on the piezo polarization and spontaneous polarization of the electron supply layer weakened due to the recess is a built-in potential between the gate electrode and the electron supply layer, that is, the bias voltage of the gate electrode. Is canceled by the potential difference between the gate electrode and the electron supply layer in a state where the zero is zero, and the 2DEG layer disappears from the portion of the electron transit layer facing the gate electrode. As a result, the drain-source is turned off in a state where no gate control voltage is applied to the gate electrode, and a normally-off characteristic is obtained.

JP 2005-183733 A

However, when the above method is used, there are the following problems.

The threshold value of the HEMT according to the above method is relatively small, for example, +1 V or less, and is likely to malfunction due to noise, and is relatively large when a positive gate control voltage is applied to the gate electrode composed of a Schottky electrode. Problems such as leakage current flow, dry etching for thinning the electron supply layer causes damage to the electron transit layer and the semiconductor crystal of the electron supply layer, and deteriorates the electrical characteristics of the HEMT. In the problem that the threshold voltage changes greatly due to variations, and in the thin part of the electron supply layer (barrier layer) under the gate electrode, a control voltage for turning on the HEMT (conductive state) is applied to the gate electrode. Since the ability to supply electrons to the electron transit layer is low even when the Can not concentration to form a sufficiently high 2DEG layer, the ON resistance between the drain electrode and the source electrode is relatively high.

The same problem as the above-described HEMT also exists in a diode using a 2DEG layer, a field effect semiconductor device (for example, MESFET) other than the HEMT, and the like.

Therefore, the problem to be solved by the present invention is that a normally-off type field effect semiconductor device with small on-resistance and gate leakage current is required, and the present invention can meet the above-mentioned requirements and has variations in characteristics. It is an object to provide a field effect semiconductor device and a method for manufacturing the same.

In order to solve the above problems, the inventors of the present invention have developed a field effect semiconductor device in which a p-type metal oxide semiconductor film is disposed between a gate electrode and an electron supply layer and a method for manufacturing the same (Japanese Patent Application). 2008-73603). The present invention has been made based on this discovery.

The field effect semiconductor device according to the invention of claim 1 comprises:

One and the other main surfaces facing each other;

A first semiconductor layer (electron transit layer) disposed between the one and other main surfaces;

A second semiconductor layer disposed between the first semiconductor layer and the one main surface and heterojunction to the first semiconductor layer and formed of a material having a lattice constant smaller than that of the first semiconductor layer; A semiconductor layer;

A third semiconductor layer disposed between the second semiconductor layer and the one main surface, lattice-matched to the second semiconductor layer, and made of a material having a lattice constant smaller than that of the first semiconductor layer; A semiconductor layer;

A two-dimensional carrier gas layer formed in the first semiconductor layer based on the heterojunction;

A main semiconductor region comprising:

A first main electrode disposed on the one main surface of the main semiconductor region and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer;

A second main electrode disposed on the one main surface of the main semiconductor region and spaced apart from the first main electrode and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer When,

A recess disposed between the first main electrode and the second main electrode on the one main surface of the main semiconductor region and penetrating the third semiconductor layer;

A metal oxide semiconductor film disposed on the recess and having a conductivity type for reducing carriers in the two-dimensional carrier gas layer;

A gate electrode disposed on the metal oxide semiconductor film;

It is characterized by providing.

According to a fourth aspect of the present invention, there is provided a field effect semiconductor device manufacturing method comprising:

One and the other main surfaces facing each other;

A first semiconductor layer (electron transit layer) disposed between the one and other main surfaces;

A second semiconductor layer disposed between the first semiconductor layer and the one main surface and heterojunction to the first semiconductor layer and formed of a material having a lattice constant smaller than that of the first semiconductor layer; A semiconductor layer;

A third semiconductor layer disposed between the second semiconductor layer and the one main surface, lattice-matched to the second semiconductor layer, and made of a material having a lattice constant smaller than that of the first semiconductor layer; A semiconductor layer;

A two-dimensional carrier gas layer formed in the first semiconductor layer based on the heterojunction;

A main semiconductor region comprising:

A method of manufacturing a field effect semiconductor device having:

Epitaxially growing the second semiconductor layer on the first semiconductor layer;

Selectively epitaxially growing the third semiconductor layer on the second semiconductor layer;

It is characterized by providing.

According to the inventions according to the claims of the present invention, it is possible to provide a field effect semiconductor device having normally-off characteristics with small on-resistance and gate leakage current and little variation in characteristics.

It is sectional drawing which shows the heterojunction type field effect semiconductor device of Example 1 of this invention. It is process sectional drawing which shows the manufacturing method of the heterojunction field effect semiconductor device of Example 1 of FIG. FIG. 2 is an energy level diagram of the heterojunction field effect semiconductor device of Example 1 of FIG. 1 and two comparative examples. It is sectional drawing which shows the heterojunction field effect semiconductor device of Example 2 of this invention. It is sectional drawing which shows the modification of the heterojunction field effect semiconductor device of this invention.

Next, a heterojunction field effect semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

A heterojunction field effect semiconductor device according to a first embodiment of the present invention shown in FIG. 1 includes a substrate 1 made of a single crystal silicon semiconductor and a buffer layer 2 on one main surface 1a of the substrate 1 sequentially. A main semiconductor region comprising an electron transit layer 4 as a first semiconductor layer, a first electron supply layer 5a as a second semiconductor layer, and a second electron supply layer 5b as a third semiconductor layer 3, the source electrode 6 as the first main electrode disposed on the main semiconductor region 3, the drain electrode 7 and the gate electrode 8 as the second main electrode, and the main semiconductor region 3. Insulating films 9a and 9b made of silicon oxide, a p-type metal oxide semiconductor film 10 according to the present invention, a gate field plate 11, and a cap layer 12 are provided. Although this heterojunction field effect semiconductor device has an insulated gate structure different from that of a typical HEMT, it operates on the same principle as that of a typical HEMT, and can also be called a HEMT or a HEMT type semiconductor device. Hereinafter, each part of FIG. 1 will be described in detail.

The substrate 1 has one main surface 1a and the other main surface 1b opposite thereto, and functions as a growth substrate for epitaxially growing semiconductor materials for the buffer layer 2 and the main semiconductor region 3, and It functions as a support substrate for supporting these mechanically. In this embodiment, the substrate 1 is made of silicon in order to reduce costs. However, the substrate 1 may be formed of a semiconductor such as silicon carbide (SiC) other than silicon, or an insulator such as sapphire or ceramic.

The buffer layer 2 on one main surface 1a of the substrate 1 is formed by an epitaxial growth method such as a well-known MOCVD method. In FIG. 1, the buffer layer 2 is shown as a single layer for the sake of simplicity, but actually, it is formed of a plurality of layers. In other words, the buffer layer 2 has alternating first sublayers (first sublayer) made of AlN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride). Is a multi-layered buffer laminated on the substrate. Since the buffer layer 2 is not directly related to the operation of the HEMT, it can be omitted. Further, the semiconductor material of the buffer layer 2 can be replaced with a nitride semiconductor other than AlN or GaN or a Group 3-5 compound semiconductor, or a buffer layer having a single layer structure can be formed.

The main semiconductor region 3 has one main surface 13 and the other main surface 14 facing each other, and the electron transit layer 4 as the first semiconductor layer is disposed on the one main surface 14 side, and the second semiconductor The first electron supply layer 5 a as a layer and the second electron supply layer 5 b as a third semiconductor layer are disposed between the electron transit layer 4 and the other main surface 13. The electron transit layer 4 is made of a first nitride semiconductor and has a thickness of 0.3 to 10 μm. The electron transit layer 4 has a two-dimensional electron gas layer (2DEG layer) as a two-dimensional carrier gas layer functioning as a current path (channel) in the vicinity of the heterojunction surface with the first electron supply layer 5a. It consists of undoped GaN (gallium nitride) epitaxially grown by a well-known MOCVD method.

Note that the electron transit layer 4 is made of, for example, AlaInbGa1-a-bN other than GaN,
Here, a is a numerical value satisfying 0 ≦ a <1, b is 0 ≦ b <1,
It can also be formed of a nitride semiconductor such as, or another compound semiconductor.

The first electron supply layer 5a formed on the electron transit layer 4 has a band gap larger than that of the electron transit layer 4 and a second nitride semiconductor having a lattice constant smaller than that of the electron transit layer 4. It is formed to a thickness of 0 to 20 nm, more preferably 2 to 15 nm, and most preferably 5 to 10 nm (for example, 7 nm). The first electron supply layer 5a of this embodiment is made of undoped Al0.26Ga0.74N epitaxially grown by a known MOCVD method. Note that the first electron supply layer 5a can be formed of a nitride semiconductor other than Al0.26Ga0.74N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0 <x <1, y is 0 ≦ y <1, and a preferable value of x is 0.1 to 0.4.

Instead of forming the first electron supply layer 5a with undoped AlxInyGa1-x-yN, a nitride semiconductor made of AlxInyGa1-x-yN doped with n-type (first conductivity type) impurities, or another It can also be formed of a nitride semiconductor having a composition or another compound semiconductor.

The first electron supply layer 5a may be formed so as to generate a 2DEG layer in the electron transit layer 4 based on the above-described heterojunction, and based on the synergistic effect of the heterojunction and lattice matching (described later). A 2 DEG layer may be formed in the electron transit layer 4.

The second electron supply layer 5b formed on the first electron supply layer 5a is formed so as to lattice match with the first electron supply layer 5a, and has a larger band gap than the electron transit layer 4. The third nitride semiconductor having a lattice constant smaller than that of the electron transit layer 4 is preferably formed to a thickness of 10 to 50 nm (for example, 18 nm). The second electron supply layer 5b generates 2DEG in the electron supply layer 4 based on the lattice matching between the first electron supply layer 5a and the second electron supply layer 5b and the heterojunction. Alternatively, the carrier concentration of 2DEG can be increased. Therefore, the first electron supply layer 5a and the first electron supply layer 5b can be collectively referred to as an electron supply layer. The second electron supply layer 5b of this embodiment is made of undoped Al0.3Ga0.7N epitaxially grown by a known MOCVD method. Note that the second electron supply layer 5b can be formed of a nitride semiconductor other than Al0.3Ga0.7N, for example, represented by the following formula.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0 <x <1, y is 0 ≦ y <1, and a preferable value of x is 0.2 to 0.5.

The cap layer 12 formed on the second electron supply layer 5b is formed to reduce the surface level of the second electron supply layer 5b, and is 1 to 150 nm (for example, 4 nm) by the third nitride semiconductor. ). The cap layer 12 is made of undoped GaN epitaxially grown by a known MOCVD method. The cap layer 12 may be doped with silicon, and the cap layer 12 may be formed of a nitride semiconductor other than GaN, for example, represented by the following formula. Further, the cap layer 12 can be omitted.
AlxInyGa1-x-yN,
Here, x is a numerical value satisfying 0 ≦ x <1, y is satisfying 0 ≦ y <1, and a preferable value of x is 0 to 0.5.

A source electrode 6 and a drain electrode 7 are disposed on one main surface 13 of the main semiconductor region 3, and a recess 15 is provided. The recess 15 is formed between the source electrode 6 and the drain electrode 7 on one main surface 13 of the main semiconductor region 3, and has a bottom surface 16 and a pair of side surfaces 17, and the second electron supply layer 5 b. It is formed so as to penetrate. That is, the bottom surface 16 of the recess 15 is in contact with the top surface of the first electron supply layer 5a. Therefore, the first electron supply layer 5 a exists between the bottom surface 16 of the recess 15 and the electron transit layer 4.

The first insulating film 9a made of silicon oxide has a source electrode 6, a drain electrode 7 and a recess 15 on one main surface 13 of the main semiconductor region 3, that is, one main surface of the second electron supply layer 5b. It is arranged other than the part that is. More specifically, the first insulating film 9a made of silicon oxide is made of SiOx (where x is a numerical value of 1 to 2 and preferably 2), preferably plasma CVD (chemical vapor). A two-dimensional carrier gas having a property of generating compressive stress, ie compressive strain (for example, 4.00 × 10 9 dyn / cm 2). Contributes to increasing the carrier concentration of the layer. That is, since an electron supply layer made of AlGaN is disposed under the first insulating film 9a made of silicon oxide, this reaction occurs when the compressive stress of the first insulating film 9a made of silicon oxide acts. As a result, extensible strain, that is, tensile stress, is generated in the electron supply layer, the piezoelectric polarization of the electron supply layer is strengthened, and the electron concentration in the two-dimensional electron gas layer (2DEG layer) increases. This increase in the electron concentration contributes to a reduction in resistance between the source electrode 6 and the drain electrode 7 when the heterojunction field effect semiconductor device is on. The first insulating film 9 a made of silicon oxide is not disposed in the recess 15 and has an opening corresponding to the recess 15. The wall surface of the opening of the first insulating film 9a made of silicon oxide, that is, the side surface adjacent to the entrance of the recess 15 has an inclination of 5 to 60 degrees.

The second insulating film 9 b made of silicon oxide is disposed on the first insulating film 9 a and in the recess 15. More specifically, the second insulating film 9b is disposed between the surface 4 of the main semiconductor region 3 and the gate electrode 10, and is made of SiOx like the first insulating film 9a, preferably 3 to 200 nm ( For example, it is formed to a thickness of 100 nm. The second insulating film 9 b is for reducing the gate leakage current, and in the concave portion 15 on one main surface 13 of the main semiconductor region 3, the p-type metal oxide semiconductor film 10 and the main semiconductor region 3. It has a portion disposed between the first electron supply layer 5a and a portion extending on the first insulating film 9a through the side surface 17 of the recess 15.

Note that the first insulating film 9a and the second insulating film 9b made of silicon oxide can be formed by another method such as sputtering. However, plasma CVD is most excellent for reducing crystal damage on one main surface 13 of the main semiconductor region 3, reducing surface states (traps), and suppressing current collapse. Alternatively, the first insulating film 9a and the second insulating film 9b can be formed of another insulating material other than silicon oxide (for example, hafnium oxide or silicon nitride).

For the source electrode 6 and the drain electrode 7, for example, titanium (Ti) is vapor-deposited to a desired thickness (for example, 25 nm) on one main surface 13 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Aluminum (Al) is deposited to a desired thickness (for example, 300 nm), and then formed into a desired pattern by photolithography. The source electrode 6 and the drain electrode 7 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but are formed of a metal capable of low resistance contact (ohmic contact) other than this. You can also Since the first electron supply layer 5a in the main semiconductor region 3 is extremely thin, the resistance in the thickness direction is negligibly small. Accordingly, the source electrode 6 and the drain electrode 7 are electrically coupled to a 2DEG layer (not shown) as a current path.

The gate electrode 8 is made of a metal layer deposited on the p-type metal oxide semiconductor film 10 and faces the bottom surface 16 of the recess 15 with the p-type metal oxide semiconductor film 10 interposed therebetween. The gate electrode 8 of this embodiment was formed by vapor deposition on a 30 nm thick nickel (Ni) layer formed by vapor deposition on a p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx). It consists of a gold (Au) layer with a thickness of 300 nm. Depending on the combination of the p-type metal oxide semiconductor film 10 made of nickel oxide (NiOx), the nickel (Ni) layer, and the gold (Au) layer, the gate leakage current can be satisfactorily reduced. However, the gate electrode 8 can be formed of a multilayer film of a nickel (Ni) layer, a gold (Au) layer, and a titanium layer, an aluminum layer, a conductive polysilicon layer, or the like.

The gate field plate 11 is electrically connected to the gate electrode 8 and is formed continuously with the gate electrode 8, and a first insulating film 9 a made of silicon oxide, a second insulating film 9 b, and the like are formed on the surface of the cap layer 12. It faces through the p-type metal oxide semiconductor film 10. Since the first insulating film 9a and the second insulating film 9b made of silicon oxide have inclined side surfaces of 5 to 60 degrees, the distance between the gate field plate 11 and the cap layer 12 is the gate on the bottom surface 16 of the recess 15. It gradually increases as the distance from the electrode 8 increases. Thereby, the relaxation of the electric field concentration at the end of the gate electrode 8 can be achieved satisfactorily.

The p-type metal oxide semiconductor film 10 according to the present invention is disposed so as to cover the bottom surface 16 and the side surface 17 of the recess 15 and part of the first insulating film 9a and the second insulating film 9b made of silicon oxide, It is formed of a metal oxide semiconductor material having a higher resistivity than the electron supply layer, and preferably has a thickness of 3 to 1000 nm, more preferably 10 to 500 nm. When the p-type metal oxide semiconductor film 10 is thinner than 3 nm, the normally-off characteristic cannot be obtained satisfactorily, and when it is thicker than 1000 nm, the turn-on characteristic by the control of the gate electrode 8 is deteriorated.

The p-type metal oxide semiconductor film 10 of this embodiment is made of 200 nm thick nickel oxide (NiOx, where x is an arbitrary numerical value, for example, 1) formed by magnetron sputtering. The p-type metal oxide semiconductor film 10 is formed by, for example, magnetron sputtering, and the inside of the magnetron sputtering apparatus is set to an atmosphere containing oxygen (preferably a mixed gas of argon and oxygen), and nickel oxide (NiO) is sputtered. Can be obtained. When nickel oxide is sputtered in an atmosphere containing oxygen, the p-type metal oxide semiconductor film 10 having a high hole concentration can be easily obtained.

A p-type metal oxide semiconductor film 10 formed by sputtering nickel oxide in an oxygen-containing atmosphere has a higher hole concentration than GaN to which a conventional p-type impurity is added and is relatively large. Has resistivity. Therefore, the p-type metal oxide semiconductor film 10 raises the potential under the gate electrode 8 relatively high to prevent the two-dimensional electron gas layer from being formed in the portion of the electron transit layer 4 below the gate electrode 8. To do. Alternatively, the p-type metal oxide semiconductor film 10 can further increase the HEMT gate threshold. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained. The p-type metal oxide semiconductor film 10 contributes to a reduction in gate leakage current (leakage current) during the operation of the HEMT.

FIG. 2 is a process cross-sectional view illustrating the method for manufacturing the heterojunction field effect semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 2A, a substrate 1 made of Si, SiC, sapphire, ceramic, or the like is prepared, and a buffer layer 2, an electron transit layer 4 and a first electron supply layer 5 are formed on the substrate 1. Sequentially epitaxially grow.

Next, as shown in FIG. 2B, the oxide film formed on the first electron supply layer 5a is patterned by a photolithography process to form a mask 20. The mask 20 is formed at a location where the source electrode 6, the drain electrode 7 and the gate electrode 8 (recess 15) are to be formed.

Next, as shown in FIG. 2C, the second electron supply layer 5b and the cap layer 12 are sequentially epitaxially grown on the first electron supply layer 5a. Since the second electron supply layer 5b and the cap layer 12 are not formed on the entire surface of the first electron supply layer 5a by the mask 20, this process can be called a selective epitaxial growth process.

Next, as shown in FIG. 2D, after removing the mask 20 by well-known wet etching, an ohmic electrode is deposited on the entire surface, and patterning is performed by a photolithography process to form the source electrode 6 and the drain electrode 7. .

Next, as shown in FIG. 2E, a first insulating film 9a is formed on the entire surface, and the first insulating film 9a around the recess 15 where the gate electrode 8 is formed is opened through a photolithography process. .

Next, as shown in FIG. 2F, after the source electrode 6 and the drain electrode 7 are ohmically connected to the first electron supply layer 5a by an annealing process, a second insulating film 9b is formed on the entire surface. .

Next, as shown in FIG. 2G, magnetron sputtering is performed in an atmosphere containing oxygen, and patterning is performed by a photolithography process to form a p-type metal oxide semiconductor film 10.

Next, as shown in FIG. 2H, Ni and Au are vapor-deposited on the entire surface, and patterning is performed by a photolithography process to form the gate electrode 8 and the gate field plate 11.

In this embodiment, the patterning of the p-type metal oxide semiconductor film 10 is performed in a separate process from the patterning of the gate field plate 11 and the gate electrode 8, but these can also be patterned at the same time.

In the method of manufacturing the heterojunction field effect semiconductor device according to the first embodiment of the present invention, since the second electron supply layer 5b is formed by selective epitaxial growth, the electron supply layer is thinned to form the recess 15. This dry etching process is not required. Therefore, it is possible to suppress the etching damage to the first electron supply layer 5a, and it is easy to control the thickness of the electron supply layer existing between the electron transit layer 4 and the recess 15.

Instead of forming the p-type metal oxide semiconductor film 10 with the nickel oxide, iron oxide (FeOx, where x is an arbitrary numerical value, for example, 2), cobalt oxide (CoOx, where x is arbitrary) For example, 2), manganese oxide (MnOx, where x is an arbitrary numerical value, for example, 1), and copper oxide (CuOx, where x is an arbitrary numerical value) For example, it can be formed by at least one selected from 1. The p-type metal oxide semiconductor film made of a metal oxide other than nickel oxide is also preferably formed by sputtering a metal material in an atmosphere containing oxygen.

The p-type metal oxide semiconductor film 10 may be formed by forming a metal film by sputtering or the like and then oxidizing the metal film instead of forming the metal material by sputtering in an atmosphere containing oxygen. it can.

Further, the p-type metal oxide semiconductor film 10 can be formed by reactive sputtering in addition to the magnetron sputtering, and a physical vapor deposition method such as a well-known molecular beam epitaxy (MBE) method or a pulsed laser deposition (PLD) method, Alternatively, it can be grown by a chemical vapor deposition method such as a well-known MOCVD method.

For example, if the magnetron sputtering method is used, the p-type metal oxide semiconductor film 10 can be formed at a high deposition rate. Further, when the p-type metal oxide semiconductor film 10 is formed using a metal oxide as a target, the film composition can be made uniform by using a physical vapor deposition method such as reactive sputtering, ECR sputtering, or laser fractionation. . In addition, when the MBE method or the PLD method is used, the film formation rate becomes slow, while the film thickness can be made uniform in addition to the film composition. If the MOCVD method is used, the p-type metal oxide semiconductor film 10 can be formed at a high deposition rate, and the film thickness can be made uniform even on the uneven surface such as the recess 15. As described above, the p-type metal oxide semiconductor film 10 in the present invention can be formed by using any physical or chemical vapor deposition method.

Further, in order to enhance the p-type characteristics of the p-type metal oxide semiconductor film 10, the p-type metal oxide semiconductor film 10 is subjected to heat treatment, ozone ashing treatment, or O2 (oxygen). It can be activated by performing ashing treatment or by ion-implanting O 2 into the p-type metal oxide semiconductor film 10.

In the heterojunction field effect semiconductor device of FIG. 1, when the gate control voltage is not applied to the gate electrode 8 (when the gate voltage is zero), even if the potential of the drain electrode 7 is higher than the potential of the source electrode 6. At most, a recess 15 is provided corresponding to the gate electrode 8, the electron supply layer is thinned under the gate electrode 8, and the p-type metal oxide semiconductor film 10 is connected to the gate electrode 8 and the first electron supply. Since the 2DEG layer is not formed in the electron transit layer 4 below the gate electrode 8, the 2DEG layer is divided, and the source electrode 6 and the drain electrode 7 are turned off. Become.

3A is an energy level diagram of a recess of the heterojunction field effect semiconductor device of FIG. 1, and FIG. 3B is an energy level of a conventional Schottky gate structure HEMT (hereinafter referred to as Comparative Example 1). FIG. 3C is a HEMT having a conventional Schottky gate structure in which the electron supply layer immediately below the gate electrode is thinly processed, that is, a HEMT having a structure in which the p-type metal oxide semiconductor film 10 is removed from FIG. 2) is shown. In these figures, EF represents the Fermi level, and EC represents the boundary level between the conduction band and the forbidden band. Further, Ni is the gate electrode 8, NiO is the p-type metal oxide semiconductor film 10, AlGaN in FIGS. 3A and 3C is the first electron supply layer 5a, and AlGaN in FIG. The electron supply layer 5 a, the second electron supply layer 5 b, and GaN indicate the electron transit layer 4.

In the heterojunction field effect semiconductor device of FIG. 1, since the first electron supply layer 5a under the gate electrode 8 is as thin as 10 nm or less, the first electron supply layer 5a under the gate electrode 8 is thin as in FIG. Lattice relaxation occurs in the electron supply layer 5a, the charge due to piezo polarization is reduced, and the bulk characteristics are diminished to reduce the charge due to spontaneous polarization. The reduction of these charges in the first electron supply layer 5a results in a decrease in Fermi level, and the potential under the gate electrode 8 is relatively increased. Further, since the p-type metal oxide semiconductor film 10 is provided, the potential under the gate electrode 8 is raised as shown in FIG. As a result, a two-dimensional carrier gas layer is not formed in the portion of the electron transit layer 4 facing the gate electrode 8, and a heterojunction field effect semiconductor device having normally-off characteristics is obtained. In other words, at the normal time, the polarization of the first electron supply layer 5 a under the recess 15 is canceled by the p-type metal oxide semiconductor film 10 and faces the gate electrode 8 of the electron transit layer 4. A two-dimensional carrier gas layer is not formed in the portion.

When a positive gate control voltage higher than a predetermined threshold voltage is applied between the gate electrode 8 and the source electrode 6 in a state where the potential of the drain electrode 7 is higher than the potential of the source electrode 6, the gate of the electron transit layer 4 A channel (current passage) is formed in a portion facing the electrode 8. That is, when a positive gate control voltage is applied to the gate electrode 8, polarization occurs in the p-type metal oxide semiconductor film 10, and holes are formed on the first electron supply layer 5a side of the p-type metal oxide semiconductor film 10. Are collected and electrons are induced on the side of the electron transit layer 4 in contact with the first electron supply layer 5a to form a channel. As a result, the source electrode 6 and the drain electrode 7 are turned on, and electrons are supplied to the source electrode 6, the second electron supply layer 5b, the first electron supply layer 5a, the 2DEG layer, the channel, the 2DEG layer, the second 1 flows through the path of the electron supply layer 5 a and the drain electrode 7. As is well known, since the first electron supply layer 5a is extremely thin, electrons pass through the tunneling effect in the thickness direction.

The p-type metal oxide semiconductor film 10 can also be regarded as an insulator, and has a higher resistivity than conventional p-type GaN or the like. For this reason, the current passing through the gate electrode 8 at the time of normally-off is greatly limited. The gate leakage current is about 1 × 10 −5 (A / mm) when the drain-source voltage of the conventional HEMT without the p-type metal oxide semiconductor film 10 and the second insulating film 9b is 300V. On the other hand, when the p-type metal oxide semiconductor film 10 is provided and the second insulating film 9b is not provided, the gate leakage current when the drain-source voltage is 300 V is about 1 × 10 −9 (A / mm). Met. Further, when the p-type metal oxide semiconductor film 10 and the second insulating film 9b are provided as shown in FIG. 1, the gate leakage current when the drain-source voltage is 300 V is about 0.7 × 10 −9 ( A / mm). As is apparent from the above, when the p-type metal oxide semiconductor film 10 is provided, not only the normally-off characteristics are improved, but also the gate leakage current is reduced. Further, when the second insulating film 9b is provided, the gate leakage current is further reduced.

The heterojunction field effect semiconductor device of Example 1 of FIG. 1 has the following effects.
(1) The p-type metal oxide semiconductor film 10 formed by sputtering (magnetron sputtering or reactive sputtering) in an atmosphere containing oxygen has a higher hole concentration than GaN to which a conventional p-type impurity is added. The p-type metal oxide semiconductor film 10 having a high hole concentration pulls up the potential under the gate electrode 8 well, and a two-dimensional electron gas layer is formed in the electron transit layer 4 under the gate electrode 8 during normal operation. Is well suppressed. As a result, a heterojunction field effect semiconductor device having good normally-off characteristics can be obtained.
(2) The p-type metal oxide semiconductor film 10 has a relatively high resistivity (insulating property) and is formed relatively thick (for example, 10 to 500 nm). Therefore, the gate leakage current during the operation of the heterojunction field effect semiconductor device is reduced, the breakdown voltage of the heterojunction field effect semiconductor device is improved, and the reliability is improved. Note that the threshold voltage does not shift to the negative side even if the p-type metal oxide semiconductor film 10 is formed relatively thick. In particular, when the p-type metal oxide semiconductor film 10 is made of nickel oxide (NiOx) and the gate electrode 8 is made of a nickel (Ni) layer and a gold (Au) layer, the effect of reducing the gate leakage current is excellent. It is done.
(3) The mask 20 for performing selective epitaxial growth is removed by wet etching. Since the damage caused to the first electron supply layer 5a by this wet etching is negligibly small compared to the damage by dry etching, a heterojunction field effect semiconductor device with little deterioration in electrical characteristics can be obtained.
(4) By forming the first electron supply layer 5a by selective epitaxial growth, it is possible to control the thickness of the electron supply layer 5a with high accuracy as compared with control by dry etching. Therefore, a heterojunction field effect semiconductor device with little variation in electrical characteristics can be obtained.
(5) Since the second insulating film 9b having a higher resistivity than the p-type metal oxide semiconductor film 12 is provided between the gate electrode 8 and the main semiconductor region 3, the gate leakage current is significantly reduced. In addition, since the second insulating film 9b covers the first first electron supply layer 5a, the surface of the first electron supply layer 5a is stabilized, and current collapse can be reduced.
(6) The p-type metal oxide semiconductor film 10 is subjected to a heat treatment, an ozone ashing process, an O2 (oxygen) ashing process, or the p-type metal oxide semiconductor film 10 By ion-implanting and activating O2, the p-type characteristics (hole concentration) of the p-type metal oxide semiconductor film 10 can be easily enhanced. Therefore, the effect that the p-type metal oxide semiconductor film 10 raises the potential below the gate electrode 8 becomes strong, and a field effect semiconductor device having a relatively large threshold voltage can be obtained.

The heterojunction field effect semiconductor device according to the second embodiment shown in FIG. 4 is formed substantially the same as the heterojunction field effect semiconductor device of FIG. 1 except that it has a modified second insulating film 9c. . The deformed second insulating film 9c is arranged in the same manner as the second insulating film 9c in FIG. 1 in the recess 15, but outside the recess 15 below the first insulating film 9a. Has been placed. Since both the first insulating film 9a and the second insulating film 9c are made of silicon oxide, the laminated portion of the first insulating film 9a and the second insulating film 9c in FIG. It functions in the same manner as the laminated portion of the insulating film 9a and the second insulating film 9b.

Since the heterojunction field effect semiconductor device of the second embodiment has the same basic structure as the heterojunction field effect semiconductor device of the first embodiment, it has the same effects as the first embodiment.

As mentioned above, although an example of an embodiment of the present invention was explained, the present invention is not limited to the specific embodiment concerned, and each example is within the scope of the gist of the present invention described in the claims. Or the combination of each modification is possible. For example, the second insulating film 9b may be formed only under the p-type metal oxide semiconductor film 10 as shown in FIG. 5A, and the second insulating film as shown in FIG. Even if 9b is not formed, normally-off characteristics can be obtained. Further, the thickness of the first electron supply layer 5a may be non-uniform, a multilayer structure may be used, and the first electron supply layer 5a may not be formed immediately below the source electrode 6 and the drain electrode 7. Further, the cap layer 12 may not be formed.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Main semiconductor region 4 Electron transit layer (first semiconductor layer)
5a First electron supply layer (second semiconductor layer)
5b Second electron supply layer (third semiconductor layer)
6 Source electrode 7 Drain electrode 8 Gate electrode 9a First insulating film 9b, 9c Second insulating film 10 P-type metal oxide semiconductor film 11 Gate field plate 12 Cap layer 15 Recess

Claims (5)

One and the other main surfaces facing each other, a first semiconductor layer (electron transit layer) disposed between the one and the other main surface,
A second semiconductor layer disposed between the first semiconductor layer and the one main surface and heterojunction to the first semiconductor layer and formed of a material having a lattice constant smaller than that of the first semiconductor layer; A semiconductor layer (first electron supply layer), disposed between the second semiconductor layer and the one main surface, lattice-matched to the second semiconductor layer, and more than the first semiconductor layer A third semiconductor layer (second electron supply layer) formed of a material having a small lattice constant;
A main semiconductor region comprising: a two-dimensional carrier gas layer formed in the first semiconductor layer based on the heterojunction;
A first main electrode disposed on the one main surface of the main semiconductor region and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer; and the one of the main semiconductor regions A second main electrode disposed on the main surface spaced apart from the first main electrode and electrically coupled to the two-dimensional carrier gas layer of the first semiconductor layer; and the main semiconductor region A recess disposed between the first main electrode and the second main electrode on one main surface and penetrating the third semiconductor layer; and the two-dimensional carrier gas disposed on the recess A metal oxide semiconductor film having a conductivity type for reducing the carrier of the layer, and a gate electrode disposed on the metal oxide semiconductor film,
The second semiconductor layer and the third semiconductor layer are adjacent electron supply layers having an opening corresponding to the recess, a side surface adjacent to the entrance of the recess having an inclination of 5 to 60 degrees, and having a compressive stress . A first insulating film that causes tensile stress in the semiconductor layer ;
A field effect semiconductor device comprising: a gate field plate disposed on the first insulating film; 2. The field effect semiconductor device according to claim 1, wherein the two-dimensional carrier gas layer is formed in the first semiconductor layer based on the heterojunction and the lattice matching.
The field effect semiconductor device according to claim 1, wherein the metal oxide semiconductor film prevents at least a part of the two-dimensional carrier gas layer from being formed.
4. The field effect semiconductor according to claim 1 , wherein a second insulating film is formed between the metal oxide semiconductor film and the second semiconductor layer in the recess. 5. apparatus.
One and the other main surfaces facing each other;
A first semiconductor layer (electron transit layer) disposed between the one and other main surfaces;
A second semiconductor layer disposed between the first semiconductor layer and the one main surface and heterojunction to the first semiconductor layer and formed of a material having a lattice constant smaller than that of the first semiconductor layer; The semiconductor layer is formed of a material disposed between the second semiconductor layer and the one main surface, lattice-matched to the second semiconductor layer, and having a lattice constant smaller than that of the first semiconductor layer. A third semiconductor layer;
A two-dimensional carrier gas layer formed in the first semiconductor layer based on the heterojunction;
A main semiconductor region comprising:
A method of manufacturing a field effect semiconductor device having:
Epitaxially growing the second semiconductor layer on the first semiconductor layer;
A step of selectively epitaxially growing the third semiconductor layer on the second semiconductor layer to form a recess; and a reduction in carriers having a conductivity type that reduces carriers in the two-dimensional carrier gas layer on the recess. Forming a conductive metal oxide semiconductor film;
A step of forming a gate electrode on the metal oxide semiconductor film, a second electrode which has an opening corresponding to the recess, has a side surface inclined at an angle of 5 to 60 degrees, has a compressive stress, and is an adjacent electron supply layer The tensile stress is generated in the semiconductor layer and the third semiconductor layer .
And a step of forming a gate field plate on the first insulating film. A method of manufacturing a field effect semiconductor device, comprising:

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