JP2008235347A - Manufacturing process of recess gate type hfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture the recess gate type HFET having stable normally off characteristic. <P>SOLUTION: The manufacturing process of recess gate type HFET including a hetero junction of a GaN layer and a AlGaN layer on a substrate and forming a gate electrode on the AlGaN layer comprises a first step to form the GaN layer on the substrate, a second step to form a first AlGaN layer on the GaN layer in the thickness of 1 nm or more and 3 nm or less, a third step to form, through re-growth, a second AlGaN layer at least on a part of the front surface of a region except for a gate electrode forming region among the front surface of the first AlGaN layer, and a fourth step to form the gate electrode in a gate electrode forming region on the front surface of the first AlGaN layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a recessed gate HFET, and more particularly, to a method for manufacturing a recessed gate HFET that can stably manufacture a recessed gate HFET having normally-off characteristics.

  Nitride semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlInGaN) have a band gap compared to gallium arsenide (GaAs) based semiconductor materials. Since energy is large, an electronic device using a nitride semiconductor material has a high heat-resistant temperature and is excellent in operation at a high temperature.

  In particular, application of electronic devices such as FETs using GaN as power supply devices is expected. Here, consider using an FET as a power supply device.

  When a power circuit such as a converter or an inverter is configured using an existing circuit, the FET is required to exhibit normally-off characteristics.

  As an FET exhibiting normally-off characteristics, there is a method of thinning an electron supply layer (for example, an AlGaN layer) immediately below a gate electrode by recess etching.

  For example, in Patent Documents 1 to 3, a recessed gate type HFET including a heterojunction of a GaN layer and an AlGaN layer that realizes a normally-off characteristic by forming a gate electrode in a portion thinned by recess etching of an electron supply layer. (Heterostructure Field Effect Transistor) is disclosed.

  FIG. 16 shows a typical configuration of the recessed gate type HFET described in Patent Documents 1 to 3. Here, the recess gate type HFET described in Patent Document 1 is obtained by sequentially growing a low-temperature GaN buffer layer 11, an undoped GaN layer 12, an n-type AlGaN layer 13, and an n + -type AlGaN layer 14 on a sapphire substrate 10. After dry etching and reducing the thickness of the n-type AlGaN layer 13 in the gate electrode formation region, the gate electrode 7 is formed on the surface of the thinned n-type AlGaN layer 13, and the n + -type AlGaN layer 14 is formed. For example, the source electrode 6 and the drain electrode 8 are formed on the surface.

  However, in the methods described in Patent Documents 1 to 3, the dry etching time becomes too short due to the high dry etching rate (usually about 1 nm / s), and the control becomes difficult. There is a problem that it is difficult to control the dry etching amount because there is an in-plane variation in amount (about 10% of the target etching amount).

  Therefore, the methods described in Patent Documents 1 to 3 cannot stably produce a recessed gate type HFET having normally-off characteristics.

  Therefore, Patent Document 4 discloses a method of manufacturing a recessed gate type HFET having normally-off characteristics by re-growing an n-type AlGaN layer in a region other than the gate electrode formation region to form a recessed gate.

However, even the method described in Patent Document 4 is insufficient to manufacture a recessed gate type HFET having stable normally-off characteristics.
JP 2000-277724 A JP 2003-229413 A Japanese Patent No. 3546634 JP 2005-191181 A

  In view of the above circumstances, an object of the present invention is to provide a method of manufacturing a recessed gate type HFET that can stably manufacture a recessed gate type HFET having normally-off characteristics.

  According to a first aspect of the present invention, there is provided a method of manufacturing a recessed gate type HFET having a heterojunction between a GaN layer and an AlGaN layer on a substrate and having a gate electrode formed on the AlGaN layer, A first step of forming a GaN layer on the substrate, a second step of forming a first AlGaN layer on the GaN layer to a thickness of 1 nm to 3 nm, and formation of a gate electrode in the surface of the first AlGaN layer A third step of forming a second AlGaN layer by regrowth on at least a part of the surface other than the region, and a fourth step of forming a gate electrode in a gate electrode formation region on the surface of the first AlGaN layer; A method for manufacturing a recessed gate type HFET can be provided.

  Here, in the first aspect of the present invention, in the third step, the second AlGaN layer is preferably formed to a thickness of 10 nm or more.

  In addition, according to the second aspect of the present invention, a recessed gate type having a heterojunction portion between a GaN layer and an AlGaN layer on a substrate, and having a source electrode, a drain electrode, and a gate electrode formed on the AlGaN layer, respectively. A method for manufacturing an HFET, comprising: a first step of forming a GaN layer on a substrate; a second step of forming a first AlGaN layer on the GaN layer to a thickness of 1 nm to 3 nm; A third step of forming a second AlGaN layer by regrowth on at least a part of the surface of the AlGaN layer other than the formation region of each of the source electrode, the drain electrode, and the gate electrode; And a fourth step of forming a source electrode, a drain electrode, and a gate electrode on the surface of the AlGaN layer, respectively. Kill.

  Here, in the second aspect of the present invention, in the third step, the second AlGaN layer is preferably formed to a thickness of 10 nm or more.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the recessed gate type HFET which can manufacture the recessed gate type HFET which has a normally-off characteristic stably can be provided.

  Hereinafter, an embodiment which is an example of the present invention will be described. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

(Embodiment 1)
First, as shown in the schematic cross-sectional view of FIG. 1, a buffer layer 4 made of, for example, AlN (aluminum nitride), GaN, or the like on a substrate 5 made of, for example, Si (silicon), SiC (silicon carbide), or sapphire. Form. Then, the GaN layer 3 is formed on the buffer layer 4 (first step).

  Here, the GaN layer 3 can be formed, for example, by epitaxially growing a GaN crystal by MOCVD (Metal Organic Chemical Vapor Deposition) method using trimethylgallium and ammonia as raw materials.

  Next, as shown in the schematic cross-sectional view of FIG. 2, the first AlGaN layer 1 is formed on the GaN layer 3 so that the thickness T1 of the first AlGaN layer 1 is 1 nm or more and 3 nm or less ( Second step). Thereby, the two-dimensional electron gas layer 2 is formed on the GaN layer 3 side of the interface between the GaN layer 3 and the first AlGaN layer 1.

  Here, the first AlGaN layer 1 can be formed, for example, by epitaxially growing an AlGaN crystal by MOCVD using a raw material containing trimethylgallium, trimethylaluminum and ammonia. The first AlGaN layer 1 may be doped with an n-type impurity such as Si.

  Further, as shown in FIG. 2, a photoresist mask 19 patterned in a predetermined shape is formed on the surface of the first AlGaN layer 1.

  Here, the photoresist mask 19 has an opening 19a in a region where a gate electrode to be described later (gate electrode formation region) is formed, and the surface of the first AlGaN layer 1 is exposed from the opening 19a. Is done.

  Subsequently, as shown in the schematic cross-sectional view of FIG. 3, a selective growth mask 9 is formed on the photoresist mask 19.

  Here, as the selective growth mask 9, it is preferable to use a silicon oxide film and / or a silicon nitride film. When a silicon oxide film and / or a silicon nitride film is used as the selective growth mask 9, the selective growth mask 9 can be easily removed by etching with hydrofluoric acid diluted with hydrofluoric acid or ammonium fluoride. Therefore, it becomes easy to remove the selective growth mask 9 by etching after the second AlGaN layer, which will be described later, is formed by regrowth.

  The selective growth mask 9 can be formed by, for example, a normal CVD (Chemical Vapor Deposition) method or a sputtering method. The selective growth mask 9 can be formed to a thickness of, for example, about 50 nm. In order to remove the second AlGaN layer, which will be described later, by lift-off, the thickness of the selective growth mask 9 is larger than that of the second AlGaN layer, which will be described later. It is preferable to set it as the thickness.

  Then, as shown in the schematic cross-sectional view of FIG. 4, by removing the photoresist mask 19, the selective growth mask 9 formed on the photoresist mask 19 is also removed by lift-off, and the first AlGaN layer 1 is removed. The selective growth mask 9 is left only in the gate electrode formation region on the surface.

  Subsequently, as shown in the schematic cross-sectional view of FIG. 5, at least a part of the surface of the surface of the first AlGaN layer 1 other than the region (gate electrode formation region) protected by the selective growth mask 9. AlGaN is regrown thereon to form the second AlGaN layer 20 (third step).

  Here, the second AlGaN layer 20 is formed, for example, by epitaxially growing an AlGaN crystal again by MOCVD using a raw material containing trimethylgallium, trimethylaluminum and ammonia, MBE (Molecular Beam Epitaxy), or the like. Can do. The second AlGaN layer 20 may also be doped with an n-type impurity such as Si.

  Further, the thickness T2 of the second AlGaN layer 20 is preferably 10 nm or more, and more preferably 13 nm or more. When the second AlGaN layer 20 is formed with a thickness of 10 nm or more, particularly when the second AlGaN layer 20 is formed with a thickness of 13 nm or more, the two-dimensional electron gas concentration in the two-dimensional electron gas layer 2 is the characteristic of the recessed gate type HFET. It tends to be high enough to exert the effect.

  Thereafter, as shown in the schematic sectional view of FIG. 6, the selective growth mask 9 is removed. Here, AlGaN crystals are not grown on the surface of the selective growth mask 9 or amorphous AlGaN is formed, but even when amorphous AlGaN is formed, it is easily removed by lift-off or the like. be able to.

  Then, as shown in the schematic sectional view of FIG. 7, the gate electrode 7 is formed in the gate electrode formation region on the surface of the first AlGaN layer 1, and the gate electrode formation region on the surface of the first AlGaN layer 1 is formed. The source electrode 6 and the drain electrode 8 are formed on the surface of the second AlGaN layer 20 formed on both sides (fourth step).

  Here, as the gate electrode 7, for example, a tungsten (W) film having a thickness of 60 nm, a tungsten nitride (WN) film having a thickness of 10 nm, and a gold (Au) film having a thickness of 200 nm are sequentially stacked. Can do.

  As the source electrode 6 and the drain electrode 8, for example, a hafnium (Hf) film having a thickness of 2.5 nm, an aluminum (Al) film having a thickness of 60 nm, a hafnium (Hf) film having a thickness of 10 nm, and a film having a thickness of 60 nm are used. A film obtained by sequentially stacking a gold (Au) film and a tungsten (W) film having a thickness of 5000 nm can be used.

  The width W1 of the source electrode 6 can be set to 5 μm, for example, the width W3 of the gate electrode 7 can be set to 1.5 μm, for example, and the width W2 of the drain electrode 8 can be set to 5 μm, for example.

  The distance W4 between the source electrode 6 and the gate electrode 7 can be set to 1.5 μm, for example, and the distance W5 between the gate electrode 7 and the drain electrode 8 can be set to 5 μm, for example.

  In the present invention, a recessed gate type HFET can be manufactured by the method including the above steps.

  As described above, in the present invention, in the second step, the first AlGaN layer 1 is formed on the GaN layer 3 by epitaxially growing an AlGaN crystal to a thickness of 1 nm to 3 nm (see FIG. 2). .

  Therefore, in the present invention, the recess gate structure is not formed by using dry etching, but the first AlGaN layer 1 and the second AlGaN layer 20 are epitaxially grown to form the recess gate structure.

  Here, since the epitaxial growth rate of the AlGaN crystal is about 1 nm / min, which is slower than the dry etching rate (about 1 nm / s), the controllability of the growth of the AlGaN crystal is good, and in-plane variation (1 of the target epitaxial growth amount) %) Can be significantly reduced as compared with the case of using dry etching (about 10% of the target etching amount).

  FIG. 15 shows the relationship between the thickness (nm) of the first AlGaN layer 1 of the recessed gate type HFET manufactured according to the present invention and the threshold voltage (V). As shown in FIG. 15, when the thickness of the first AlGaN layer 1 of the recessed gate type HFET manufactured according to the present invention is controlled in the range of 1 nm to 3 nm, the recessed gate type HFET manufactured according to the present invention. Will have normally-off characteristics.

  In the present invention, since the first AlGaN layer 1 is formed by epitaxial growth, the in-plane variation can be about 1% of the target epitaxial growth amount. Therefore, in the present invention, for example, by setting the epitaxial growth amount of the first AlGaN layer 1 to 2 nm, the thickness of the first AlGaN layer 1 is in the range of 2 nm ± 0.02 nm even if in-plane variation is taken into consideration. Since it can be controlled, the recessed gate type HFET manufactured according to the present invention stably exhibits normally-off characteristics (the current between the source and the drain becomes 0 when the gate voltage Vg = 0 V).

  In the present invention, since the in-plane variation in the thickness of the first AlGaN layer 1 can be reduced, the variation in the gate voltage (threshold voltage) for flowing a current between the source and the drain can also be reduced.

(Embodiment 2)
First, as shown in the schematic sectional view of FIG. 8, the buffer layer 4 is formed on the substrate 5. Then, the GaN layer 3 is formed on the buffer layer 4 (first step).

  Next, as shown in the schematic cross-sectional view of FIG. 9, the first AlGaN layer 1 is formed on the GaN layer 3 so that the thickness T1 of the first AlGaN layer 1 is 1 nm or more and 3 nm or less ( Second step).

  Next, as shown in the schematic cross-sectional view of FIG. 10, a photoresist mask 19 patterned into a predetermined shape is formed on the surface of the first AlGaN layer 1.

  Here, the photoresist mask 19 has openings 19a in respective formation regions of a source electrode, a gate electrode, and a drain electrode, which will be described later, and the surface of the first AlGaN layer 1 is formed from each opening 19a. It is formed to be exposed.

  Then, as shown in the schematic cross-sectional view of FIG. 11, a selective growth mask 9 made of a silicon oxide film and / or a silicon nitride film is formed on the photoresist mask 19 to a thickness of about 50 nm, for example, by the CVD method. .

  Thereafter, by removing the photoresist mask 19, the selective growth mask 9 formed on the photoresist mask 19 is also removed by lift-off, and the selective growth is applied only to the gate electrode formation region on the surface of the first AlGaN layer 1. The mask 9 is left.

  Subsequently, as shown in the schematic cross-sectional view of FIG. 12, AlGaN is regrown on at least a part of the surface of the first AlGaN layer 1 other than the region protected by the selective growth mask 9. Thus, the second AlGaN layer 20 is formed (third step).

  Then, as shown in the schematic sectional view of FIG. 13, the selective growth mask 9 is removed. Here, AlGaN crystals are not grown on the surface of the selective growth mask 9 or amorphous AlGaN is formed, but even when amorphous AlGaN is formed, it is easily removed by lift-off or the like. be able to.

  Thereafter, as shown in the schematic cross-sectional view of FIG. 14, the source electrode 6 is formed on the removed portion of the selective growth mask 9 on the surface of the first AlGaN layer 1 (the portion where the second AlGaN layer 20 is not formed). Then, the gate electrode 7 and the drain electrode 8 are respectively formed (fourth step).

  In the present invention, a recessed gate type HFET can be manufactured by the method including the above steps.

  In the recessed gate type HFET manufactured according to the second embodiment of the present invention, in addition to the effects described in the first embodiment, the thickness of the AlGaN layer immediately below the source electrode 6 and the drain electrode 7 is the same as in the first embodiment. Since it can be made thinner than the fabricated recessed gate HFET, the on-resistance can be reduced as compared with the recessed gate HFET fabricated in the first embodiment.

  This is because the distance between the source electrode 6 and the drain electrode 7 and the two-dimensional electron gas layer 2 in the recessed gate type HFET manufactured according to the second embodiment of the present invention is larger than that in the first embodiment. This is because it can be shortened.

  In addition, when the thickness of the entire AlGaN layer (the first AlGaN layer 1 and the second AlGaN layer 20) is reduced, the two-dimensional electron gas concentration in the two-dimensional electron gas layer 2 tends to be low. It is preferable to reduce the thickness of only the AlGaN layer immediately below each of the source electrode 6 and the drain electrode 7.

Other explanations in the second embodiment are the same as those in the first embodiment.
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the method for manufacturing a recessed gate type HFET of the present invention, a recessed gate type HFET having normally-off characteristics can be manufactured stably.

  Therefore, the recessed gate type HFET manufactured according to the present invention stably has normally-off characteristics and can be suitably applied to a power semiconductor device or the like.

It is typical sectional drawing illustrating a part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 1 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating a part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is typical sectional drawing illustrating another part of manufacturing process of Embodiment 2 which is an example of the manufacturing method of the recessed gate type HFET of this invention. It is a figure which shows the relationship between the thickness (nm) and threshold voltage (V) of the 1st AlGaN layer of recess gate type HFET manufactured by this invention. It is typical sectional drawing of the typical structure of the conventional recessed gate type HFET.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 1st AlGaN layer, 2 2D electron gas layer, 3 GaN layer, 4 buffer layer, 5 substrate, 6 source electrode, 7 gate electrode, 8 drain electrode, 9 mask for selective growth, 10 sapphire substrate, 11 low temperature GaN Buffer layer, 12 undoped GaN layer, 13 n-type AlGaN layer, 14 n + -type AlGaN layer, 19 photoresist mask, 19a opening, 20 second AlGaN layer.

Claims (4)

A method of manufacturing a recessed gate type HFET having a heterojunction between a gallium nitride layer and an aluminum gallium nitride layer on a substrate, and a gate electrode formed on the aluminum gallium nitride layer,
A first step of forming a gallium nitride layer on the substrate;
A second step of forming a first aluminum gallium nitride layer on the gallium nitride layer to a thickness of 1 nm to 3 nm;
A third step of re-growing a second aluminum gallium nitride layer on at least a part of the surface of the first aluminum gallium nitride layer other than the gate electrode formation region;
A fourth step of forming a gate electrode in a gate electrode formation region on the surface of the first aluminum gallium nitride layer;
A method of manufacturing a recessed gate type HFET.   2. The method of manufacturing a recessed gate type HFET according to claim 1, wherein in the third step, the second aluminum gallium nitride layer is formed to a thickness of 10 nm or more. This is a method for manufacturing a recessed gate type HFET having a heterojunction portion of a gallium nitride layer and an aluminum gallium nitride layer on a substrate and having a source electrode, a drain electrode and a gate electrode formed on the aluminum gallium nitride layer, respectively. And
A first step of forming a gallium nitride layer on the substrate;
A second step of forming a first aluminum gallium nitride layer on the gallium nitride layer to a thickness of 1 nm to 3 nm;
A second aluminum gallium nitride layer is formed by regrowth on at least a part of the surface of the first aluminum gallium nitride layer other than the formation region of each of the source electrode, the drain electrode, and the gate electrode. A third step;
A fourth step of forming a source electrode, a drain electrode and a gate electrode on the surface of the first aluminum gallium nitride layer,
A method of manufacturing a recessed gate type HFET.   4. The method of manufacturing a recessed gate type HFET according to claim 3, wherein, in the third step, the second aluminum gallium nitride layer is formed to a thickness of 10 nm or more.

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